design

Edited by Bill Travis and Anne Watson Swager

ideas
D1 (MURS120) MBRS130 + + 100 F + 5V AT 1A 300 D2 MBRS130 (MURS120)

Push-pull driver provides isolated 5V at 1A

Ron Young, Maxim Integrated Products, Sunnyvale, CA
he circuit in Figure 1 converts a regulated 5V input to an Figure 1 isolated 5V output with 1A current-output capability. IC1, a pushpull transformer driver, powers a pair of cross-coupled power MOSFETs in a flipflop-like configuration. In turn, the MOSFETs toggle the primary winding of a forward transformer. The transformers secondary output, after rectification and filtering, provides the isolated 5V supply. Because the output voltage is unregulated, its voltage tolerance depends on the input-voltage range and the range of load current. With Schottky rectifiers, such as the MBRS130 for D1 and D2, the circuit delivers 5V 10% at 700 to 1000 mA from a 5V 5% input with 80% efficiency (Figure 2). Using ultrafast-recovery silicon rectifiers, such as the MURS120, the circuit delivers 5V 10% at 200 to 500 mA from a 5V 5% input, with 77% efficiency. (DI #2502)

T1 (COILTRONICS) CTX03-14439

5V 100 F

MMDF3N03HD 300

1 2 3 4 MAX253 IC1

8 7 6 5 0.1 F 5V

A simple circuit produces a 5V, 1A isolated output from a 5V regulated input.

To Vote For This Design, Circle No. 366

Push-pull driver provides isolated 5V at 1A ..........................................101 Circuit programs Atmel AVR Cs ............102 Circuit adds latch-off current limit to regulator ..........................................104 Dual power supply delivers 8A with no heat sinks..................................106 Power switch provides soft start ..............108 Circuit eliminates PC echoes ....................110 Clamping circuit dissipates minimal power..............................................112 Piezo crystal monitors liquid level............112 Switch intelligently controls current ........114

90 SCHOTTKY 80 ULTRAFAST 70 60 EFFICIENCY (%) 50 40 30 20 10 0 100 200 300 400 500 600 700 800 IOUT (mA) 900 1000 1100 1200 1300 MURS120 MBRS130

Figure 2
The efficiency of the circuit in Figure 1 depends directly on the forward drops of the output rectifiers.

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March 30, 2000 | edn 101

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ideas

Circuit programs Atmel AVR Cs

Guo-Yin Xu, XuMicro, Houston, TX
tmel AVR Cs feature an enhanced RISC architecture that purportedly offer the highest MIPS-per-milliwatt capability in the 8-bit C market. Figure 1 shows an easy-to-build AVR C-programming circuit that can program the 40-pin AT90S4414/8515, the 20-pin AT 90S1200/2313, and the eight-pin AT 90S2323/2343. The programmer uses only three chips. It connects to the host PCs serial port via a MAX232 RS-232 transceiver, IC1. Power comes from a 9V wall cube and the 78L05 linear regulator, VR1. The AT89C4051 C (IC2) works with the 11.0592-MHz oscillator, and controls all programming tasks. LED1 indicates the programmers status. The circuit exploits the fact that all AVR Cs

have a built-in SPI (serial-peripheral-interface) port that you can use to effect serial programming. The SPI port uses only the system-clock (SCK), master-output/ slave-input (MOSI), and master-input/ slave-output (MISO) pins. The AVR data book requires that, to place a C in serial-programming mode, you must first pull the Reset and SCK pins low (Reference 1). Then, the C must execute a programming-enable instruction before it can execute any program of erase instructions. Hence, you need four pins to control the programming of a C. For instance, the control signals from the AT89C4051 port pins P1.4 to P1.7 are for 40-pin Cs, the signals from P1.0 to P1.3 are for 20-

pin Cs, and the signals from P3.2 to P3.5 are for eight-pin Cs. Note that you need pullup resistors for the AT89C4051 port pins P1.0 and P1.1, because these pins normally serve as analog-signal-input lines. Jumper JP1 controls the 5V power supply for 20- and eight-pin Cs. You should remove the jumper when programming 40-pin Cs, which use a hard-wired connection to the 5V power. The circuit uses two 4-MHz ceramic resonators: CR2 for 20-pin Cs, and CR/CR3 for 40- or eight-pin Cs. Because the wires for the resonators should be as short as possible, the circuit uses no switching or jumping mechanisms. Instead, it uses one more resonator, CR2 thats hard-wired to pins 4 and 5 of the

VR1 5V 9V DC 78L05 + C1 10 F C2 0.1 F 20 1 + R1 330 C3 4.7 F LED1 P1.7 11 5V P3.7 P1.6 P1.5 P1.4 C4 + 10 F 1 C6 + 4.7 F 16 2 4 + C5 10 F P1.3 P1.2 C7 4.7 F P1.1 12 6 CR/CR3 4 MHz CR2 4 MHz VCC RST IC2 AT89C4051 19 18 17 16 MOSI MISO SCK RESET R2 10k R3 10k VCC 1 2 3 4 5 6 7 8 9 10 15 14 13 RESET2 11 12 13 14 15 16 P3.2 RESET3 17 18 19 20 5V 5 XTAL1 7 P3.3 8 P3.4 9 P3.5 1 2 3 4 5 6 7 8 9 10 GND 1 2 3 4 8 7 6 5 20 19 18 17 16 15 14 13 12 11 40-PIN ZIF SOCKET 40 39 38 37 36 35 34 33 32 31 30 29 VCC2 SCK2 C9 0.1 F JP1

Figure 1

TO PC SERIAL PORT COM1 2 3

IC1 3 MAX232 5

J1

7 8

9 10 6

OSC1 11.0592 MHz GND 10

Exploit the power of Atmels AVR Cs, using this easy-to-build programmer.

102 edn | March 30, 2000

15

28 MISO2 27 MOSI2 26 25 24 23 22 21 MISO3 MOSI3 VCC3 SCK3

2 3 C8 4.7 F

P1.0 RX TX

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contains the host-PC communication program. You can download these routines from EDNs Web site, www.ednmag.com. Click on Search Databases and then enter the Software Center to download the file for Design Idea #2504. (DI #2504) References 1. 8-bit RISC Microcontrollers Data Book, Atmel Corp, August 1999. 2. Xu, Guo-Yin, 8X51 EPROM/flash microcontroller programmer, Circuit Cellar Magazine, April 1998.

20-pin C pins 14 and 15 of the ZIF socket. This connection does not disturb the programming of 40-pin Cs. In addition to the hardware in Figure 1, the programmer also needs associated software. A binary file, AVRP1.BIN, holds the finished AVR-programmer software, burned into the AT89C4051 C by using an 8X51 EPROM/flash C programmer (Reference 2). A DOS file, AVRP1.EXE,

To Vote For This Design, Circle No. 367

Circuit adds latch-off current limit to regulator

Craig Varga, Linear Technology Corp, Milpitas, CA
n many applications, forcing a highcurrent power supply to latch off if a sustained fault condition exists can minimize the likelihood of damage to the pc-board traces and the power devices in the supply. Pulse-width-modulation (PWM)-control circuits provide no latch-off feature, but the circuit in Figure 1 does. The circuit is based on IC1, an LTC1430 PWM controller. The currentlimiting feature of the IC operates by sensing the voltage across the high-side MOSFET and compares it with a threshold voltage developed across R3. If an overcurrent condition exists, an internal current source starts to discharge the

soft-start capacitor, C9. At this point, the latch-off circuit begins to take over. When the voltage across C9 decreases to a couple of volts below VCC, Q2 turns on and begins to source current, charging C12. After a time interval depending on the values of R5 and C12, Q5 turns off and pulls the shutdown pin low, thereby turning off the controller. Because this action internally grounds the soft-start pin (to allow a normal soft-start cycle at turnon), the circuit remains latched in the off state. You can initiate a reset by applying a fast logic high to the reset line. C6 and C7 provide a differential pulse to the base of Q4, which discharges C12, allowing the
R1 10

regulator to restart. If you dont need the reset function, you can eliminate C6, R7, R10, and Q4. You can then initiate a restart by recycling the 5V input power. The only timing requirement is that the latch-off delay be greater than the soft-start rise time at turn-on. Otherwise, the regulator can never start. You can modify the circuit to work with any other controller, such as the LTC1553, having the soft-start function. (DI #2503)

To Vote For This Design, Circle No. 368

12V

Figure 1
C1 330 F 6.3V IC1 LTC1430 15 PV CC2 14 VCC 11 FSET 12 IMAX 8 SD 10 COMP 9 SS 4 SGND PVCC1 G1 IFB G2 PGND SENS +SENS FB 2 1 13 16 3 5 7 6 R6 1k Q3 IRF7801 L1 2.4 H + D1 MBRS130 C7 330 F C10 330 F 6.3V 6.3V + C8 330 F 6.3V OUTPUT 3.3V AT 7A E2 C15 0.1 F E1 + C4 1 F C + 1 330 F 6.3V 5V C2 C3 + 330 F + 330 F 6.3V 6.3V

OVERCURRENT LATCH-OFF CIRCUIT

C8 0.1 F R3 16k

R2 51

Q1 IRF7801

R5 15k RESET C6 0.01 F R7 10k Q5 Q4 2N3904

R4 10k Q2 TP0610T

C9 0.01 F

R9 2N3904 20k C12 1 F C11 220 pF

R8 13k C14 1500 pF + C13 22 F 35V

R10 10k

R11 10k

You can add a latch-off current-limiting feature to a simple pulse-width-modulation controller by adding a few external components.

104 edn | March 30, 2000

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Dual power supply delivers 8A with no heat sinks

John Seago, Linear Technology Corp, Milpitas, CA
he circuit in Figure 1 is a high-current dual supply that provides 5 and 3.3V at currents as high as 8A. The circuit uses a fixed-frequency, two-output, current-mode synchronous-buckcontroller, IC1, to regulate both 5 and 3.3V outputs. The circuit uses separate regulator circuits for each output voltage. However, both circuits are identical except for the lower feedback resistors, R4 and R7, which determine the 5 and 3.3V output voltages, respectively. IC1 regulates the 5V output, VOUT1, by

controlling the duty cycle of the top MOSFET for VOUT1, Q1, so that average input voltage to the buck inductor, L1, is equal to the output voltage. The buck inductor and output capacitors C3 to C5 three 330- F capacitors in parallelintegrate and filter the energy pulses from Q1 to generate the dc output. After Q1 turns off, the bottom MOSFET for VOUT1, Q2, turns on to conduct inductor current to the load. To avoid shoot-through current, a short dead time occurs before each MOSFET turns on. During this dead

time, inductor current flows through the commutating diode, D1, to the load. Feedback resistors R3 and R4 connect IC1s internal error amplifier to the output. Loop-compensation components R1, C1, and C2 control the frequency response of the error amplifier. The internal current comparator senses inductor current by the voltage developed across the current-sense resistor, R2. The 3.3 regulator, which produces VOUT2, functions exactly like the 5V regulator. Q3 and Q4 are the top and bottom

Figure 1
47k

0.1 F

MMSD0.1 F 914 C1 1000 pF

10 10 1 1000 pF 2 SENSE 1 3 4 5 82 pF 6 7 8 VOSENSE1 ITH1 POR2 COSC SGND LBI LBO SFB1 ITH2 VOSENSE2 SENSE 2 SENSE+2 IC1 LTC1438-ADJ SENSE+1 RUN/SS1 BOOST 1 TGL1 SW1 VIN BG1 INTVCC PGND BG2 EXTVCC SW2 TGL2 BOOST 2 RUN/SS2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.1 F 10 0.1 F C14 TO C16 + 330 F 35V 3 VIN2 5.5 TO 2.8V CMDSH-3 0.1 F Q4 L2 5.2 H R6 0.01 R8 35.7k 1000 pF 1 F + 0.1 F CMDSH-3 Q2 L1 5.2 H D1 Q3 D2 C3 TO C5 330 F + 6V, 3 C8 TO C10 330 F 6V, 3 Q1 R2 0.01 10 0.1 F 0.1 F 50V VIN1 5.5 TO 28V

R1 2.2k POR2

C2 2200 pF

C11 TO C13 + 330 F 50V 3

1M 280k

R3 35.7k R4 11.0k

1000 pF 100 pF

VOUT1 5V/8A 1 F 10V

4.7 F 10V

LB0 C6, 1000 pF C7, 2200 pF R5 2.2k 47k

9 10 11 12 13 14 1000 pF MMSD914 10

R7 20.0k

100 pF 1 F 10V VOUT2 3.3V/8A

0.1 F NOTES: C11 TO C13, C14 TO C16=SANYO 35CV330GX. C3 TO C5, C8 TO C10=KEMET T495X337M006AS. D1, D2=MOTOROLA MBRD835L. L1, L2=PULSE ENGINEERING PE-53700. Q1, Q4=SILICONIX SUD50N03-10. Q2, Q3=SILICONIX Si4420DY. R2, R6=IRC LRF2512-01-R010-J.

A single IC regulates both 5 and 3.3V outputs; each output delivers 8A.

106 edn | March 30, 2000

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high but goes low when the input voltage is low. IC1 includes a complete power-onreset circuit. At startup, the POR2 pin is low. This pin goes high 65,536 oscillator cycles after Channel 2s output voltage reaches 95% of its programmed value. The POR2 pin goes low if the output voltage falls 7.5% from nominal. Each output has a RUN/SS pin that provides output-voltage delay, output-current soft-start, and on/off control. The value of the capacitor connected to the RUN/SS pin determines the output voltage delay and the inductor-current ramp time, both at a rate of 0.5 sec/ F. Pulling a RUN/SS pin low turns off that output voltage. Pulling both RUN/SS pins low shuts down IC1, turns off all internal circuitry, and limits the input current to 16 A. (DI #2494) To Vote For This Design, Circle No. 369

MOSFETs, respectively, and L2 is the buck inductor. D2 is the commutating diode. Feedback resistors R7 and R8 connect the error amplifier to the output. R5, C6, and C7 are the loop-compensation components, and R6 is the sense resistor. C8, C9, and C10 make up the output capacitor. The circuit in Figure 1 has some features that add versatility. The low-battery comparator in IC1 flags a low-input-voltage condition. Normally, the LBO pin is

Power switch provides soft start

John Haase, Colorado State University, Fort Collins, CO
n the circuit in Figure 1, series-connected MOSFETs turn on the line voltage near the zero-crossing point and off when the 555-timer delay lapses. That delay ranges from 1 to 7 msec. The MOSFETs body diodes and the 1N4005 diodes form a full-wave bridge rectifier that provides a floating 12V-dc level via the 10-k , 3W resistor. The bridge simultaneously delivers the crossing signal

to 2N2906 common-base comparator. When the emitter current approaches zero, the collector voltage falls to 4V and triggers the delay timer, initiating gate drive to the switches. Positive-going pin 3 of the 555 also removes the trigger threshold by coupling to the diode OR gate. Because the circuit generates the 12V operating voltage only during offtime, the limit for maximum delay is ap-

proximately 7 msec.You trim the delay by selecting a resistance value from Pin 5 to raise (pins 5 to 8) or lower (pins 5 to 1) the upper comparator threshold at Pin 6. Thus, load power is from 0 to 90% of maximum (600W). You must use a heat sink for the power MOSFETs. (DI #2506).
To Vote For This Design, Circle No. 370

Figure 1
N

1N4005

1N4005 RLOAD L

IRFP264

IRFP264

10

10 6.8k CW

10k 3W

2N3906 47k 3

4 50k 5

TLC555CP

47 F + 25V

1N5242B 100k 470k

2 1

6 7 0.1 F

NOTE: VL,N=115V AC AT 60 Hz.

This smart switch provides a small initial current for loads with a normally high inrush current.

108 edn | March 30, 2000

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6V and closes with a gate voltage of 0V. Q3 compensates for the switching-circuit losses and buffers the output. R9 and R10 provide an appropriate input impedance to Q3 and limit the output to 5V p-p, thus preventing any possible damage to the PCs microphone input. IC1, which acts as low-level retriggerable monostable multivibrator, controls the Q2 FET switch. Loudspeaker voltage levels as low as 15 mV from the PC cause comparator IC1As open-collector output to discharge C6 via R18. The falling voltage of C6, passing the threshold of comparator IC1B, produces a high output that turns off Q2. Any input from the PCs loudspeaker output discharges C6. The absence of an input allows C6 to charge within approximately 40 msec to the IC1B threshold, producing a low-level output and turning on Q2. LED D2 lights whenever no loudspeaker output is present, and the microphone input to the PC becomes enabled. D1 reduces the Q2 gate voltage to 0V when the IC1B output saturates. You should set R1 such that approximately a 100-mV p-p microphone input just triggers IC1, as indicated by the LEDs extinguishing. This level prevents any noise from the PCs loudspeaker output from falsely triggering the monostable multivibrator. (DI #2508).

Circuit eliminates PC echoes

Hans Krobath, EEC, Nesconset, NY
ong-distance-telephone services available via the Internet often require the PC user to wear headphones of a headset to prevent echo caused by the microphones picking up the loudspeaker outputs. The circuit in Figure 1 eliminates the echo while using the existing PC microphone and speakers for a comfortable conversation. The interface is between a standard electret condenser microphone and the microphone input of the PC. The loudspeaker output of the PC serves to mute the microphone input. R1 and R2 provide biasing for both the electret microphone and the Q1 emitter follower. Q2, a p-channel FET, acts as a switch that opens with the application of a gate voltage greater than

To Vote For This Design, Circle No. 371

Figure 1
R1 27k Q1 2N3904 C2 0.1 F R3 1k

12V

C1 + 150 pF J1

R9 1.5k Q2 2N5460 S D R7 10k R6 1M C3 0.1 F Q3 2N3906

R10 2k

R4 10k

FROM PC MIC

R2 20k

R5 1M

C4 0.22 F R8 360k R11 2.4k

J2 R12 10k TO PC MIC INPUT

12V

R15 10M

J3 X

R14 22k C5 0.1 F R13 1k

R19 IC1A 8 LM393N 2.2M 3 + 1 2 R18 4 1k R16 20k R17 20k

R20 220k

R21 220k 5 + 6 8

R22 10M

R23 10k

R24 4.7k

TALK D2 LED

7 D1 1N4148

IC1B 4 LM393N

R25 150k

C6 0.022 F

FROM PC SPEAKER

SET TO 100-mV P-P THRESHOLD

Eliminate annoying echoes from loudspeaker-microphone feedback by using this simple circuit.

110 edn | March 30, 2000

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Q2). For input voltages that exceed VR3s breakdown voltage by approximately 3V, R6 and VR3 dissipate the energy the charge pump supplies. In this mode, the circuit functions as a source follower, and the output voltage is approximately 3V lower than VR3s breakdown voltage. The circuit dissipates minimal power. During transients, the load current determines the dissipation in Q2. (DI #2499)

Clamping circuit dissipates minimal power

Carlisle Dolland, Allied Signal Aerospace, Torrance, CA
Q2 he circuit in Figure 1 D S is a quasi-linear regulator. It functions as a C3 Q1 G source follower for input VIN D2 R6 voltages greater than a preset VR3 level, determined by VR3. R1 R2 R4 For input voltages lower R5 than the preset level, the pass 8 R3 VR1 7 4 element, Q2, operates as a + C2 6 3 saturated switch. The circuit 2 _ IC1 comprises an oscillator, a ICM7555MTV C1 1 charge pump, and a linear regulator. The linear Figure 1 regulator, consisting of Q1, R1, VR1, and R2, drives a charge pump comprising This circuit clamps transient voltages and dissipates minimal power. C2, D2, D3, and C3. The charge pump generates a voltage equal to voltage of VR1. For input voltages lower the output of the linear regulator for in- than VR1s breakdown voltage, the output voltages greater than the breakdown put voltage is VOUT VIN IOUT (RON of

VOUT D3

To Vote For This Design, Circle No. 372

Piezo crystal monitors liquid level

J Jayapandian, IGCAR, Tamil Nadu, India
he simple and inexpensive circuit in Figure 1 monitors the liqFigure 1 LIQUID uid level in a container. The piezo crystal, carefully mounted at the bottom surface of the container, receives it activation from the 74HCT14 hex DATA BUS 6.14 MHz CRYSTAL VCC Schmitt trigger. The crystal generates stable clock pulses according to its specifiCONTAINER CLOCK 0 74HCT14 cation (for example, 6.14 MHz) when it is in free air. The crystal-based clock 0TH COUNTER GATE 0 drives the 0th counter in an 8254 programmable-counter/timer chip, pro1k 1k OUT 1 FIRST COUNTER 56 pF grammed in Mode 0 as an event count8254 er. The first counter of the 8254, CLOCK 1 programmed in Mode 1 as a retriggerable SECOND COUNTER one-shot whose time period is 1 sec, controls the gate of the 0th counter. The first counter allows the 0th counter to count CS WR RD A0 A1 for a period of 1 sec. The counts in the air medium serve as a reference. Depending By measuring frequency shifts, this circuit provides a measure of liquid level. on the height of the liquid level, the pressure acting on the surface of the crystal To Vote For This Design, increases, thereby reducing reference- medium reference gives you the height of Circle No. 373 crystal clock frequency. The variation in the liquid level. (DI # 2507) clock frequency with respect to the air-

112 edn | March 30, 2000

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Switch intelligently controls current

Jim Hartmann, Silent Knight LLC, Maple Grove, MN
V DC he circuit in Figure 1 can intelligently control ac or dc current Figure 1 VZC D1 when connected in series with D2 D1N4002 OPTIONAL ZEROVDUTY D1N4002 a load. The circuit steals its power by CROSSING INPUT turning off the load at a low duty cycle. Q2 Q1 VCC 2N7002 The switch uses the MOSFETs parasitic 2N7002 body diode to its advantage. While the RLOAD VREG CONTROL + MOSFETs are off, the body diodes, along C1 C2 V AC with D1 and D2, serve as two legs of a diode bridge. Current flows through the 0 load and the bridge, charging C1 to the peak ac or dc voltage. The relatively small With a control circuit of your choice, you can obtain intelligent control of ac or dc current. control-block supply current continues to flow through the load when the load the MOSFETs on-resistance. maximum duty cycle is 99.9%. By choosis turned off. The circuit has low inserWhile the load is turned on, the con- ing MOSFETs and diodes with higher tion loss because of the MOSFETs bidi- trol block draws current from C1. The cir- current ratings, you can adapt the circuit rectional nature. The control block con- cuit must periodically recharge C1 by to control high-power loads. Many apnects power to the load by turning briefly turning off the load . You can al- plications are possiblelamp dimmers MOSFETs Q1 and Q2 on. On alternating low the duty cycle to go as high as 99.99% and thermostats, for example. The concycles, either Q1 or Q2 becomes reverse- with a high-current load and a micro- troller can optionally synchronize to the biased, but current does not flow through power control circuit. The maximum ac zero-crossing point as shown. (DI # the body diode because the MOSFET can duty cycle is approximately ILOAD/(ICON- 2505) To Vote For This Design, conduct in either direction. The insertion TROL ILOAD). For example, with a 1A load Circle No. 374 loss is equivalent to the loss in two times and a control-circuit current of 1 mA, the

Design Idea Entry Blank

Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design, selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine 275 Washington St, Newton, MA 02458 I hereby submit my Design Ideas entry. Name Title Phone E-mail Company Fax Entry blank must accompany all entries. (A separate entry blank for each author must accompany every entry.) Design entered must be submitted exclusively to EDN, must not be patented, and must have no patent pending. Design must be original with author(s), must not have been previously published (limited-distribution house organs excepted), and must have been constructed and tested. Fully annotate all circuit diagrams. Please submit text and listings by e-mail to b.travis@cahners.com or send a disk. Exclusive publishing rights remain with Cahners Publishing Co unless entry is returned to author, or editor gives written permission for publication elsewhere. In submitting my entry, I agree to abide by the rules of the Design Ideas Program. Signed Country Design Idea Title Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
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114 edn | March 30, 2000