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Hafiz Md. Hasan Babu and Ahsan Raja Chowdhury Department of Computer Science and Engineering University of Dhaka Dhaka, Bangladesh. E-mail: hafizbabu@hotmail.com, farhan717@yahoo.com
Abstract
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.
Fan-out is not permitted Loops are not permitted. Synthesis of reversible logic is significantly different from conventional logic synthesis [11]. Since loops are not permitted, a reversible logic circuit can be specified as a simple sequence of gates. Further since fanout is not permitted, and assuming an appropriate technology, a reversible logic circuit can realize the inverse specification simply by applying the gates in the reverse order. Hence, synthesis can be carried out from the inputs towards the outputs or from the outputs towards the inputs. Traditional design methods use, among other criteria, the number of gates as complexity measure (sometimes taken with some specific weights reflecting are of the gate). From the point of view of reversible logic we have one more factor, which is more important than the number of gates used, namely the number of garbage outputs. The unutilized outputs from a reversible gate/circuit are called garbage. Though every synthesis method engages them producing less number of garbage outputs, but sometimes garbage outputs are unavoidable. For example, a single output function of n variables will require at least n-1 garbage outputs, since the reversibility necessitates an equal number of outputs and inputs. In this paper, we have proposed a reversible circuit named as Reversible Binary Coded Decimal (BCD) adder that poses all the good features of reversible logic synthesis. The restrictions of reversible circuits were highly avoided and use of gates was minimal. We have succeeded to restrict the number of garbage outputs as fewer as possible. This paper is organized as follows: Section 2 provides the necessary background on reversible logic along with the examples of popular reversible logic gates. Section 3 provides the synthesis of reversible circuits. Proposed design technique for reversible BCD adder is thoroughly discussed in Section 4. The paper concludes with observations and suggestions for further study in Section 5. Section 6 mentions the references needed in this paper.
1. Introduction
Loss of energy is an important consideration in digital design. Part of the problem of energy dissipation is related to non-identity of switches and materials. Higher level of integration and the use of new fabrication processes have dramatically reduced the heat loss over the last decades. The other part of the problem arises from Landauers principles [1,6] state that, logic computations that are not reversible, necessarily generate heat kT*ln2 for every bits of information that is lost, where k is the Boltzmanns constant and T is the temperature. For room temperature T, the amount of dissipating heat is small (i.e. 2.9* 10-21 joules) but not negligible. The design that doesnt resulting information loss called reversible. Reversible are circuits (gates) in which the number of inputs is equal to the number of outputs and there is a one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can always be re-constructed from the vector of output states. More formally, a reversible logic gate is a k-input, k-output (denoted k*k) device that maps each possible input pattern into a unique output pattern [2,3,4]. While constructing reversible circuits with the help of reversible gates, some restrictions should be strictly maintained [2,3]:
Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID05) 1063-9667/05 $20.00 2005 IEEE
Definition 2.5: Let Iv and Ov be the input and output vector of a 3*3 Fredkin Gate [8,12] respectively, where Iv=(A,B,C) and Ov=(P=A,Q=A B AC , R=A C AB). Example 2.5: Fig. 2.3 shows the block diagram of 3*3 Fredkin gate.
Definition 2.6: A 3*3 New Gate (NG) [7] can be defined as Iv=(A, B, C) and Ov=(P=A,Q=AB C , R=A C B ), where Iv and Ov are the input and output vector respectively. Example 2.6: The block diagram of a 3*3 New gate is shown in Fig. 2.4.
One extra output should be produced to make the circuit reversible and that unwanted output (P=A, marked as *) is known as garbage. Now we will define some popular reversible gates where most of them will be used in our proposed design. Definition 2.2: 1*1 NOT gate is the simplest among all the reversible gates where the gate has only one input (A) and one output (B) such that B = A . Example 2.2: The truth table for the gate is given in Table 2.1.
Table 2.1. Truth table for 1*1 NOT gate.
Definition 2.7: A 3*3 New Toffoli Gate (NTG) [4] can be defined as Iv =(A,B,C) and Ov=(P=A,Q= A B,R=AB C) where Iv and Ov are the input and output vector respectively. Example 2.7: Fig. 2.5 shows the block diagram of 3*3 New Toffoli Gate (NTG).
A 0 1
B 1 0
Definition 2.3: Let Iv and Ov be the input and output vector of a 2*2 Feynman gate (FG) [9,10] respectively, where Iv=(A,B) and Ov=(P=A, Q=A B). Example 2.3: The block diagram for 2*2 Feynman gate is shown in Fig.2.1. Definition 2.4: Let Iv and Ov be the input and output vector of a 3*3 Toffoli Gate (TG) [8,11] respectively, where Iv =(A, B, C) and Ov=(P=A, Q=B,R=AB C). Example 2.4: Fig. 2.2 shows the 3*3 Toffoli gate.
Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID05) 1063-9667/05 $20.00 2005 IEEE
Feynman gates can be used as copying circuits, the same way as in the spy circuits, to increase the fan-out. We have already succeeded to design reversible circuits overcoming the constraints of the reversible logic synthesis [2,3,4] and in the proposed circuits the constraints are carefully abided.
(decimal 6) should be added with the previous addition result (S3S2S1S0) to calculate the final result. In this case, a carry will be generated that directs the overflow of the addition. In another case, if X is 0, no modification will occur in the previous addition.
Definition 4.1: When all the decimal numbers are represented as the four bits binary number of each decimal digit, the representation scheme is known is Binary Coded decimal or BCD [5]. Though 16 distinct digits can be represented in 4 bit binary numbers, only the first ten numbers (0000 to 1001) are valid in BCD system. Example 4.1: 0010 1001 is a valid BCD number that is equivalent to 29 in decimal system, but 0101 1010 is not valid as 1010 cant be represented with the help of one decimal digit. Definition 4.2: A BCD adder is a special type of adder that adds two BCD numbers and converts the result into its equivalent BCD number [5]. The conversion is required because of overflow of the addition. Definition 4.3: A BCD adder is special type of adder that can only add two BCD numbers successfully. Example 4.2: A BCD adder will produce 1001 after adding 0101 and 0100. In another case, the addition of 0101 and 0111 will be 1100, that is converted into 0001 0010 by BCD adder, as 1100 (12 in decimal) cannot be represented with one decimal digit. For error correction purpose, a combinational logic should be used in a BCD adder that will control the overflow of the result of the addition of two BCD number. Let A3A2A1A0 and B3B2B1B0 be the two BCD numbers, S3S2S1S0 is the addition of two BCD numbers A and B, and C4 is carry of the addition. In the combinational logic, S3,S2,S1 and C4 should be checked for error correcting purpose. The equation will directly control the errorcorrecting module X = C4+(S1+S2).S3. If X is 1, 0110
Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID05) 1063-9667/05 $20.00 2005 IEEE
2. 3.
4.
5. 6.
To comprehend the above algorithm clearly, we have presented each step in different figures. According to the algorithm, the design of the reversible BCD adder has been shown as follows: Fig. 4.3.1 (Step 1), Fig. 4.3.2 (Step 2), Fig. 4.3.3 (Step 3), Fig. 4.3.4 (Step 4), Fig. 4.3.5 (Step 5), and Fig. 4.3.6 (Step 6). The final circuit, reversible BCD adder, is presented in Fig. 4.3.7.
Figure 4.3.4. 4-bit reversible parallel adder with two 4-bits variable A and B.
Figure 4.3.5. Combinational logic for BCD adder with appropriate inputs that produces 6 garbage outputs. Figure 4.3.1. A reversible full-adder circuit with only 2 reversible gates, i.e., one New Gate and a New Toffoli Gate that generates only 2 garbage outputs [4].
Figure 4.3.2. 4-bits reversible parallel adder with the cascade of four reversible full-adder.
Figure 4.3.6. Second 4-bit parallel reversible adder with the output of the combinational logic.
Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID05) 1063-9667/05 $20.00 2005 IEEE
=22. In our proposed circuit, we use four reversible fulladder circuits to construct a reversible 4-bit parallel adder; total 8 reversible gates are required to construct a 4-bit reversible adder. Combinational Logic (((S1+ S2)* S3) +C4) requires three New gates (NG) in our proposed reversible BCD adder. Three Feynman gates are required for copying S1, S2, and S3 to avoid fan-out of those bits. Finally, another Feynman gate is required for copying the result of combinational logic ((S1+ S2)* S3) + C4). As a result, the total number of gates required to construct a reversible BCD adder is 2*8 + 3 + 4=23.
6. References
[1] Bennett, C., Logical Reversibility of Computation, IBM Journal of Research and Development, 17, 1973, 525-532. [2] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, Reversible Logic Synthesis for Minimization of Fulladder Circuit, IEEE Conference on Digital System Design 2003, Euro-Micro03, Belek, Antalya, Turkey, 2003, pp. 50-54. [3] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, Synthesis of Full-adder Circuit Using Reversible Logic, 17th International Conference on VLSI design 2004, Mumbai, India, 2004, pp. 757-760. [4] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, On the Realization of Reversible Full-Adder Circuit, International Conference on Computer and Information Technology, Dhaka, Bangladesh, 2003, Vol. 2, pp. 880883.
In our proposed circuit, we used four reversible fulladder circuits of [4] to construct a reversible 4-bit parallel adder, and each of the full-adder circuit produces two garbage outputs. So, the total number of garbage outputs generated from the reversible 4-bit adder is 8. Combinational Logic (((S1+ S2)* S3) +C4) generates six garbage outputs in our proposed reversible BCD adder using three New gates. Feynman gates, which are used for copying bits, dont produce any garbage outputs while one copy is needed for a bit. As a result, the total number of garbage outputs required to construct a reversible BCD adder is 2*8 + 6
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[5] Ronald J. Tocci, Digital Systems- Principles and Application, New Delhi, India, 1996. [6] R. Landauer, Irreversibility and Heat Generation in the Computational Process, IBM Journal of Research Development, 5 ,1961, 183-191. [7] Md. M. H Azad Khan, Design of Full-adder With Reversible Gates, International Conference on Computer and Information Technology, Dhaka, Bangladesh, 2002, pp. 515-519. [8] E. Fredkin, T. Toffoli, Conservative Logic, International Journal of Theor. Physics, 21, 1982, pp. 219-253. [9] Milburn, Gerard J., The Feynman Processor, Perseus Books, 1998. [10] R. Feynman, Quantum Mechanical Computers, Optical News, 1985, pp. 11-20. [11] T. Toffoli., Reversible Computing, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).
[12] P.D. Picton, Fredkin Gates as the Basic for Comparison of Different Logic Designs, Synthesis and Optimization of Logic Systems, London, UK, 1994. [13] M. Perkowski, L. Jozwiak, P. Kerntopf, A Mishchenko, A. Al-Rabadi, A. Coppola, A. Buller, X Song, M. M. H. A. Khan, S Yanushkevich, V.S Shmerko, and M. Chzazowska-Jeske, A general decomposition for reversible logic, in: Proc. RM 01. [14] Andrel B. Khlopotine, M Perkowski and Pawel Kerntopf, Reversible Logic Synthesis by Iterative Composition, in: Proc. IWLS 02,pp. 261-266. [15]. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Hoque, Ahsan Raja Chowdhury, Logic Synthesis and Minimization of Boolean Functions Using TANT Network, International conference on computer and information technology 2003, 19-21, Dhaka, Bangladesh, Dec 2003, Vol-2 pp.884-889. [16]. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Hoque, Ahsan Raja Chowdhury, Heuristic approach to synthesize Boolean functions using TANT network, IEEE, International Symposium on Circuits and Systems, Vancouver, Canada, 23-26 May 2004, VLSI-L7.4, vol. II, pp. 373 376.
Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID05) 1063-9667/05 $20.00 2005 IEEE