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Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-bit Parallel Adder

Hafiz Md. Hasan Babu and Ahsan Raja Chowdhury Department of Computer Science and Engineering University of Dhaka Dhaka, Bangladesh. E-mail: hafizbabu@hotmail.com, farhan717@yahoo.com

Abstract

In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4- bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.

1. Introduction

Loss of energy is an important consideration in digital design. Part of the problem of energy dissipation is related to non-identity of switches and materials. Higher level of integration and the use of new fabrication processes have dramatically reduced the heat loss over the last decades. The other part of the problem arises from Landauer’s principles [1,6] state that, logic computations that are not reversible, necessarily generate heat kT*ln2 for every bits of information that is lost, where k is the Boltzmann’s constant and T is the temperature. For room temperature T, the amount of dissipating heat is small (i.e. 2.9* 10 -21 joules) but not negligible. The design that doesn’t resulting information loss called reversible. Reversible are circuits (gates) in which the number of inputs is equal to the number of outputs and there is a one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can always be re-constructed from the vector of output states. More formally, a reversible logic gate is a k-input, k-output (denoted k*k) device that maps each possible input pattern into a unique output pattern [2,3,4]. While constructing reversible circuits with the help of reversible gates, some restrictions should be strictly maintained [2,3]:

Fan-out is not permitted Loops are not permitted.

Synthesis of reversible logic is significantly different from conventional logic synthesis [11]. Since loops are not permitted, a reversible logic circuit can be specified as a simple sequence of gates. Further since fanout is not permitted, and assuming an appropriate technology, a reversible logic circuit can realize the inverse specification simply by applying the gates in the reverse order. Hence, synthesis can be carried out from the inputs towards the outputs or from the outputs towards the inputs. Traditional design methods use, among other criteria, the number of gates as complexity measure (sometimes taken with some specific weights reflecting are of the gate). From the point of view of reversible logic we have one more factor, which is more important than the number of gates used, namely the number of garbage outputs. The unutilized outputs from a reversible gate/circuit are called garbage”. Though every synthesis method engages them producing less number of garbage outputs, but sometimes garbage outputs are unavoidable. For example, a single output function of n variables will require at least n-1 garbage outputs, since the reversibility necessitates an equal number of outputs and inputs. In this paper, we have proposed a reversible circuit named as Reversible Binary Coded Decimal (BCD) adder that poses all the good features of reversible logic synthesis. The restrictions of reversible circuits were highly avoided and use of gates was minimal. We have succeeded to restrict the number of garbage outputs as fewer as possible. This paper is organized as follows: Section 2 provides the necessary background on reversible logic along with the examples of popular reversible logic gates. Section 3 provides the synthesis of reversible circuits. Proposed design technique for reversible BCD adder is thoroughly discussed in Section 4. The paper concludes with observations and suggestions for further study in Section 5. Section 6 mentions the references needed in this paper.

Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE

2. Background of the reversible logic gates

In this section, we describe all about reversible logic and reversible logic gates. Though it is already briefly described about garbage outputs, in this section we will define it with more appropriate examples and figures.

Definition 2.1: Garbage is the number of outputs added to make an n-input k-output Boolean function ((n, k) function) reversible. In other sense, a reversible logic gate has an equal number of inputs and outputs (k*k) and all the outputs are not expected. Some of the outputs should be considered to make the circuit reversible and those unwanted outputs are known as garbage outputs. A heavy price is paid for every garbage outputs. Example 2.1: If we want to find the Exclusive-OR between two variables in reversible computation, the circuit will look like Fig. 2.1.

rsible computation, the circuit will look like Fig. 2.1. Figure 2.1. Calculating Exclusive-OR in reversible mode.

Figure 2.1. Calculating Exclusive-OR in reversible mode.

One extra output should be produced to make the circuit reversible and that unwanted output (P=A, marked as *) is known as garbage. Now we will define some popular reversible gates where most of them will be used in our proposed design.

1*1 NOT gate is the simplest among

all the reversible gates where the gate has only one input

(A) and one output (B) such that B = A . Example 2.2: The truth table for the gate is given in Table 2.1.

Definition 2.2:

Table 2.1. Truth table for 1*1 NOT gate.

A B 01 1 0
A
B
01
1
0

Definition 2.3: Let I v and O v be the input and output vector of a 2*2 Feynman gate (FG) [9,10] respectively,

where I v =(A,B) and O v =(P=A, Q=A B). Example 2.3: The block diagram for 2*2 Feynman gate is shown in Fig.2.1. Definition 2.4: Let I v and O v be the input and output vector of a 3*3 Toffoli Gate (TG) [8,11] respectively,

where I v =(A, B, C) and

(TG) [8,11] respectively, where I v =(A, B, C) and O v =(P=A, Q=B,R=AB C). Example

O v =(P=A, Q=B,R=AB

where I v =(A, B, C) and O v =(P=A, Q=B,R=AB C). Example 2.4: Fig. 2.2

C).

Example 2.4: Fig. 2.2 shows the 3*3 Toffoli gate.

C). Example 2.4: Fig. 2.2 shows the 3*3 Toffoli gate. Figure 2.2. 3*3 Toffoli gate. Let

Figure 2.2. 3*3 Toffoli gate.

Let I v and O v be the input and output

vector of a 3*3 Fredkin Gate [8,12] respectively, where

I v =(A,B,C) and O v =(P=A,Q=A B

Example 2.5: Fig. 2.3 shows the block diagram of 3*3

Fredkin gate.

Definition 2.5:

shows the block diagram of 3*3 Fredkin gate. Definition 2.5: AC , R=A C AB). Figure

AC , R=A C

diagram of 3*3 Fredkin gate. Definition 2.5: AC , R=A C AB). Figure 2.3. 3*3 Fredkin

AB).

of 3*3 Fredkin gate. Definition 2.5: AC , R=A C AB). Figure 2.3. 3*3 Fredkin gate.

Figure 2.3. 3*3 Fredkin gate.

Definition 2.6: A 3*3 New Gate (NG) [7] can be

,

R=A C B ), where I v and O v are the input and output vector respectively. Example 2.6: The block diagram of a 3*3 New gate is shown in Fig. 2.4.

defined as I v =(A, B, C) and O v =(P=A,Q=AB

2.4. defined as I v =(A, B, C) and O v =(P=A,Q=AB C Figure 2.4. 3*3
2.4. defined as I v =(A, B, C) and O v =(P=A,Q=AB C Figure 2.4. 3*3

C

2.4. defined as I v =(A, B, C) and O v =(P=A,Q=AB C Figure 2.4. 3*3

Figure 2.4. 3*3 New gate.

Definition 2.7: A 3*3 New Toffoli Gate (NTG) [4] can be defined as I v =(A,B,C) and O v =(P=A,Q= A B,R=AB C) where I v and O v are the input and output vector respectively. Example 2.7: Fig. 2.5 shows the block diagram of 3*3 New Toffoli Gate (NTG).

2.5 shows the block diagram of 3*3 New Toffoli Gate (NTG). Figure 2.5. 3*3 New Toffoli
2.5 shows the block diagram of 3*3 New Toffoli Gate (NTG). Figure 2.5. 3*3 New Toffoli
2.5 shows the block diagram of 3*3 New Toffoli Gate (NTG). Figure 2.5. 3*3 New Toffoli

Figure 2.5. 3*3 New Toffoli Gate.

3. Synthesis of reversible circuits

The main differences of synthesizing a circuit with reversible gates [2,3,4,13], as compared to synthesizing a standard binary circuit [6,15,16] are the following:

The number of outputs of a logic gate is equal to the number of inputs. It is easy to find solutions sacrificing one or more gate outputs for garbage, but such solution are of less value. Every gate output that is not used as input to other gate or as a primary output is called garbage. A heavy price is paid for every garbage bit, if the garbage bit is left unattended, or if the mirror circuit and spy gates are added. In reversible logic, fan-out of any gate output is not allowed; every output can be used only once.

Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE

Feynman gates can be used as “copying circuits”, the same way as in the “spy circuits”, to increase the fan-out.

We have already succeeded to design reversible circuits overcoming the constraints of the reversible logic synthesis [2,3,4] and in the proposed circuits the constraints are carefully abided.

4. Proposed reversible BCD adder

In this section, we will show all the details about our proposed reversible BCD adder with the details specification of each part of this adder. The algorithm, presented in Section 4.3, is the summarization of the design technique of reversible BCD adder.

4.1 Basic definitions and terminologies

In this section, we will discuss about the properties of a Binary Coded Decimal (BCD) number and all about BCD adder.

Definition 4.1: When all the decimal numbers are represented as the four bits binary number of each decimal digit, the representation scheme is known is Binary Coded decimal or BCD [5]. Though 16 distinct digits can be represented in 4 bit binary numbers, only the first ten numbers (0000 to 1001) are valid in BCD system. Example 4.1: 0010 1001 is a valid BCD number that is equivalent to 29 in decimal system, but 0101 1010 is not valid as 1010 can’t be represented with the help of one decimal digit. Definition 4.2: A BCD adder is a special type of adder that adds two BCD numbers and converts the result into its equivalent BCD number [5]. The conversion is required because of overflow of the addition. Definition 4.3: A BCD adder is special type of adder that can only add two BCD numbers successfully. Example 4.2: A BCD adder will produce 1001 after adding 0101 and 0100. In another case, the addition of

0101

and 0111 will be 1100, that is converted into 0001

0010

by BCD adder, as 1100 (12 in decimal) cannot be

represented with one decimal digit. For error correction purpose, a combinational logic should be used in a BCD adder that will control the overflow of the result of the addition of two BCD number. Let A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0 be the two BCD numbers, S 3 S 2 S 1 S 0 is the addition of two BCD numbers A and B, and C 4 is carry of the addition. In the combinational logic, S 3 ,S 2 ,S 1 and C 4 should be checked for error correcting purpose. The equation will directly control the error- correcting module X = C 4 +(S 1 +S 2 ).S 3 . If X is 1, 0110

(decimal 6) should be added with the previous addition result (S 3 S 2 S 1 S 0 ) to calculate the final result. In this case, a carry will be generated that directs the overflow of the addition. In another case, if X is 0, no modification will occur in the previous addition.

4.2 Properties of reversible BCD adder

Some key points are considered in the design time of reversible BCD adder. First one is the number of gates that we have tried to keep as fewer as possible. Second key point is the number of garbage outputs. A 4 bits reversible parallel adder should be constructed with the help of four reversible full-adders. We have shown the 4 bits reversible parallel adder in Fig. 4.2.2. But there are some lower bounds on both the number of gates and number of garbage outputs.

Lemma 4.2.1: A reversible 4-bit adder parallel adder can be realized by at least 8 garbage outputs. Proof: It has been proved that, a reversible full-adder circuit can be realized by at least 2 garbage outputs [2, 3]. As a reversible 4-bit parallel adder consists of four reversible full-adder, a reversible 4-bit parallel adder can be realized by at least (2*4=) 8 garbage outputs.

Lemma 4.2.2: A reversible 4-bit adder parallel adder can be realized by at least 8 reversible gates. Proof: It has been proved that, a reversible full-adder circuit can be realized by at least 2 reversible gates [4]. As a reversible 4-bit parallel adder consists of four reversible full-adder, a reversible 4-bit parallel adder can be realized by at least (2*4=) 8 reversible gates.

On the design of a reversible circuit, copies of some of the bits are greatly needed for computation purposes, so that fan-out is needed. But fan-out is strictly prohibited in reversible computation. In that case, a reversible gate should be used for copying. But, inappropriate selection of gate leads to generate a garbage output with the expected copy. But we will select Feynman gate as an appropriate gate.

Lemma 4.2.3: Feynman gate is the most suitable gate for a single copy of a bit. Proof: As there are exactly two outputs corresponding to the inputs of a Feynman gate, a ‘0’ in the second input will copy the first input in both the outputs of that gate. So, Feynman gate is the most suitable gate for single copy of bit since it is not producing any garbage output.

copy of bit since it is not producing any garbage output. 4.3 Synthesis algorithm of the
copy of bit since it is not producing any garbage output. 4.3 Synthesis algorithm of the
copy of bit since it is not producing any garbage output. 4.3 Synthesis algorithm of the
copy of bit since it is not producing any garbage output. 4.3 Synthesis algorithm of the
copy of bit since it is not producing any garbage output. 4.3 Synthesis algorithm of the
copy of bit since it is not producing any garbage output. 4.3 Synthesis algorithm of the

4.3 Synthesis algorithm of the proposed circuit

Construction of reversible BCD adder consists of several steps. The steps to construct a reversible BCD adder are shown in the following Algorithm.

Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE

Algorithm (Construct_Reversible_BCD_ Adder):

1. Construct a reversible full-adder circuit efficiently so that the circuit requires very few numbers of gates and generates small number of garbage outputs.

2. Construct a reversible 4 bits parallel adder by cascading four copies of reversible full-adder circuits.

3. Construct necessary combinational logic to control overflow of the result of addition by selecting appropriate reversible gates.

4. Apply two 4 bits operands (A 3 , A 2 , A 1 , A 0 and B 3 , B 2 , B 1 , B 0 ) into the first 4 bits reversible adder and generate the initial sum (S 3 , S 2 , S 1 , S 0 ) and carry C 4 .

5. Apply the result into the combinational logic for error correction.

6. Apply the initial sum (S 3 , S 2 , S 1 , S 0 ) into the first four pins of the second reversible 4-bits parallel adder and error correcting code into the last four pins to get the final addition.

To comprehend the above algorithm clearly, we have presented each step in different figures. According to the algorithm, the design of the reversible BCD adder has been shown as follows: Fig. 4.3.1 (Step 1), Fig. 4.3.2 (Step 2), Fig. 4.3.3 (Step 3), Fig. 4.3.4 (Step 4), Fig. 4.3.5 (Step 5), and Fig. 4.3.6 (Step 6). The final circuit, reversible BCD adder, is presented in Fig. 4.3.7.

circuit, reversible BCD adder, is presented in Fig. 4.3.7. Figure 4.3.1. A reversible full-adder circuit with

Figure 4.3.1. A reversible full-adder circuit with only 2 reversible gates, i.e., one New Gate and a New Toffoli Gate that generates only 2 garbage outputs [4].

New Toffoli Gate that generates only 2 garbage outputs [4]. Figure 4.3.2. 4-bits reversible parallel adder

Figure 4.3.2. 4-bits reversible parallel adder with the cascade of four reversible full-adder.

adder with the cascade of four reversible full-adder. Figure 4.3.3. Combinational logic for reversible BCD adder.

Figure 4.3.3. Combinational logic for reversible BCD adder.

Figure 4.3.3. Combinational logic for reversible BCD adder. Figure 4.3.4. 4-bit reversible parallel adder with two

Figure 4.3.4. 4-bit reversible parallel adder with two 4-bits variable A and B.

reversible parallel adder with two 4-bits variable A and B. Figure 4.3.5. Combinational logic for BCD

Figure 4.3.5. Combinational logic for BCD adder with appropriate inputs that produces 6 garbage outputs.

with appropriate inputs that produces 6 garbage outputs. Figure 4.3.6. Second 4-bit parallel reversible adder with

Figure 4.3.6. Second 4-bit parallel reversible adder with the output of the combinational logic.

Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE

Figure 4.3.7. Full-design of the proposed BCD adder. In our proposed circuit, we used four

Figure 4.3.7. Full-design of the proposed BCD adder.

In our proposed circuit, we used four reversible full- adder circuits of [4] to construct a reversible 4-bit parallel adder, and each of the full-adder circuit produces two garbage outputs. So, the total number of garbage outputs generated from the reversible 4-bit adder is 8. Combinational Logic (((S 1 + S 2 )* S 3 ) +C 4 ) generates six garbage outputs in our proposed reversible BCD adder using three New gates. Feynman gates, which are used for copying bits, don’t produce any garbage outputs while one copy is needed for a bit. As a result, the total number of garbage outputs required to construct a reversible BCD adder is 2*8 + 6

=22. In our proposed circuit, we use four reversible full- adder circuits to construct a reversible 4-bit parallel adder; total 8 reversible gates are required to construct a 4-bit reversible adder. Combinational Logic (((S 1 + S 2 )* S 3 ) +C 4 ) requires three New gates (NG) in our proposed reversible BCD adder. Three Feynman gates are required for copying S 1 , S 2 , and S 3 to avoid fan-out of those bits. Finally, another Feynman gate is required for copying the result of combinational logic ((S 1 + S 2 )* S 3 ) + C 4 ). As a result, the total number of gates required to construct a reversible BCD adder is 2*8 + 3 + 4=23.

5. Conclusion and future work

In this paper, we presented a reversible design technique for Binary Coded Decimal (BCD) adder circuit. We have also established the lower bound for the total number of gates and garbage outputs. There exists many significant applications of reversible logics such as low power CMOS, quantum computing, nano-technology, and optical computing [1,6,8-11]. The proposed BCD adder circuit is one of the contributions of reversible logic. This circuit can further be used in a large reversible system as a module of reversible logic. In future, we have the plan to construct large reversible system that executes more than one reversible operations concurrently.

6. References

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525-532.

[2] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, “Reversible Logic Synthesis for Minimization of Full- adder Circuit”, IEEE Conference on Digital System Design 2003, Euro-Micro’03, Belek, Antalya, Turkey, 2003, pp. 50-54.

[3] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury and Syed Mostahed Ali Chowdhury, “Synthesis of Full-adder Circuit Using Reversible Logic”, 17th International Conference on VLSI design 2004, Mumbai, India, 2004, pp. 757-760.

[4] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan

Raja Chowdhury and Syed Mostahed Ali Chowdhury, “On the Realization of Reversible Full-Adder Circuit”, International Conference on Computer and Information Technology, Dhaka, Bangladesh, 2003, Vol. 2, pp. 880-

883.

Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE

[5] Ronald J. Tocci, Digital Systems- Principles and Application, New Delhi, India, 1996.

[6] R. Landauer, “Irreversibility and Heat Generation in the Computational Process”, IBM Journal of Research Development, 5 ,1961, 183-191.

[7] Md. M. H Azad Khan, “Design of Full-adder With Reversible Gates”, International Conference on Computer and Information Technology, Dhaka, Bangladesh, 2002, pp. 515-519.

[8] E. Fredkin, T. Toffoli, “Conservative Logic”, International Journal of Theor. Physics, 21, 1982, pp.

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[9] Milburn, Gerard J., The Feynman Processor, Perseus Books, 1998.

[10] R. Feynman, “Quantum Mechanical Computers”, Optical News, 1985, pp. 11-20.

[11] T. Toffoli., “Reversible Computing”, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).

[12] P.D. Picton, “Fredkin Gates as the Basic for Comparison of Different Logic Designs”, Synthesis and Optimization of Logic Systems, London, UK, 1994.

[13] M. Perkowski, L. Jozwiak, P. Kerntopf, A Mishchenko, A. Al-Rabadi, A. Coppola, A. Buller, X Song, M. M. H. A. Khan, S Yanushkevich, V.S Shmerko, and M. Chzazowska-Jeske, “A general decomposition for reversible logic”, in: Proc. RM ‘01.

[14] Andrel B. Khlopotine, M Perkowski and Pawel Kerntopf, “Reversible Logic Synthesis by Iterative Composition”, in: Proc. IWLS ‘02,pp. 261-266.

[15]. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Hoque, Ahsan Raja Chowdhury, “Logic Synthesis and Minimization of Boolean Functions Using TANT Network”, International conference on computer and information technology 2003, 19-21, Dhaka, Bangladesh, Dec 2003, Vol-2 pp.884-889.

[16]. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Hoque, Ahsan Raja Chowdhury, “Heuristic approach to synthesize Boolean functions using TANT network”, IEEE, International Symposium on Circuits and Systems, Vancouver, Canada, 23-26 May 2004, VLSI-L7.4, vol. II, pp. 373 – 376.

Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (VLSID’05) 1063-9667/05 $20.00 © 2005 IEEE