TB-FMCL-HDMI Hardware User Manual

TB-FMCL-HDMI Hardware User Manual

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Revision History Version Rev.0.01 Rev.1.00 Rev.1.01 Date 2010/03/02 2010/04/05 2010/05/27 Description Bata version release Release version 2. Overview : Add notice of ADV7441A Table 8-1 : LED function modified Table 8-2 : Switch function modified Table 9-1 : FPGA Ping assign modified Table 11-2 : Initial setting of DIP SW modified 12. Example of use : Add comment Rev1.02 Rev.1.03 2010/5/28 2010/5/31 Table 9-1 : Changed Ping assign Changed document format Yoshioka Yoshioka Publisher Tecchikawahara Yoshioka Yoshioka

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Table of Contents
1. 2. 3. 4. 5. 6. 7. Related Documents and Accessories............................................................................................................................. 8 Overview..................................................................................................................................................................................... 8 Feature........................................................................................................................................................................................ 8 Block Diagram .......................................................................................................................................................................... 9 External View of the Board...............................................................................................................................................10 Board Specifications............................................................................................................................................................11 Description of Components ..............................................................................................................................................12
7.1. 7.2. 7.3. 7.4. 7.5. Power Supply Structure for the TB-FMCL-HDMI Board........................................................... 12 HDMI Encoder block ................................................................................................................ 13 HDMI Decoder block ................................................................................................................ 14 FMC Connector ........................................................................................................................ 15 Other Interfaces........................................................................................................................ 17 UART Interface ................................................................................................................. 17 EEPROM Interface ........................................................................................................... 17 JTAG Interface .................................................................................................................. 17 General-Purpose Clock Interface ..................................................................................... 17 Display Function ............................................................................................................... 18 Operation Function ........................................................................................................... 18

7.5.1. 7.5.2. 7.5.3. 7.5.4.

8.

Display and Operation Functions....................................................................................................................................18

8.1.1. 8.1.2.

9. FPGA Pin Assignment.........................................................................................................................................................19 10. Input and output signals phase of FPGA ...............................................................................................................24 11. Default Switch Settings ................................................................................................................................................25 12. Example of Use.................................................................................................................................................................26 13. Others ..................................................................................................................................................................................27

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List of Figures
Figure 3-1 FMC Connector Pinout ..................................................................................................... 8 Figure 4-1 Block Diagram .................................................................................................................. 9 Figure 5-1 Component Side ............................................................................................................. 10 Figure 5-2 Solder Side ..................................................................................................................... 10 Figure 6-1 Board Dimensions (inclusive of wastable substrate) .......................................................11 Figure 7-1 Power Supply Structure .................................................................................................. 12 Figure 11-1 Default Switch Settings (Component Side)................................................................... 25 Figure 12-1 Example of Use ............................................................................................................ 26

List of Tables
Table 7-1 VCCIO_SEL Jumper Setting ............................................................................................ 12 Table 7-2 HDMI Connector (Transmit Side) ..................................................................................... 13 Table 7-3 HDMI Connector (Receiver Side)..................................................................................... 14 Table 7-4 SCL/SDA Jumper Setting ................................................................................................. 14 Table 7-5 JP7/JP8 Jumper Setting................................................................................................... 15 Table 7-6 FMC Connector Pin Assignment ...................................................................................... 16 Table 7-7 UART Connector .............................................................................................................. 17 Table 7-8 JTAG Connector ............................................................................................................... 17 Table 8-1 LEDs................................................................................................................................. 18 Table 8-2 Switches ........................................................................................................................... 18 Table 9-1 FPGA Pin Assignment ...................................................................................................... 19 Table 11-1 Default Jumper Settings ................................................................................................. 25 Table 11-2 Default DIP Switch Settings............................................................................................ 25 Table 12-1 Jumper Settings in the Example .................................................................................... 26

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Introduction
Thank you for purchasing the TB-FMCL-HDMI board. manual, then always keep it handy. Before using the product, be sure to carefully First read through this read this user manual and fully understand how to correctly use the product.

SAFETY PRECAUTIONS

Be sure to observe these precautions

Observe the precautions listed below to prevent injuries to you or other personnel or damage to property. Before using the product, read these safety precautions carefully to assure correct use. These precautions contain serious safety instructions that must be observed. After reading through this manual, be sure to always keep it handy. The following conventions are used to indicate the possibility of injury/damage and classify precautions if the product is handled incorrectly.

Danger

Indicates the high possibility of serious injury or death if the product is handled incorrectly. Indicates the possibility of serious injury or death if the product is handled

Warning

incorrectly. Indicates the possibility of injury or physical damage in connection with houses or

Caution

household goods if the product is handled incorrectly.

The following graphical symbols are used to indicate and classify precautions in this manual. (Examples)

Turn off the power switch.

Do not disassemble the product.

Do not attempt this.

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Warning
In the event of a failure, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. immediately and contact our sales personnel for repair. Disconnect the power supply

If an unpleasant smell or smoking occurs, disconnect the power supply.

If the product is used as is, a fire or electric shock may occur. immediately. repair. Disconnect the power supply After verifying that no smoking is observed, contact our sales personnel for

Do not disassemble, repair or modify the product.

Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. inspection, modification or repair, contact our sales personnel. For

! ! ! ! ! ! !

Do not touch a cooling fan.

As a cooling fan rotates in high speed, do not put your hand close to it. cause injury to persons. Never touch a rotating cooling fan. Otherwise, it may

Do not place the product on unstable locations.

Otherwise, it may drop or fall, resulting in injury to persons or failure.

If the product is dropped or damaged, do not use it as is.

Otherwise, a fire or electric shock may occur.

Do not touch the product with a metallic object.

Otherwise, a fire or electric shock may occur.

Do not place the product in dusty or humid locations or where water may splash.
Otherwise, a fire or electric shock may occur.

Do not get the product wet or touch it with a wet hand.

Otherwise, the product may break down or it may cause a fire, smoking or electric shock.

Do not touch a connector on the product (gold-plated portion).

Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting in contact failure of a connector or it may cause a malfunction, fire or electric shock due to static electricity.

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Caution

Do not use or place the product in the following locations.

Humid and dusty locations Airless locations such as closet or bookshelf Locations which receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high Staticky locations Locations close to water or chemicals Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat generation.

Do not place heavy things on the product.

Otherwise, the product may be damaged.

Disclaimer
This product is a board intended for HDMI encoding and decoding function. And provide Molex HDMI connector and Samtec FMC low pin count connector. stated. Even if the product is used properly, Tokyo Electron Device Limited assumes no responsibility for any damages caused by: (1) Earthquake, thunder, natural disaster or fire resulting from the use beyond our responsibility, acts by a third party or other accidents, the customers willful or accidental misuse or use under other abnormal conditions. (2) Secondary impact arising from use of this product or its unusable state (business interruption or others) (3) Use of this product against the instructions given in this manual. (4) Malfunctions due to connection to other devices. Tokyo Electron Device Limited assumes no responsibility or liability for: (1) Erasure or corruption of data arising from use of this product. (2) Any consequences or other abnormalities arising from use of this product, or (3) Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research, testing or evaluation. authorized for use in any system or application that requires high reliability. Repair of this product is carried out by replacing it on a chargeable basis, not repairing the faulty devices. However, non-chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product. The specification of this product is subject to change without prior notice. The product is subject to discontinuation without prior notice. It is not Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those

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1. Related Documents and Accessories

Related documents: All documents relating to this board can be downloaded from our website. Please see attached paper on the products. Board accessories: FMC spacer set M2.6 X 10 spacer (Duracon): Screws with Duracon washer: Jumper socket set Jumper socket: 5 2 4

2. Overview
This board provides HDMI encoder and decoder functions. (Low-Pin Count) and Molex HDMI connector. platform board with a Low-Pin Count connector. Notice: 1) This board uses Analog Devices Inc, ADV7441A(Encoder) and ADV7510(Decoder). These devices do not support HDCP functions. 2) ADV7441A(Encoder) accepts 8 or 12bits input format but output format is 8 or 10bits. When using 12bits input signal, output is reduced to 10bits.(lost LSB 2bits) It uses Samtec FMC connector The board is designed for connection with the

3. Feature
FMC Connector: HDMI Connector: Power Selection: Samtec FMC (Low-Pin Count) connector Molex 5002541927 Supply voltage is selectable using an onboard jumper switch

Figure 3-1 FMC Connector Pinout

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4. Block Diagram
Figure 4-1 shows the block diagram of the TB-FMCL-HDMI board. the solder side of the board. The FMC connector is mounted on

FMCLPC FPGA
LA00_P/NLA33_P/N

ENC_D350 ENC_DE/DCLK/HSYNC/VSYNC

TDMS_TX2+/TX2-

HDMI

ENC
ENC_DSD50ENC_DSD_CLK

TDMS_TX1+/TX1TDMS_TX0+/TX0TDMS_TXC+/TXCENC_DDCA_SCL/SDA ENC_CEC ENC_HPD

ADV7510

CLK0_M2C_P/NCLK1_M2C_P/N

ENC_I2S30/SCLK/LRCLK ENC_SPDIF ENC_MCLK

SCLSDA ENC_PD ENC_INT ENC_SDA/SCL

ENC_HPD_IO

DEC_P290 DSW30 DEC_DE/LLC/HSYNC/VSYNC

TDMS_RX2+/RX2-

HDMI

DEC ADV7441A

TDMS_RX1+/RX1TDMS_RX0+/RX0TDMS_RXC+/RXCDEC_CEC DEC_DDCA_SCL/SDA

DEC_2S30/LRCLK/SCLK DLED30 DEC_SPDIF DEC_MCLKOUT DEC_INT1/INT2 DEC_RESETX/EXT_CLAMP

EEPROM

EEPROM_SCL/SDA DEC_SDA/SCL

HPD1

CLK

SYSCLK_P DEC_HPD_IO DEC_DET1

RS232C

UART_TXD/RXD

JP

EEPROM

Figure 4-1 Block Diagram

Main Functions: 1. 2. 3. 4. 5. 6. 7. 8. 9. HDMI Encoder Function (FMC Connector: ADV7441A) HDMI Decoder Function (ADV7510: FMC Connector) FMC Connector Interface (FMC Connector: FPGA) UART Interface EEPROM Interface JTAG Interface General-Purpose Clock Interface General-Purpose Switch General-Purpose LED

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5. External View of the Board

Figure 5-1 and 5-2 show the external view of the board.

Figure 5-1 Component Side

Figure 5-2 Solder Side

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6. Board Specifications
Figure 6-1 shows the board specifications. External Dimensions: Number of Layers: Board Thickness: Material: FPGA: FMC Connector: HDMI Connector: 135.9 mm (W) x 69 mm (H) 8 layers 1.6 mm FR-4 Xilinx XC3S400AN-5FGG400 Samtec ASP-134604-01 Molex 5002541927

Figure 6-1 Board Dimensions (inclusive of wastable substrate)

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7.
7.1.

Description of Components
Power Supply Structure for the TB-FMCL-HDMI Board

Figure 7-1 shows the power supply structure for the board.
VCC_12V_IN LT3503EDCB VCC_5V
ADG702: 0.001mA 24LCS22A: 3mA

97mA (0.485W) 234mA (2.25W)

LT1963AES

VCC_3.3V_2.5V
FPGA_VCCIO: 94mA

LT3503EDCB

VCC_3.3V
FPGA_VCAUX: 31mA FPGA_VCCIO: 244mA MAX3223: 1mA NC7SZ125: 0.02mA ADV7510: 0.3mA ADV7441: 251mA KC3225A: 6mA LTC1326: 0.04mA

/SHDN

533mA (1.76W)

VCC_3.3V_IN

LT3568EDD

VCC_2.5V

982mA

1235mA (3.08W)

LTC3026EMSE

VCC_1.8V
ADV7510: 325mA

LTC3026EMSE

VCC_1.8V_DEC ADV7441: 562mA

PG

LTC3026EMSE

VCC_1.2V
FPGA_VCCINT: 348mA

Figure 7-1 Power Supply Structure

VCC_3.3V_2.5V is used as I/O voltage for FPGA BANK2/BANK3. The BANK supports both 3.3V and 2.5V interfaces. JP4-VCCIO_SEL. Caution: Initial setting of FPGA IO standard is 2.5V (LVDS25) interface. JP4 can provide 3.3V for FPGA IO power but FPGA configuration ROM is 2.5V device. Please contact to us if require 3.3V IO. The interface selection can be performed using

Table 7-1 VCCIO_SEL Jumper Setting

No 1 2 Interface 3.3V 2.5V VCCIO_SEL: 2-3 Short VCCIO_SEL: 1-2 Short Jumper Setting

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7.2.

HDMI Encoder block

The HDMI transmitter connector is the 5002541927 (Molex) and the HDMI encoder is the ADV7510BSTZ (Analog Devices). The following EMI/ESD devices are used: ESD: EMI: ESD Suppressor EZAEG2A (Panasonic) Choke Coil DLP11SN900HL2L (Murata)

Table 7-2 shows the HDMI transmitter connector pin assignments.

Table 7-2 HDMI Connector (Transmit Side)

Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name TDMS DATA2+ TMDS SHLD2 TDMS DATA2TDMS DATA1+ TMDS SHLD1 TDMS DATA1TDMS DATA0+ TMDS SHLD0 TDMS DATA0TDMS CLK+ TMDS CLK SHLD TDMS CLKCEC RESERVED DDC_SCL DDC_SDA DDC/CEC GND DDC_+5V HOTPLUG_DET Description TMDS Transmit Data 2+ TMDS Transmit Data 2 Shield TMDS Transmit Data 2TMDS Transmit Data 1+ TMDS Transmit Data 1 Shield TMDS Transmit Data 1TMDS Transmit Data 0+ TMDS Transmit Data 0 Shield TMDS Transmit Data 0TMDS Transmit Clock+ TMDS Transmit Clock Shield TMDS Transmit ClockCEC Signal Reserved DDC Serial Clock DDC Serial Data DDC/CEC Ground +5V Power Supply Hot Plug Detection

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7.3.

HDMI Decoder block

The HDMI receiver connector is the 5002541927 (Molex) and the HDMI decoder is the ADV7441ABSTZ (Analog Devices). The following EMI/ESD devices are used: ESD: EMI: ESD Suppressor EZAEG2A (Panasonic) Choke Coil DLP11SN900HL2L (Murata)

Table 7-3 shows the HDMI receiver connector pin assignments.

Table 7-3 HDMI Connector (Receiver Side)

Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name TDMS DATA2+ TMDS SHLD2 TDMS DATA2TDMS DATA1+ TMDS SHLD1 TDMS DATA1TDMS DATA0+ TMDS SHLD0 TDMS DATA0TDMS CLK+ TMDS CLK SHLD TDMS CLKCEC RESERVED DDC_SCL DDC_SDA DDC/CEC GND DDC_+5V HOTPLUG_DET Description TMDS Receive Data 2+ TMDS Receiver Data 2 Shield TMDS Receive Data 2-Shield TMDS Receive Data 1+ TMDS Receive Data 1 Shield TMDS Receive Data 1TMDS Receive Data 0+ TMDS Receive Data 0 Shield TMDS Receive Data 0TMDS Receive Clock TMDS Receive Clock Shield TMDS Receive Clock CEC Signal Reserved DDC Serial Clock DDC Serial Data DDC/CEC Ground +5V Power Supply Hot Plug Detection

The decoder circuit has an EEPROM (Micro Chip: 24LCS22A-SN). This EEPROM allows the bidirectional access from HDMI decoder and FPGA. The selection can be performed using JP5-SCL/JP6-SDA. Caution: The EEPROM has a temporary data when shipping this board. Temporary data is used for only evaluation environment. Please do not use temporary data to product.

Table 7-4 SCL/SDA Jumper Setting

No 1 2 Access From FPGA From HDMI SCL: 2-3 Short SCL: 1-2 Short Jumper Setting SDA: 2-3 Short SDA: 1-2 Short

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7.4.

FMC Connector

The FMC connector (Low-Pin Count) which is connected to the main board uses a SAMTEC ASP-134488-01. The TB-FMCL-HDMI board uses +12V and +3.3V supplied by the main board. An external power supply source can also be used. This can be selected using jumpers JP7 and JP8.

Table 7-5 JP7/JP8 Jumper Setting

No 1 2 Power Supply FMC Connector External Power Supply JP7: 1-2 Short JP7: 2-3 Short Jumper Setting JP8: 1-2 Short JP8: 2-3 Short

The following test pins are used for the external power supply input. TP13: 3.3VIN TP14: 12VIN

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Table 7-6 shows the FMC connector pin assignment.

Table 7-6 FMC Connector Pin Assignment

Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 C-row GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 +12V GND +12V GND +3.3V GND D-row PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO +3.3VAUX TMS TRST GA1 +3.3V GND +3.3V GND +3.3V G- row GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND H-row VREF_A_M2C PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ

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7.5.

Other Interfaces

The board has the following interfaces. 7.5.1. UART Interface

The board has a UART interface for the communication with an external device. Silk: UART JP3 Connector P/N: 90120-0123 (Molex)

Table 7-7 UART Connector

Pin # 1 3 TXD GND Signal Pin # 2 RXD Signal Name

7.5.2.

EEPROM Interface

The board has an I2C interface on FPGA that controls EEPROM. EEPROM device: 24LCS22A-SN (Micro Chip)

7.5.3.

JTAG Interface

The board has a JTAG connector for the FPGA configuration. JTAG connector: 87832-1420 (Molex)

Table 7-8 JTAG Connector

Pin # 1 3 5 7 9 11 13 GND GND GND GND GND GND GND Signal Pin # 2 4 6 8 10 12 14 3.3V TMS TCK TDO TDI NC NC Signal Name

7.5.4.

General-Purpose Clock Interface

The board has a general-purpose clock oscillator on FPGA (27MHz). KC5032C027.0000C30E00 (Kyocera)

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8. Display and Operation Functions

The board provides a variety of display and operation functions using various LEDs and switches. 8.1.1. Display Function

Table 8-1 shows the onboard LEDs and their functions.

Table 8-1 LEDs

No 1 2 3 4 5 6 7 Circuit # DS1 DS2 DS3 DS4 DS9 DS11 DS14 Silk LED1 LED2 LED3 LED4 DONE HPD LED General-purpose LED1 General-purpose LED2 General-purpose LED3 General-purpose LED4 Configuration status HDMI transmit hot plug display HDMI receive hot plug display Description DCM RX Lock status of FPGA DCM TX Lock status of FPGA Finish of write access of I2C Not used ON: Configuration complete ON: Connection status ON: Connection status

8.1.2.

Operation Function

Table 8-2 shows the onboard switches and their functions.

Table 8-2 Switches

No 1 2 3 4 5 Circuit # S1-1 S1-2 S1-3 S1-4 S4 Silk DSW DSW DSW DSW Function FPGA reset switch(ON: Active / OFF: Not Active) Polarity change of HSYNC,VSYNC for encoder(ON: Invert) Input select from DVI / HDMI(ON:HDMI In / OFF: DVI In) Connection select from DEC / ENC. (ON:DEC to ENC / OFF: DEC,ENC to FMC) Reconfiguration switch(keep to pushing over 3 second)

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9. FPGA Pin Assignment

Table 9-1 shows the FPGA pin assignment. Ping assign of FMC to FPGA signals are related by signal format. When input format is 8bits, signals are assigned to each color of upper 8bits. And under 2bits(bit 9/10) of FPGA to FMC signals should be 0.

Table 9-1 FPGA Pin Assignment

Pin Name LA33_N LA33_P LA32_N LA32_P LA30_N LA30_P LA31_N LA31_P LA29_N LA29_P LA22_N LA22_P LA27_N LA27_P LA26_N LA26_P LA28_N LA28_P LA24_N LA24_P LA23_N LA23_P LA25_N LA25_P LA21_N LA21_P LA20_N LA20_P LA19_N LA19_P LA18_N_CC LA18_P_CC LA17_N_CC LA17_P_CC LA16_N LA16_P LA15_N LA15_P # D3 D4 C2 B1 D2 C1 E1 D1 G5 F4 J5 J6 H4 H6 G4 F3 F2 E3 H2 G3 G1 F1 H3 J4 J2 J3 K2 J1 L3 K3 L5 K4 M1 L1 M3 M2 M5 M4 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Spec LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 Not used Not used FPGA to FMC : DATA ENABLE FMC to FPGA : DATA ENABLE FPGA to FMC : HSYNC FMC to FPGA : HSYNC FPGA to FMC : VSYNC FMC to FPGA : VSYNC FPGA to FMC : DATA29(R9) FMC to FPGA : DATA29(R9) FPGA to FMC : DATA28(R8) FMC to FPGA : DATA28(R8) FPGA to FMC : DATA27(R7) FMC to FPGA : DATA27(R7) FPGA to FMC : DATA26(R6) FMC to FPGA : DATA26(R6) FPGA to FMC : DATA25(R5) FMC to FPGA : DATA25(R5) FPGA to FMC : DATA24(R4) FMC to FPGA : DATA24(R4) FPGA to FMC : DATA23(R3) FMC to FPGA : DATA23(R3) FPGA to FMC : DATA22(R2) FMC to FPGA : DATA22(R2) FPGA to FMC : DATA21(R1) FMC to FPGA : DATA21(R1) FPGA to FMC : DATA20(R0) FMC to FPGA : DATA20(R0) FPGA to FMC : DATA19(G9) FMC to FPGA : DATA19(G9) FPGA to FMC : DATA18(G8) FMC to FPGA : DATA18(G8) FPGA to FMC : DATA17(G7) FMC to FPGA : DATA17(G7) FPGA to FMC : DATA16(G6) FMC to FPGA : DATA16(G6) FPGA to FMC : DATA15(G5) FMC to FPGA : DATA15(G5) Description

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Pin Name LA14_N LA14_P LA13_N LA13_P LA12_N LA12_P LA11_N LA11_P LA10_N LA10_P LA09_N LA09_P LA08_N LA08_P LA07_N LA07_P LA06_N LA06_P LA05_N LA05_P LA04_N LA04_P LA03_N LA03_P LA02_N LA02_P LA01_N_CC LA01_P_CC LA00_N_CC LA00_P_CC CLK0_M2C_N CLK0_M2C_P CLK1_M2C_N CLK1_M2C_P FMC_SCL FMC_SDA DSW0 DSW1 DSW2 DSW3 DLED0 DLED1

# N2 N1 N4 N3 R1 P1 P4 P3 R3 R2 T2 T1 R4 T3 U3 U1 T4 R5 V2 V1 W2 W1 W4 Y3 R7 T6 U5 V5 U6 T7 Y9 W9 W10 V10 V11 Y11 R12 T12 Y12 W13 T15 U15

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I I I I O O

Spec LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25

Description FPGA to FMC : DATA14(G4) FMC to FPGA : DATA14(G4) FPGA to FMC : DATA13(G3) FMC to FPGA : DATA13(G3) FPGA to FMC : DATA12(G2) FMC to FPGA : DATA12(G2) FPGA to FMC : DATA11(G1) FMC to FPGA : DATA11(G1) FPGA to FMC : DATA10(G0) FMC to FPGA : DATA10(G0) FPGA to FMC : DATA9(B9) FMC to FPGA : DATA9(B9) FPGA to FMC : DATA8(B8) FMC to FPGA : DATA8(B8) FPGA to FMC : DATA7(B7) FMC to FPGA : DATA7(B7) FPGA to FMC : DATA6(B6) FMC to FPGA : DATA6(B6) FPGA to FMC : DATA5(B5) FMC to FPGA : DATA5(B5) FPGA to FMC : DATA4(B4) FMC to FPGA : DATA4(B4) FPGA to FMC : DATA3(B3) FMC to FPGA : DATA3(B3) FPGA to FMC : DATA2(B2) FMC to FPGA : DATA2(B2) FPGA to FMC : DATA1(B1) FMC to FPGA : DATA1(B1) FPGA to FMC : DATA0(B0) FMC to FPGA : DATA0(B0) Not used FMC to FPGA : Clock Not used FPGA to FMC : Clock I2C serial clock I2C serial data General-purpose DIP SW input 0 General-purpose DIP SW input 1 General-purpose DIP SW input 2 General-purpose DIP SW input 3 General-purpose LED output 0 General-purpose LED output 1

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Pin Name DLED2 DLED3 DEC_P29 DEC_P28 DEC_P27 DEC_P26 DEC_P25 DEC_P24 DEC_P23 DEC_P22 DEC_EXT_CLK DEC_P21 DEC_P20 DEC_P19 DEC_P18 DEC_P17 DEC_P16 DEC_P15 DEC_P14 DEC_P13 DEC_P12 DEC_P11 DEC_P10 DEC_P9 DEC_P8 DEC_P7 DEC_P6 DEC_P5 DEC_P4 DEC_P3 DEC_LLC SYSCLK_P DEC_SCLK DEC_MCLKOUT DEC_P2 DEC_P1 DEC_P0 DEC_RESETX DEC_INT1 DEC_INT2 DEC_VSYNC DEC_HSYNC

# W16 Y16 A18 B18 C17 D17 E15 D16 A17 B17 A16 C16 C15 D15 A14 C14 A15 B15 F13 E13 C13 D14 C12 B13 F12 D12 A12 B12 C11 B11 D11 A10 D10 A9 C9 B9 C8 B8 D8 C7 F9 E9

IO O O I I I I I I I I O I I I I I I I I I I I I I I I I I I I I I I I I I I O I I I I

Spec LVCMOS25 LVCMOS25 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33

Description General-purpose LED output 2 General-purpose LED output 3 DEC Video data input 29 DEC Video data input 28 DEC Video data input 27 DEC Video data input 26 DEC Video data input 25 DEC Video data input 24 DEC Video data input 23 DEC Video data input 22 DEC external clock output DEC Video data input 21 DEC Video data input 20 DEC Video data input 19 DEC Video data input 18 DEC Video data input 17 DEC Video data input 16 DEC Video data input 15 DEC Video data input 14 DEC Video data input 13 DEC Video data input 12 DEC Video data input 11 DEC Video data input 10 DEC Video data input 9 DEC Video data input 8 DEC Video data input 7 DEC Video data input 6 DEC Video data input 5 DEC Video data input 4 DEC Video data input 3 DEC LLC signal System clock input (25MHz) DEC Audio serial clock DEC Audio master clock DEC Video data input 2 DEC Video data input 1 DEC Video data input 0 DEC reset output DEC interrupt input 1 DEC interrupt input 2 DEC VSYNC input DEC HSYNC input

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Pin Name DEC_DE DEC_SCL DEC_SDA DEC_EXT_CLAMP DEC_LRCLK DEC_I2S3 DEC_I2S2 DEC_I2S1 DEC_I2S0 DEC_SPDIF DEC_DDCA_SDA_F DEC_DDCA_SCL_F DEC_CEC DEC_HPD_IO DEC_DET1 UART_TXD UART_RXD EEPROM_SCL EEPROM_SDA ENC_HPD_IO ENC_PD ENC_LRCLK ENC_SCLK ENC_I2S3 ENC_I2S2 ENC_I2S1 ENC_I2S0 ENC_MCLK ENC_SPDIF ENC_DSD_CLK ENC_DSD5 ENC_DSD4 ENC_DSD3 ENC_DSD2 ENC_DSD1 ENC_DSD0 ENC_VSYNC ENC_HSYNC ENC_DE ENC_D0 ENC_D1 ENC_D2

# F8 E8 A7 B7 C6 A6 B5 A5 F7 E7 D6 C5 C4 A4 B3 A3 F6 E6 A2 V20 W20 U18 V19 T17 T20 T18 U20 U19 P17 P16 R17 R18 R20 R19 P20 P18 N17 N15 N19 N18 M18 M17

IO I O IO O I I I I I I IO I IO O I O I O IO O O O O O O O O O O O O O O O O O O O O O O O

Spec LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33

Description DEC data enable DEC I2C serial clock DEC I2C serial data DEC external CLAMP signal DEC LRCLK signal DEC I2S Audio signal 3 DEC I2S Audio signal 2 DEC I2S Audio signal 1 DEC I2S Audio signal 0 DEC SPDIF digital Audio input DEC slave serial data DEC slave serial clock DEC CEC signal DEC hot plug control DEC Detect signal UART transmit data UART receive data EEPROM serial clock EEPROM serial data ENC hot plug control ENC power down signal ENC LRCLK signal ENC Audio serial clock ENC I2S Audio signal 3 ENC I2S Audio signal 2 ENC I2S Audio signal 1 ENC I2S Audio signal 0 ENC Audio master clock ENC SPDIF digital Audio output ENC DSD clock ENC DSD Audio data 5 ENC DSD Audio data 4 ENC DSD Audio data 3 ENC DSD Audio data 2 ENC DSD Audio data 1 ENC DSD Audio data 0 ENC VSYNC output ENC HSYNC output ENC data enable ENC Video data output 0 ENC Video data output 1 ENC Video data output 2

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Pin Name ENC_D3 ENC_D4 ENC_D5 ENC_D6 ENC_D7 ENC_D8 ENC_D9 ENC_D10 ENC_D11 ENC_D12 ENC_D13 ENC_D14 ENC_D15 ENC_D16 ENC_DCLK ENC_D17 ENC_D18 ENC_D19 ENC_D20 ENC_D21 ENC_D22 ENC_D23 ENC_D24 ENC_D25 ENC_D26 ENC_D27 ENC_D28 ENC_D29 ENC_D30 ENC_D31 ENC_D32 ENC_D33 ENC_D34 ENC_D35 ENC_SDA ENC_SCL ENC_CEC ENC_INT

# L16 L15 M20 M19 L18 L19 L17 K18 J20 K20 J18 J19 K16 J17 H18 H19 G20 H20 H17 G18 F19 F20 F18 G17 E19 E20 F17 E18 D18 D20 F16 G16 C19 C20 B19 B20 N14 P15

IO O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O IO O IO I

Spec LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33

Description ENC Video data output 3 ENC Video data output 4 ENC Video data output 5 ENC Video data output 6 ENC Video data output 7 ENC Video data output 8 ENC Video data output 9 ENC Video data output 10 ENC Video data output 11 ENC Video data output 12 ENC Video data output 13 ENC Video data output 14 ENC Video data output 15 ENC Video data output 16 ENC Video data clock ENC Video data output 17 ENC Video data output 18 ENC Video data output 19 ENC Video data output 20 ENC Video data output 21 ENC Video data output 22 ENC Video data output 23 ENC Video data output 24 ENC Video data output 25 ENC Video data output26 ENC Video data output 27 ENC Video data output 28 ENC Video data output 29 ENC Video data output 30 ENC Video data output 31 ENC Video data output 32 ENC Video data output 33 ENC Video data output 34 ENC Video data output 35 ENC I2C serial data ENC I2C serial clock ENC CEC signal ENC interrupt input

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10.

Input and output signals phase of FPGA

Fugure 10-1 shows timing chart of input and output signals. The data transfer of FPGA to FMC connector, output timing is falling edge of video clock. Main board should latch signals by rising edge of video clock. The data transfer of FMC to FPGA, FPGA latch signals by rising edge of video clock. Main board should output signals by falling edge of video clock.

Figure 10-1 Timing chart of input and output signals

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11.

Default Switch Settings

Figure 10-1 shows default switch settings (see yellow-dotted circles).

Figure 11-1 Default Switch Settings (Component Side)

Table 11-1 Default Jumper Settings

No. 1 2 3 4 5 Silk No. JP4 JP5 JP6 JP7 JP8 Initial Setting 2-3 short 2-3 short 2-3 short 1-2 short 1-2 short Function VCCIO_SEL (1-2: 3.3V / 2-3: 2.5V) SCL_SEL (1-2: FPGA / 2-3: HDMI DEC) SDA_SEL (1-2: FPGA / 2-3: HDMI DEC) 3.3VIN_SEL (1-2: FMC connector / 2-3: External power supply) 12VIN_SEL (1-2: FMC connector / 2-3: External power supply)

Table 11-2 Default DIP Switch Settings

No. 1 2 3 4 Silk No. SW1-1 SW1-2 SW1-3 SW1-4 Initial Setting OFF OFF OFF OFF Function FPGA reset switch(ON: Active / OFF: Not Active) Polarity change of HSYNC,VSYNC for encoder(ON: Invert) Input select from DVI / HDMI(ON:HDMI In / OFF: DVI In) Connection select from DEC / ENC. (ON:DEC to ENC / OFF: DEC,ENC to FMC)

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12.

Example of Use

Figure 12-1 show an example of use when the loop back test. Please be careful with onboard jumper settings. If video is not output, keep to pushing S4 over 3 seconds for re-configuration.

Figure 12-1 Example of Use

Table 12-1 Jumper Settings in the Example

No. 1 2 Silk No. JP2 JP6,7 Setting 1-2 Non Function Bank2 voltage setting (2.5V / 3.3V) FMC3 VADJ voltage setting (2.5V / 3.3V / 5V / None) (Two jumper settings must be the same positions).

* The values indicated by boldface are used in the example of use.

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13.

Others

Bottom of TB-FMCL-HDMI, 4.7K ohm resistor is on the R167, C21 of silk numbers. This is normal state of part mounting.

4.7K

Figure 13-1 Bottom view of TB-FMCL-HDMI

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PLD Solution Division URL: http://www.inrevium.jp/eng/x-fpga-board/ E-mail: psd-support@teldevice.co.jp HEAD Quarter : Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City, Kanagawa, Japan 221-0056 TEL:+81-45-443-4016 FAX:+81-45-443-4058

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