On the BIBO Stability Condition of Adaptive Recursive FLANN Filters With Application to Nonlinear Active Noise Control

Abstract
In this paper, a bounded-input bounded-output (BIBO) stability condition for the recursive functional link artificial neural network (FLANN) filter, based on trigonometric expansions, is derived. This filter is considered as a member of the class of causal shift-invariant recursive nonlinear filters whose output depends linearly on the filter coefficients. As for all recursive filters, its stability should be granted or, at least, tested. The relevant conclusion we derive from the stability condition is that the recursive FLANN filter is not affected by instabilities whenever the recursive linear part of the filter is stable. This fact is in contrast with the case of recursive polynomial filters where, in general, specific limitations on the input range are required. The recursive FLANN filter is then studied in the framework of a feedforward scheme for nonlinear active noise control. The novelty of our study is due to the simultaneous consideration of a nonlinear secondary path and an acoustical feedback between the loudspeaker and the reference microphone. An output error nonlinearly Filtered-U normalized LMS adaptation algorithm, derived for the elements of the above-mentioned class of nonlinear filters, is then applied to the recursive FLANN filter. Computer simulations show that the recursive FLANN filter, in contrast to other filters, is able to simultaneously deal with the acoustical feedback and the nonlinearity in the secondary path.

Aim
To Design recursive functional link artificial neural network (FLANN) filter

Objective
The objectives of this works are,

1.

Design and Implementation of recursive functional link artificial neural network (FLANN) filter using VHDL. 2. Functional verification of the above design 3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.