Following questions have been asked in GATE 2011 CS exam.

1) A thread is usually defined as a light weight process because an operating system (OS) maintains smaller data structures for a thread than for a process. In relation to this, which of the followings is TRUE? (A) On per-thread basis, the OS maintains only CPU register state (B) The OS does not maintain a separate stack for each thread (C) On per-thread basis, the OS does not maintain virtual memory state (D) On per thread basis, the OS maintains only scheduling and accounting information. Answer (A) Threads are called light weight process because they only need storage for stack and registers. They dont need separate space for other things like code segment, global data, etc

2) Let the page fault service time be 10ms in a computer with average memory access time being 20ns. If one page fault is generated for every 10^6 memory accesses, what is the effective access time for the memory? (A) 21ns (B) 30ns (C) 23ns (D) 35ns Answer (B)
Let P be the page fault rate Effective Memory Access Time = p * (page fault service time) + (1 - p) * (Memory access time) = ( 1/(10^6) )* 10 * (10^6) ns + (1 - 1/(10^6)) * 20 ns = 30 ns (approx)

P -> Probability of page fault occurrence is (1/10^6) so, EAT ( in ns) goes like => P* page fault service time + (1-P) * memory access time => (1/10^6) * 10*10^6 + (1- (1/10^6)) * 20 =>29.9ns =>30ns (approx)

3) An application loads 100 libraries at startup. Loading each library requires exactly one disk access. The seek time of the disk to a random location is given as 10ms.

Rotational speed of disk is 6000rpm. If all 100 libraries are loaded from random locations on the disk, how long does it take to load all libraries? (The time to transfer data from the disk block once the head has been positioned at the start of the block may be neglected) (A) 0.50s (B) 1.50s (C) 1.25s (D) 1.00s Answer (B) Since transfer time can be neglected, the average access time is sum of average seek time and average rotational latency. Average seek time for a random location time is given as 10 ms. The average rotational latency is half of the time needed for complete rotation. It is given that 6000 rotations need 1 minute. So one rotation will take 60/6000 seconds which is 10 ms. Therefore average rotational latency is half of 10 ms, which is 5ms.
Average disk access time = seek time + rotational latency = 10 ms + 5 ms = 15 ms For 100 libraries, the average disk access time will be 15*100 ms

4. Consider the following table of arrival time and burst time for three processes P0, P1 and P2.
Process P0 P1 P2 Arrival time 0 ms 1 ms 2 ms Burst Time 9 ms 4 ms 9 ms

The pre-emptive shortest job first scheduling algorithm is used. Scheduling is carried out only at arrival or completion of processes. What is the average waiting time for the three processes? (A) 5.0 ms (B) 4.33 ms (C) 6.33 ms (D) 7.33 ms Answer: (A) Process P0 is allocated processor at 0 ms as there is no other process in ready queue. P0 is preempted after 1 ms as P1 arrives at 1 ms and burst time for P1 is less than remaining time of P0. P1 runs for 4ms. P2 arrived at 2 ms but P1 continued as burst time of P2 is longer than P1. After P1 completes, P0 is scheduled again as the remaining time for P0 is less than the burst time of P2. P0 waits for 4 ms, P1 waits for 0 ms amd P2 waits for 11 ms. So average waiting time is (0+4+11)/3 = 5.

Both K4 and Q3 are planar Consider the languages L1. L2 and L3 as given below. L1= {0p 1q | p, q N}, L2= {0p 1q | p, q N and p = q} and L3 = {0p 1q 0r | p, q, r N and p = q = r}. Which of the following statements is NOT TRUE? A. Push Down Automata (PDA) can be B. L1 is a regular language used to recognize L1 and L2 C. All the three languages are context free D. Turing machines can be used to recognize all the languages Answer: Option C Explanation: L1: regular language L2: context free language L3: context sensitive language On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory. Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address register Decrement the count

If count != 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output? A. 3.4 B. 4.4 C. 5.1 D. 6.7 Answer:A Explanation: No. of clock cycles required by using load-store approach = 2 + 500 * 7 = 3502 and that of by using DMA = 20 + 500 * 2 = 1020 Required speed up => 3502/1020 = 3.4