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SDH Basics
AN00091831 (62.1013.105.11-A001) Edition e, 03.2000

M a r c o n i C o m m u n ic a t io n s G m b H D -7 1 5 2 0 B a ck n a n g T e le f o n ( 0 7 1 9 1 ) 1 3 -0 T e le f a x ( 0 7 1 9 1 ) 1 3 - 3 2 1 2 h t t p : / / w w w .m a r c o n i . c o m C o p y r ig h t 2 0 0 0 b y M a r c o n i C o m m u n ic a t io n s G m b H ( h ie r in b e z e ic h n e t a ls M a r c o n i) n d e r u n g e n v o r b e h a lt e n G e d r u c k t in D e u t s c h la n d M a r c o n i , M a r c o n i C o m m u n i c a t i o n s , d a s M a r c o n i L o g o , d a s g e s c h w u n g e n e 'M ' , S k y b a n d , M D R S , M D M S u n d S e r v ic e O n A c c e s s s in d e in g e t r a g e n e M a r k e n z e ic h e n v o n M a r c o n i C o m m u n ic a t io n s G m b H . W in d o w s is t e in e in g e t r a g e n e s M a r k e n z e ic h e n d e r M ic r o s o ft C o r p o r a t io n , R e d m o n d . M a r c o n i C o m m u n ic a t io n s G m b H D -7 1 5 2 0 B a ck n a n g T e le p h o n e + 4 9 (7 1 9 1 ) 1 3 -0 T e le f a x + 4 9 (7 1 9 1 ) 1 3 - 3 2 1 2 h t t p : / / w w w .m a r c o n i . c o m C o p y r ig h t 2 0 0 0 b y M a r c o n i C o m m u n ic a t io n s G m b H ( h e r e in r e f e r r e d to a s M a r c o n i) S p e c if ic a t io n s s u b je c t t o c h a n g e P r in t e d in G e r m a n y M a r c o n i , M a r c o n i C o m m u n i c a t i o n s , t h e M a r c o n i l o g o , t h e s w a s h 'M ', S k y b a n d , M D R S , M D M S a n d S e r v ice O n A cce ss a re tra d e m a rk s of M a r c o n i C o m m u n ic a t io n s G m b H . W in d o w s is a t r a d e m a r k o f M ic r o s o f t C o r p o r a tio n , R e d m o n d .

Notes
This Introduction to the Synchronous Digital Hierarchy is a company-internal brochure. Marconi Communications GmbH takes no responsibility for the correctness of its contents! Have you detected any faults or deficiencies? Do you have any new ideas? Please let us know them! Marconi Communications GmbH, Department: Customer documentation.

Attention: The ordering no. has changed with edition e. The new ordering no. is: 62.1013.105.11-A001 Ordering no. of previous editions: 62.1013.109.00-A001.

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Table of contents

Table of contents
1 Introduction
1.1 1.2 1.3 1.4 SDH functional model ............................................................................................................. 1-1 From the source signal to the transport frame ........................................................................ 1-2 Transport frame ...................................................................................................................... 1-7 Section Overhead ................................................................................................................... 1-9

Structures
2.1 2.2 2.3 Synchronous Transport Module Level 1 (STM-1) ................................................................... 2-1 Structure of the synchronous STM-1 frame ............................................................................ 2-1 SDH multiplex elements ......................................................................................................... 2.3.1 Container C .................................................................................................................... 2.3.2 Virtual container.............................................................................................................. 2.3.3 Administrative Unit.......................................................................................................... 2.3.4 Tributary Unit .................................................................................................................. 2.3.5 Tributary Unit Group ....................................................................................................... 2.3.6 Administrative Unit Group............................................................................................... 2-4 2-4 2-5 2-6 2-6 2-8 2-8

2.4 2.5 2.6 2.7 2.8

Concatenation....................................................................................................................... 2-13 Synchronous multiplexing ..................................................................................................... 2-14 Multiframe generation ........................................................................................................... 2-15 Error monitoring using BIP-X ................................................................................................ 2-17 SDH transmission sections................................................................................................... 2-18

3
3.1 3.2 3.3 3.4 3.5 3.6 3.7

Multiplex paths in the SDH

SDH multiplex scheme ........................................................................................................... 3-1 C-4 to STM-N.......................................................................................................................... 3-2 C-3 to STM-N.......................................................................................................................... 3-4 Two-step multiplexing of C-3 into STM-N ............................................................................... 3-6 C11, C12 and C2 to TUG-2 .................................................................................................... 3-8 TUG-2 to TUG-3 ................................................................................................................... 3-11 TUG-2 to VC-3...................................................................................................................... 3-12

Mapping procedures
4.1 4.2 4.3 4.4 4.5 Asynchronous mapping of 140 Mbit/s signals into VC-4 ........................................................ 4-1 Asynchronous mapping of 34 Mbit/s signals into VC-3 .......................................................... 4-4 Asynchronous mapping of 2 Mbit/s signals into VC-12 .......................................................... 4-6 Asynchronous mapping of 1.5 Mbit/s signals into VC-11 ....................................................... 4-7 Mapping 1.5 Mbit/s signals into VC-12 ................................................................................... 4-8

5
5.1

Overhead
Section Overhead ................................................................................................................... 5-1 5.1.1 Regenerator Section Overhead (RSOH) ........................................................................ 5-2 5.1.2 Multiplex Section Overhead (MSOH) ............................................................................. 5-2 Path Overhead........................................................................................................................ 5-3 5.2.1 Higher-order POH (VC-3/VC-4) ...................................................................................... 5-3 5.2.2 Lower-order POH (VC-1x/VC-2) ..................................................................................... 5-6

5.2

6
6.1

Pointers
Pointer value modification....................................................................................................... 6-1

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6.1.1 Setting a new pointer value ............................................................................................ 6-1 6.1.2 Frequency matching ....................................................................................................... 6-1 6.2 Pointer types ........................................................................................................................... 6-4 6.2.1 AU-3 pointer ................................................................................................................... 6-4 6.2.2 AU-4 pointer ................................................................................................................... 6-6 TU-3 pointer............................................................................................................................ 6-8 TU-2 pointer.......................................................................................................................... 6-10 TU-11 pointer........................................................................................................................ 6-12 TU-12 pointer........................................................................................................................ 6-14

6.3 6.4 6.5 6.6

Reference model
7.1 7.2 7.3 Lower-order path functions ..................................................................................................... 7-2 Higher-order path functions .................................................................................................... 7-2 Transport terminal functions ................................................................................................... 7-2

Applications
8.1 Synchronous line equipment .................................................................................................. 8-1 8.1.1 Synchronous line multiplexer.......................................................................................... 8-1 8.1.2 Synchronous line regenerator ........................................................................................ 8-2 Multiplexers............................................................................................................................. 8.2.1 Terminal Multiplexer ....................................................................................................... 8.2.2 Add/Drop Multiplexer ...................................................................................................... 8.2.3 Cross-connect Multiplexer .............................................................................................. 8-4 8-4 8-6 8-8

8.2

8.3

Networks............................................................................................................................... 8-10 8.3.1 Ring networks............................................................................................................... 8-11 8.3.2 Double rings ................................................................................................................. 8-11

Protection switching
9.1 9.2 9.3 Overview................................................................................................................................. 9-1 Definitions ............................................................................................................................... 9-1 Protection switching ................................................................................................................ 9.3.1 MS 1+1 protection .......................................................................................................... 9.3.2 MS 1:n protection ........................................................................................................... 9.3.3 MS shared protection ring .............................................................................................. 9.3.4 MS dedicated protection ring .......................................................................................... 9.3.5 Path/subnetwork protection ............................................................................................ 9.3.6 Protocols......................................................................................................................... 9-1 9-3 9-4 9-4 9-6 9-6 9-7

9.4 9.5

Network topologies ................................................................................................................. 9-8 Equipment protection............................................................................................................ 9-15

10 Literature Index

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List of figures

List of figures
Fig. 1-1 Fig. 1-2 Fig. 1-3 Fig. 1-4 Fig. 1-5 Fig. 1-6 Fig. 1-7 Fig. 1-8 Fig. 1-9 Fig. 2-1 Fig. 2-2 Fig. 2-3 Fig. 2-4 Fig. 2-5 Fig. 2-6 Fig. 2-7 Fig. 2-8 Fig. 2-9 Fig. 2-10 Fig. 2-11 Fig. 2-12 Fig. 2-13 Fig. 2-14 Fig. 2-15 Fig. 2-16 Fig. 3-1 Fig. 3-2 Fig. 3-3 Fig. 3-4 Fig. 3-5 Fig. 3-6 Fig. 3-7 Fig. 3-8 Fig. 3-9 Fig. 3-10 Fig. 3-11 Fig. 3-12 Fig. 4-1 Fig. 4-2 Fig. 4-3 Fig. 4-4 Fig. 4-5 Fig. 4-6 Fig. 4-7 Fig. 5-1 Fig. 5-2 Fig. 5-3 Fig. 5-4 Fig. 5-5 Fig. 5-6 Fig. 5-7 Fig. 6-1 Fig. 6-2 Fig. 6-3 Transmitter/receiver model ................................................................................................ 1-1 Conversion of a serial source signal into a block structure................................................ 1-2 Container ........................................................................................................................... 1-3 Container with label ........................................................................................................... 1-3 Transport frame ................................................................................................................. 1-4 Combining containers to a container group ....................................................................... 1-5 Concatenated containers................................................................................................... 1-6 Transport frame of the 1st hierarchy level ......................................................................... 1-7 Overhead with pointer........................................................................................................ 1-9 STM-1 frame...................................................................................................................... 2-1 Pointer ............................................................................................................................... 2-3 Containers ......................................................................................................................... 2-4 Virtual containers ............................................................................................................... 2-5 Administrative Unit............................................................................................................. 2-6 Tributary Unit ..................................................................................................................... 2-7 Tributary Unit Group .......................................................................................................... 2-8 Administrative Unit Group.................................................................................................. 2-8 Generation of an STM-1 signal from a 140 Mbit/s signal................................................... 2-9 Generation of an STM-1 signal in compliance with ETSI ................................................ 2-10 Generation of an STM-1 signal from a 2.048 Mbit/s signal.............................................. 2-11 Terminal Multiplexer 63 x 2.048 Mbit/s ............................................................................ 2-12 SDH multiplexing procedure ............................................................................................ 2-14 TU-1x/TU-2 Multiframe identification by the H4 byte ....................................................... 2-16 BIP-8 monitoring process ................................................................................................ 2-17 SDH digital signal sections .............................................................................................. 2-18 Synchronous multiplex structure in compliance with ITU-T Recommendation G.707 ....... 3-1 Multiplexing of AU-4 to AUG.............................................................................................. 3-2 Multiplexing N x AUGs into STM-N.................................................................................... 3-3 Multiplexing of three AU-3s into AUG ................................................................................ 3-4 Multiplexing of one TUG-3 into one VC-4 .......................................................................... 3-6 TU-3 pointer....................................................................................................................... 3-7 TU-11 Tributary Unit ......................................................................................................... 3-8 TU-12 Tributary Unit .......................................................................................................... 3-9 TU-2 Tributary Unit ............................................................................................................ 3-9 Multiplexing TU-11, TU-12 and TU-2 into TUG-2 ............................................................ 3-10 Multiplexing seven TUG-2s into one TUG-3 .................................................................... 3-11 Multiplexing seven TUG-2s into one VC-3....................................................................... 3-12 Splitting up VC-4 into 13-byte blocks................................................................................. 4-1 Asynchronous mapping of 140 Mbit/s signals into VC-4 ................................................... 4-2 VC-3 divided up into three partial frames .......................................................................... 4-4 Asynchronous mapping of 34 Mbit/s signals into VC-3 ..................................................... 4-4 Asynchronous mapping of 2 Mbit/s signals into VC-12 ..................................................... 4-6 Asynchronous mapping of 1.5 Mbit/s signals into VC-11 .................................................. 4-7 Conversion of a VC-11 into a VC-12 (1.5 Mbit/s in VC-12) ............................................... 4-8 Overhead bytes ................................................................................................................. 5-1 Higher-order POH.............................................................................................................. 5-3 VC3/VC4 path status (G1) ................................................................................................. 5-4 TU multiframe indicator H4 ................................................................................................ 5-5 Lower Order POH .............................................................................................................. 5-6 Bit assignment of the V5 byte ............................................................................................ 5-6 V5[5-7] Mapping Code....................................................................................................... 5-7 Pointer modification (positive justification)......................................................................... 6-2 Pointer modification (negative justification) ....................................................................... 6-3 AU-3 pointer....................................................................................................................... 6-4

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List of figures

Fig. 6-4 Fig. 6-5 Fig. 6-6 Fig. 6-7 Fig. 6-8 Fig. 6-9 Fig. 7-1 Fig. 8-1 Fig. 8-2 Fig. 8-3 Fig. 8-4 Fig. 8-5 Fig. 8-6 Fig. 8-7 Fig. 8-8 Fig. 8-9 Fig. 8-10 Fig. 8-11 Fig. 8-12 Fig. 8-13 Fig. 9-1 Fig. 9-2 Fig. 9-3 Fig. 9-4 Fig. 9-5 Fig. 9-6 Fig. 9-7 Fig. 9-8 Fig. 9-9 Fig. 9-10 Fig. 9-11

AU-4 pointer....................................................................................................................... 6-6 Multiplexing a VC-3 into a TUG-3 ...................................................................................... 6-8 TU-3 pointer....................................................................................................................... 6-9 TU-2 pointer..................................................................................................................... 6-10 TU-11 pointer................................................................................................................... 6-12 TU-12 pointer................................................................................................................... 6-14 Reference model for the design of SDH units ................................................................... 7-1 SLA4 and SLA16 synchronous line equipment (Example) ................................................ 8-1 Multiplex scheme in compliance with ITU G.707 ............................................................... 8-2 FlexPlex MS1/4 used as Terminal Multiplexer in an SDH network.................................... 8-4 Functioning of a Terminal Multiplexer................................................................................ 8-5 FlexPlex MS1/4 used as an Add/Drop Multiplexer in an SDH network ............................. 8-6 Functioning of an Add/Drop Multiplexer............................................................................. 8-7 FlexPlex MS1/4 used as Cross-connect Multiplexer in an SDH network .......................... 8-8 Functioning of a Cross-connect Multiplexer....................................................................... 8-9 Synchronous networks .................................................................................................... 8-10 Single ring network .......................................................................................................... 8-11 Double ring network......................................................................................................... 8-12 Interrupted double ring..................................................................................................... 8-12 Double ring connection of two ring networks ................................................................... 8-13 MSP 1+1 Multiplex Section Protection .............................................................................. 9-3 MS 1:n Protection Switch................................................................................................... 9-4 Example of the traffic flow in an MS shared protection ring............................................... 9-5 Example for the traffic flow in an MS dedicated protection ring......................................... 9-6 Path und subnetwork protection ........................................................................................ 9-7 Linear multiplexer chain with redundancy.......................................................................... 9-9 Path protection in a multiplexer chain................................................................................ 9-9 Examples for multiplexer rings with two and four connecting lines.................................. 9-11 Example for protection switching in interconnected rings................................................ 9-12 Interconnection of two rings with path protection............................................................. 9-13 Interconnection of two rings with MS shared protection .................................................. 9-14

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Introduction

1 Introduction
The Synchronous Digital Hierarchy (SDH) supersedes the previous Plesiochronous Digital Hierarchy (PDH) and provides a worldwide uniform multiplex hierarchy. Besides standardization, SDH systems offer further advantages for the setup and operation of modern network topologies: Simple multiplex process (no positive/negative justification) Network-wide standardized reference clock Direct access to individual channels High bit rates for broadband applications High transmission capacity for network monitoring and network control Control by highly efficient network management systems Integration of the previous plesiochronous multiplex hierarchy.

1.1 SDH functional model

The following transmitter/receiver model shows the transmission of source signals. The transmitter converts the incoming source signals into a SDHconforming structure. In doing this, the signals are assembled in defined transport frames. These frames are then transmitted to the receiver. The receiver extracts again the individual signals from the frame. The source signals can be both plesiochronous or synchronous.

Transport frame

2 Mbit/s 140 Mbit/s 2 Mbit/s

Receiver Transmitter

Receiver

2 Mbit/s 140 Mbit/s 2 Mbit/s

Transmitter

140 Mbit/s Fig. 1-1 Transmitter/receiver model

140 Mbit/s

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Introduction

1.2 From the source signal to the transport frame

The serial source signal (e.g. 140 Mbit/s) is at first converted into a byte-oriented block structure. In this block structure, the bytes are arranged in columns and rows. In the Synchronous Digital Hierarchy, the block structures are defined and have a certain size. The number of blocks per second is also specified. Example: Block size: 260 columns with 9 rows each consisting of 1 byte = 2340 Byte Number of blocks per second: 8000 This results in a transmission capacity of 260 columns x 9 rows x 8000 blocks per second = 18,720 kbyte/s or 149,760 kbit/s. The above calculation shows that the transmission capacity of the blocks is larger than the bit rate of the source signal. In order to compensate this difference, each block must contain a certain amount of justification, i.e. stuffing information.

Serial bit stream, e.g. 140 Mbit/s + stuffing information

1 0 0 1 1 1 0 1 0 1 1 1 ...

1 byte
9CH
1 260 260 1 260

9C ... ... ... ... ... ... ... ...

72 ... ... ... ... ... ... ... ...

33 ... ... ... ... ... ... ... ...

A4 ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ...

9C

Fig. 1-2 Conversion of a serial source signal into a block structure

1-2

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Introduction

Containers
The transmission of SDH signals can be compared with the transmission of containers on a conveyor belt. The payload is transported in containers of certain sizes. Since the payloads have different volumes, containers with different capacities have been defined. If the payload is too small, it is filled up with stuffing information.

t Co n

r aine

Fig. 1-3 Container For transporting the information, the container needs a label. The latter includes information on the container contents, monitoring data etc. The receiver evaluates this information. Payload Blind information
er tain Con

Label Fig. 1-4 Container with label The complete containers are then put on a kind of conveyor belt. This conveyor belt is divided up into several frames of identical size. They are used to transport the containers.

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Introduction

The position of the containers in the frame is arbitrary, i.e. a container does not have to start at the beginning of the frame. A container can be located on two adjacent frames.
iner

ta Con

t Co n
n ssio

r aine

n ctio D i re

of

s mi t ra n

Start of frame

Empty frame

Fig. 1-5 Transport frame

1-4

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Introduction

Groups of containers
The type of payload in the containers is unimportant for transportation. The stuffing information can therefore be regarded as part of the payload. Before transportation, several small containers can be combined to form a group. This group is then packed into a larger container. Each of these containers includes a label which is evaluated by the receiver. Whenever necessary, stuffing information is added. The individual containers are assigned a certain position within the group. The position no. determines the start of the respective container.

Stuffing information

Position within the container

Fig. 1-6 Combining containers to a container group

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Introduction

Concatenation
The above description was based on the assumption that the payload is smaller than the container available. If the payload to be transported is larger than the container available for it, several containers can be concatenated. They then form a continuous container chain. In this case, the payload is distributed on this container chain. Example: The source signal is 599.04 Mbit/s (broadband ISDN). Since the largest container defined can transport only a signal up to 140 Mbit/s, four such containers have to be concatenated. The position of the container chain on the conveyor belt is defined for the first container. The position of all other containers 2, 3 and 4 is determined by the first one. 1st container 2nd container 3rd container 4th container

Position Start of frame Fig. 1-7 Concatenated containers

Concatenation

1-6

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Introduction

1.3 Transport frame

The transport frame represents the transmission medium for the containers. It has a block structure similiar to that of a container, i.e. it is composed of N columns and M rows (N= 270, M=9). In order to meet the different capacity requirements, different sizes of transport frames have been defined. These subdivisions are referred to as hierarchy levels. Example: Transport frame of the 1st hierarchy level It is composed of 270 columns and 9 rows. The first 9 columns are reserved for special transport functions. The other 261 columns are used to transport payload signals. 8000 frames are transported per second. This corresponds to a frame duration of 125 s. 270 columns 9 columns 261 columns

9 rows

Additional transport capacity

Payload area

Fig. 1-8 Transport frame of the 1st hierarchy level The Additional transport capacity has a transmission capacity of 9 (columns) x 9 (rows) x 8 (bits) x 8000 (frames per second) = 5.184 Mbit/s. This area is referred to as Section Overhead. In addition to the payload (which can be arbitrarily structured), additional payload-independent information is transmitted. The Section Overhead is transmitted even when there is no payload.

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Hierarchy levels
The transport frame of the higher hierarchy levels differ from each other only with respect to the number of columns. The following hierarchy levels have been defined: Hierarchy level 1 4 16 Number of columns 270 1080 (4 x 270) 4320 (16 x 270) Number of rows 9 9 9 Transport capacity 155.520 Mbit/s 622.080 Mbit/s 2488.320 Mbit/s

Table 1-1 Hierarchy levels

1-8

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Introduction

1.4 Section Overhead

The Section Overhead is a minicontainer containing various information required for transmission. The Section Overhead offers free capacity which can be used for additional information. The Section Overhead always starts at the beginning of the transport frame. The Section Overhead also includes a pointer defining the position of the containers in the payload area. The pointer value, also referred to as offset, indicates the offset of the container with respect to a reference point of the frame. The pointer, however, is not part of the Section Overhead! Before a container is placed on the conveyor belt (add function), the pointer value is calculated and the container is placed e.g. in position 30, calculated from the end of the fixed pointer position. On taking the container from the conveyor belt (drop function), the pointer is evaluated and the position of the container determined. The pointer also permits a dynamic adaptation of the container to the transport frame. This means that the container can be moved on the conveyor belt in both directions by changing the offset value. If a container is to be shifted to another conveyor belt (cross-connect), this is also done by means of the pointer.

ti o n irec

r of t

on issi nsm a
nter Poi

ter Poin

Section Overhead
nter Poi

70

30
ter Poin

Cro

ssc on

ne c t
nter Poi

Position of pointer in the Section Overhead

nter

60

P oi

40
ter Poin

Reference point

Add/Drop

Fig. 1-9 Overhead with pointer

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2 Structures
2.1 Synchronous Transport Module Level 1 (STM-1)
The Synchronous Digital Hierarchy (SDH) defines the Synchronous Transport Module Level 1 (STM-1) as multiplex signal of the lowest level. It has a transmission rate of 155.520 Mbit/s. The STM-N bit rates of the standardized higher hierarchy level (N= 4 and 16) are always higher by factor 4.
Transport capacity in kbit/s 155 520 622 020 2 488 320 Interface Electrical G.703 Optical G.957 G.957 G.957

Synchronous Hierarchy Transport Module level STM-1 STM-4 STM-16 1 4 16

Table 2-1 Allocation of transmission capacity to transport modules

An STM-N multiplex signal is formed by interleaving the individual STM-1 frames byte by byte.

2.2 Structure of the synchronous STM-1 frame

The following diagram shows the structure of the byte-oriented STM-1 frame. The frame is composed of 270 columns and 9 rows. An STM-4-(16) frame has 4 (16) * 270 columns and also 9 rows.
270 Bytes 1 1 SOH 9

Pointer 9 rows Payload

SOH 9 19440 bits or 2430 bytes/frame Bit length: 6.4300411 ns Transmission bit rate: 155.520 Mbit/s Frame length: 125 s

Fig. 2-1 STM-1 frame

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Structures

The first 9 columns include the Section Overhead (SOH) and the Pointer of the Administrative Unit (AU pointer). The remaining 261 columns are used for transporting the payload. It consists of packed and multiplexed payload signals (tributaries) and an accompanying Path Overhead (POH). The repetition frequency of the STM-1 frame is 8 kHz, i.e. one STM-1 frame has a length of 125 s. The transmission capacity of one byte in an STM-N frame is thus 64 kbit/s. With STM-1, an Overhead capacity of 5184 kbit/s is transported in addition to the traffic bit rate of 150,336 kbit/s. Bit rates of the STM-1 frame
Columns x rows x 64 kbit/s STM-1 frame Section-Overhead Payload 270 x 9 x 64 kbit/s 9 x 9 x 64 kbit/s 261 x 9 x 64 kbit/s Bit rate 155,520 kbit/s 5,184 kbit/s 150,336 kbit/s

Table 2-2 Bit rates in the STM-1 frame

2-2

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Structures

The payload has no fixed phase relation to the STM-N frame. In order to be able to access the payload, the Section Overhead block contains a pointer. It is located in the 4th row of the STM-N frame.
Payload
522 ...

SOH

...

782

STM-1

Pointer

310

...

310 522

...

522

...

...

782

Pointer

3101
310

...

310

...

Fig. 2-2 Pointer The pointer indicates the beginning of the payload frame and permits the payload to be directly accessed. The first byte of the payload frame (byte 0) follows the last pointer byte. Bytes 522 to 782 are located in front of the pointer. Pointer values higher than 521 are thus pointing at the next STM frame!

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Structures

2.3 SDH multiplex elements

In the SDH, only synchronous signals with an STM-N structure are transmitted. However, tributary signals, i.e. signals received by synchronous multiplexers, are currently still plesiochronous. For this reason, they have to be converted into the clock-synchronous block structure of the payload before being transmitted. A block structure is a frame with a certain number of columns and rows.

2.3.1 Container C
The transmission capacity of the incoming source signal is smaller than the capacity of the block structure. The source signal is therefore filled up by adding stuffing information (positive justification). The process of filling up the incoming information to obtain the defined block structure is referred to as mapping. The complete block structure is called Container C. Different container sizes (e.g. C-11, C-12, C-2, C-3, C-4) are available for the different source signal bit rates. The digit in the container designation indicates the hierarchy level of the plesiochronous signal (e.g. C-4 for 140 Mbit/s). If several containers for different bit rates are available within one hierarchy level, a second digit defines the bit rate assignment (C-11=1,5 Mbit/s, C-12=2 Mbit/s). 1 260 1 84

C-4

C-3

12

C-2

C-12

C-11

Hierarchy

Bit rate assignment

1.5 Mbit/s + stuffing bits 2 Mbit/s + stuffing bits 6 Mbit/s + stuffing bits 45 (34) Mbit/s + stuffing bits 140 Mbit/s + stuffing bits Fig. 2-3 Containers

C-11 C-12 C-2 C-3 C-4

2-4

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Structures

2.3.2 Virtual container

Each container is completed with a Path Overhead (POH) which is used to monitor and control the correct addressing as well as to identify the container contents. The POH + C-n entity is referred to as Virtual Container (VC-n) and is transported within the synchronous network from the source to the sink, i.e. over the complete path. The name convention is identical with that of normal containers. Note: The POH of VC-11, VC-12 or VC-2 is composed of four bytes (V5/J2/N2/K4). One byte of this POH is transmitted per VC-n, thus leading to the generation of a multiframe.

261

85

POH

C-4

POH

C-3

VC-4 1 POH C-2 VC-2 12 POH C-12 VC-12 1 4 POH C-11 1

VC-3 3

VC-11

C-11 + POH C-12 + POH C-2 + POH C-3 + POH C-4 + POH

VC-11 VC-12 VC-2 VC-3 VC-4

Fig. 2-4 Virtual containers

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2.3.3 Administrative Unit

The AU pointer provides the phase relation between the start of VC-3 or VC-4 and the reference point of the STM-1 frame. By adding the pointer value, the VC-3/VC-4 becomes an Administrative Unit (AU-3/AU-4). The payload of an STM-1 signal consists of one AU-4 or three AU-3s. AU-4 1 9 10 270

AU-4 pointer VC-4

AU-3 123 4 AU-3 pointer VC-3 VC-4 + AU-4 pointer VC-3 + AU-3 pointer Fig. 2-5 Administrative Unit 90

AU-4 AU-3

2.3.4 Tributary Unit

The Virtual Containers VC-11, VC-12 and VC-2 are completed to a Tributary Unit by adding the pointer. This results in the following TU structures of the individual columns and rows: TU-11: 9 rows x 3 columns TU-12: 9 rows x 4 columns TU-2: 9 rows x 12 columns TU-3: 9 row x 86 columns In TU-11, TU-12 and TU-2, there is only space for one pointer byte. However, three bytes are required for the pointer operations. In order to be able to transport these bytes, a multiframe has been defined (see Multiframe generation on page 16). The position of the pointer bytes is depicted in the alternative illustration (see next figure). The V1 and V2 bytes form the TU pointer. Byte V3 is available for a dynamic increase in the payload (stuffing). VC-3 can also be completed to form a TU-3 instead of an AU-3.

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Structures

1
V

12

TU-2
in frame #1

TU-2
in frame #2

TU-2
in frame #3

TU-2
in frame #4

TU-2

V1 321 322 ... 426 427 V2

... 105 106 V3 107 108 ... 212 213 V4 214 215 ... 319 320

Pointer bytes 1
V

TU-12
in frame #1

TU-12
in frame #2
0 1 ...

TU-12
in frame #3
...

TU-12
in frame #4
68 69 V4 70 71 ... 103 104

TU-12
V1 105 106 ... 138 139 V2 33 34 V3 35 36

Pointer bytes 1
V

TU-11
in frame #1

TU-11
in frame #2
0 1 ...

TU-11
in frame #3
...

TU-11
in frame #4
50 51 V4 52 53 ... 76 77

TU-11
V1 78 79 ... 102 103 V2 24 25 V3 26 27

Pointer bytes

TU-3 1 Pointer bytes

H1 H2 H3

86

VC-3

H1 595 596 ... H2 ... 763 764 H3

...

VC-2 + TU-2 pointer TU-2 VC-12 + TU-12 pointer TU-12 VC-11 + TU-11 pointer TU-11 or VC-11 + stuff. info + TU-12 pointer TU-12 VC-3 + TU-3 pointer TU-3 Fig. 2-6 Tributary Unit

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Structures

2.3.5 Tributary Unit Group

The Tributary Units are multiplexed to so-called Tributary Unit Groups (TUGs). These Tributary Unit Groups represent an arrangement of blockstructured signals with a frame length of 125 s. TUG-3 1 12 1 86

TUG-2 Stuffing information 4 x TU-11 TUG-2 3 x TU-12 TUG-2 1 x TU-2 TUG-2 7 x TUG-2 + stuff. info TUG-3 1 x TU-3 + stuff. info TUG-3 Fig. 2-7 Tributary Unit Group

TU-3

2.3.6 Administrative Unit Group

On multiplexing the AU-N into STM-N, an Administrative Unit Group (AUG) is formed by three AU-3s or one AU-4. The three AU-3s are interleaved byte by byte. The Administrative Unit Group (AUG) represents an information structure composed of 9 rows each consisting of 261 columns plus 9 bytes in row 4 for the AU pointers. AUG 10 270

Space for 3 AU-3 or 1 AU-4 pointers 1x AU-4 3x AU-3 AUG AUG

Fig. 2-8 Administrative Unit Group

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Examples
With 140 Mbit/s signals, the generation of an STM-1 signal can be described as follows: 1. 2. 3. 4. Filling up the 140 Mbit/s signal with stuffing bits -> Adding the Path Overhead (POH)-> Calculating and adding the pointer -> Adding the Section Overhead (SOH) -> C-4 VC-4 AU-4 STM-1

In this case, AUG and AU-4 are identical, i.e. the AUG does not have to be separately illustrated in the following figure.
270 bytes 9 1

3 1

SOH PTR POH SOH PTR POH POH C

Payload

STM-1

AU-4

VC-4

C-4 140 Mbit/s signal

Fig. 2-9 Generation of an STM-1 signal from a 140 Mbit/s signal

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Structures

Bit rate < 140 Mbit/s

At bit rates lower than 140 Mbit/s, the plesiochronous signals are converted into an STM-1 signal via a 2-step procedure. .

Filling up the tributary bit rate with stuffing bits

No

<140 Mbit/s

No

<140

Adding the Path Overhead Calculating and adding the pointer

P O H P T R

VC

No

<34 Mbit/s

No

<34

Generating TUG-2

TUG-2

Generating TUG-3

TUG-3

Adding the Path Overhead Calculating and adding the pointer

P O C-4 H P T VC-4 R S O AU-4 H STM-1

Adding the Section Overhead

Fig. 2-10 Generation of an STM-1 signal in compliance with ETSI

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The following diagram shows how a 2.048 Mbit/s signal is converted into an STM-1 signal via the different multiplex steps.
9 bytes 270 bytes

SOH Pointer VC-4 POH stuff. info Pointer SOH stuff. info TUG-2 TU-12 f TUG-3

9 bytes

STM-1 AU-4 VC-4 TUG-3 TUG-2 TU-12 VC-12 C-12 Payload

2.048 Mbit/s + stuffing info
TU-12 pointer VC-12 POH

x1 STM-1 AU-4 VC-4

x3 TUG-3

x7 TUG-2

x3 TU-12 VC-12 C-12 2.048 Mbit/s

Fig. 2-11 Generation of an STM-1 signal from a 2.048 Mbit/s signal The maximum number of 2.048 Mbit/s signals can be calculated as follows: 3 (TU-12) x 7 (TUG-2) x 3 (TUG-3) x 1 (VC-4) = 63 x 2.048 Mbit/s A maximum of 63 x 2.048 Mbit/s signals can thus be assembled in one STM-1 signal. This is shown in the next figure. The individual 2.048 Mbit/s signals are subjected to the same multiplex procedure in both the transmit and receive direction, however, in the opposite order. For this reason, the two directions are not separately depicted. For further simplification, tributary signals of the same type (e.g. 2.048 Mbit/s) are shown only one time. All intermediate steps of the same type (e.g. TUG-2) are also illustrated only once. The application of this principle to all tributary signals defined results in the SDH multiplex scheme described in chapter 3 below.

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Structures

TU-12 TUG-2 TU-12 TU-12 TU-12 TUG-2 TU-12 TU-12 TU-12 TUG-2 TU-12 TU-12 TU-12 TUG-3 TUG-2 TU-12 TU-12 TU-12 TUG-2 STM-1 AU-4 VC-4 TU-12 TU-12 TU-12 TUG-2 TU-12 TU-12 TU-12 TUG-2 TU-12 TU-12

VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12 VC-12

C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12 C-12

2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s 2.048 Mbit/s

TUG-3

7x

21 x 2.048 Mbit/s

TUG-3

7x

21 x 2.048 Mbit/s

Fig. 2-12 Terminal Multiplexer 63 x 2.048 Mbit/s

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2.4 Concatenation
If the payload is larger than the container available for it, it can be distributed to several consecutive containers. The individual containers are concatenated by means of a special pointer value. This pointer value is referred to as Concatenation Indication. Example of a VC-4 concatenation A number of four VC-4 containers are required for an ATM cell stream of the broadband ISDN with a bit rate of 599.04 Mbit/s. In the first VC-4, a valid POH is generated. The other three VC-4s are only filled up with payload and are assembled to form one VC-4-4c Virtual Container. By adding the pointer, the VC-4-4c is converted into the AU-4-4c group. The first AU-4 of the AU-4-4c group is provided with a pointer. All other AUs contained in the AU-4-4c group receive the pointer value which indicates the concatenation of the containers. All following AUs within the AU-4-4c group receive the Concatenation Indication (CI) instead of the pointer value. The CI is composed as follows: 1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1

The CI value indicates that this AU-4 belongs to the previous AU-4 and that all pointer operations of the first AU-4 shall be executed on all AU-4 units contained in the AU-4-4c group.

A VC-4 concatenation is possible only in STM-N frames with N > 1, e.g. STM-4 frames.

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Structures

2.5 Synchronous multiplexing

The STM-N multiplex signal is generated by interleaving the individual STM-1 frames byte by byte. The STM-1 frames are numbered in the sequence in which they appear in the STM-N frame. The third STM-1 frame (STM-1#3) starts, for example, in the 3rd column of the STM-N frame. In this connection, it is pointed out that the Section Overheads (SOH) of the individual STM-1 signals are not interleaved. The multiplex procedure used for generating lower-order multiplex elements (TUG-2, TUG-3 etc.) is identical with the one used for generating STM-N signals. The demultiplexing procedure (disassembling the multiplex signal into the individual STM-1 frames, TUG-3, TUG-2) is performed in the same way, however, in the opposite order.

STM-1#1
1 9 10 11 12 13 270 1

STM-1#2
9 10 11 12 13 270 1

STM-1#3
9 10 11 12 13 270 1

STM-1#4
9 10 11 12 13 270

SOH
Pointer

SOH
Pointer

SOH
Pointer

SOH
Pointer

SOH
125s

SOH
125s

SOH
125s

SOH
125s

SOH is newly inserted, not interleaved!

10 10 10 1 1 1 1 9 9 9

Byte interleaving
10 11 11 11 12 12 13 11 12 13 12 13 13

270 270 270 270

4x9 Pointer

STM-4 frame SOH

4x9 4 x 261

Payload

SOH

SOH
125s

Fig. 2-13 SDH multiplexing procedure

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Structures

2.6 Multiframe generation

The TU-11, TU-12 and TU-2 frames offer space for only one pointer byte. However, three bytes are required for the pointer operations, i.e. two bytes for addressing and one byte for the negative justification process. A fourth byte is to be provided as spare byte. For this reason, several TU frames are combined to form a multiframe. The pointer bytes are then distributed to these consecutive TU frames. The still separate TU frames are arranged in a TUG-2 unit. In compliance with the multiplex structure, they can be accommodated in a VC-3 or via TUG-3 in a VC-4. This VC-3 /VC-4 is finally converted into an STM-1 frame. In order to ensure that the receiver knows that the VC-3/VC-4 includes Tributary Units with a multiframe, a so-called multiframe indicator (H4) is set and transmitted in the POH of VC-3/VC-4. The receiver evaluates this indicator and interprets the pointer bytes in the individual TUs correspondingly. The relevant ITU-T Recommendations currently only define the 500 s multiframe: 500 s (4 frames) for byte-asynchronous payloads in VC-11, VC-12 and VC-2 (floating mode).

Example:

The system generates a TU multiframe composed of four TU-2 frames. The TU-2 Tributary Units are converted via TUG-2 into a VC-3. The TU pointer bytes V1 to V4 are distributed to four consecutive VC-3s. By means of a counting process, the H4 byte determines the VC-3 frames containing the individual pointer bytes. H4 = x x x x x x 0 0 indicates that the next VC-3/VC-4 frame includes the V1 pointer byte. .

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Structures

VC-3/VC-4 POH V4 VC-3/VC-4 Payload 9 rows

H4 (00)

V1 VC-3/VC-4 Payload

H4 (01)

V2 VC-3/VC-4 Payload

H4 (10)

V3 VC-3/VC-4 Payload

H4 (11)

V4 VC-3/VC-4 Payload

H4 (00)

Fig. 2-14 TU-1x/TU-2 Multiframe identification by the H4 byte

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Structures

2.7 Error monitoring using BIP-X

Bit Interleaved Parity X (BIP-X) is a method used for monitoring a signal for bit errors. This method consists in adding an additional information of X bits to a defined length of the signal to be monitored (e.g. one frame). In the SDH, X can assume the values 2, 8 and 24. Example: BIP-8 Starting from the first bit of the signal to be monitored, every eighth bit is analyzed in order to determine the number of logic ones. Then the first bit of the BIP-8 value is defined so that together with this bit, there is an even number of logic ones. Then the same process is executed starting from the second bit of the signal to be monitored, i.e. every eighth bit is analyzed and the second bit of the BIP-8 value is defined by applying the same rule. This calculation is performed for all eight bits of the BIP-8 value. The result is then transmitted together with the signal to the opposite station. There the same calculation is performed. Possible deviations of the calculated value from the transmitted BIP-8 value permit transmission errors to be detected. A maximum of 8 parity violations can be identified by means of one BIP-8 value on condition that these parity violations are statistically distributed. The BIP-2 and BIP-24 monitoring process is based on the same principle. The BIP-2 value to be transmitted is composed of two bits, the BIP-24 value of three bytes. Before being transmitted, the signals are scrambled. On reception, they are descrambled. The BIP value is calculated in front of the scrambler and inserted in the next frame also in front of the scrambler. 1 9 17 25 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1
+ + + + + + + + + + + + + + + + + + + + + + + + + + +

Signal 1st bit 1 1 0 1

CBH <-

1 1 0 1 0 0 1 1

0 0 1 1

BIP-8 value

Result from signal

Fig. 2-15 BIP-8 monitoring process

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Structures

2.8 SDH transmission sections

From its assembly to its disassembly, a container passes the transmission sections shown in the diagram below. The C3 container can either be injected directly into the higher-order path or via an upstream stage into the lowerorder path (also see multiplex structure). The Multiplex Section represents the section between two multiplexers. A Regenerator Section is located between a multiplexer and a regenerator or between two regenerators. The overheads are generated or terminated in accordance with these sections. The SOH of a Regenerator Section (RSOH) is disassembled and newly inserted at each regenerator. The MSOH is transmitted between two multiplexers. The Path Overhead (POH) accompanies the container all over the paths. In accordance with the two paths available, they are referred to as lower-order POH or higher-order POH.
Lower-order path Higher-order path Multiplex Section

VC-4 Assembler

C-3

VC-4 Assembler

VC-3 Assembler

Regenerator Section Regenerator STM-N Multiplexer Regenerator STM-N Multiplexer

VC-3 Assembler

C-3

VC-3, VC4 Assembler

C-3, C-4

VC-3, VC4 Assembler

C-11, C-12, C-2

VC-11, VC-12, VC-2 Assembler

VC-11, VC-12, VC-2 Assembler

C-11, C-12, C-2

STM-N RSOH

C-3, C-4

STM-N MSOH

VC-3, VC-4 POH VC-11, VC-12-, VC-2-, VC-3POH

SOH = Section Overhead (assigned to the transmission section) POH = Path Overhead (assigned to the virtual container)

Fig. 2-16 SDH digital signal sections

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Multiplex paths in the SDH

3 Multiplex paths in the SDH

3.1 SDH multiplex scheme
The source signals received are assembled in the corresponding containers, provided with the POH and pointer and converted into a STM-1 signal via the different multiplex steps. Source signals with bit rates higher than 139.264 Mbit/s are multiplexed into the STM-1 frame in one step, those with lower bit rates in two steps. The multiplex paths (demultiplex paths) for the individual source signals are combined to a multiplex scheme. This multiplex scheme complies with ITU-T G.707 and includes optional multiplex paths. The VC-3 can e.g. be multiplexed via TU-3 into VC-4 or the AU-3 path can be selected. A distinction is made between the lower-order and higher-order path. For SDH signals there are two levels which are used to set up the phase relation using pointers: TU-11, TU-12, TU-2 and TU-3 being the lower level and AU3, AU-4 being the higher level.

xN STM-N N = 1, 4 AUG

x1 AU-4 VC-4 x3 x1 x3 TUG-3 TUG-3 TU-3 VC-3 VC-3 C-4

139.264 Mbit/s 44.736 Mbit/s

C-3 34.368 Mbit/s

AU-3

VC-3 x7 x7 x1 x3 TUG-2 x4 TU-12 TU-2 VC-2 C-2 see note 6.312 Mbit/s 2.048 Mbit/s 1.544 Mbit/s

VC-12

C-12

Pointer processing Note 8 Mbit/s and non-hierarchical bit rates can be mapped into concatenated VC-2 virtual containers.

TU-11

VC-11

C-11

Fig. 3-1 Synchronous multiplex structure in compliance with ITU-T Recommendation G.707 The following chapter contains a detailed description of the individual sections and elements of the multiplex structure. The assembly of payload signals in containers is explained in a separate chapter.

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Multiplex paths in the SDH

3.2 C-4 to STM-N

xN STM-N N=1, 4 AUG x1 AU-4 VC-4 C-4 139,264 Mbit/s

C-4 to AU-4
The 139.264 Mbit/s signal is assembled in a C-4 container. Then the VC-5 is generated by adding the POH. It is composed of 261 columns, each consisting of 9 rows. By adding the AU-4 pointer, the VC-4 is converted into an AU-4. The AU pointer indicates the relative offset between the frame start of the VC and the STM-1 frame.

AU-4 to AUG
The AU-4 Administrative Unit is converted into an AUG arrangement. The AUG represents an information structure composed of 9 rows consisting of 261 columns plus 9 additional bytes in row 4 for the AU pointers. In the example depicted below, the AUG consists of one VC-4 and one AU-4 pointer. The AU-4 and AUG are identical. 1
J1 B3 C2 G1 VC-4-POH F2 H4 F3 K3 N1

261

C-4

VC-4

no fixed phase

H1 Y Y H2 1* 1* H3 H3 H3

AU-4

fixed phase

AUG

Fig. 3-2 Multiplexing of AU-4 to AUG

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AUG to STM-N
The AUGs generated this way can now be either assembled in a STM-1 frame by mapping in an AUG directly or in an STM-N frame by multiplexing N x AUGs byte by byte. 10 1 9
#1

261 1 9

10

261

#2

AUG

AUG

SOH 123...N123...N SOH

123...N123...N

Nx9

N x 261 STM-N

Fig. 3-3 Multiplexing N x AUGs into STM-N

Phase relation
The phase of the VC-4 has no fixed relation to the STM-N frame. The AU-4 pointer indicates the frame start of VC-4. This pointer is transmitted in the STM-N signal and establishes thus the phase relation to the STM-N frame. The AU-4 pointer has a defined phase relation to the AUG and thus to the STM-N frame.

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3.3 C-3 to STM-N

.

xN STM-N N=1, 4 AUG

x3 AU-3 VC-3 C-3

44,736 Mbit/s 34,368 Mbit/s

The 34.368 Mbit/s signal (44.736 Mbit/s) is assembled in a C-3 container. Then the VC-3 is generated by adding the POH. This virtual container is composed of 85 columns with 9 rows each. For mapping three VC-3s into a AUG, two columns with fixed stuffing information must at first be inserted in VC-3 (3 x (85 +2) = 261).
1 30 59 87 1 30 59 87 1 30 59 87

VC-3

J1 B3 C2 G1 F2 H4 F3 K3 N1

VC-3

J1 B3 C2 G1 F2 H4 F3 K3 N1

VC-3

J1 B3 C2 G1 F2 H4 F3 K3 N1

VC-3-POH

no fixed phase

VC-3-POH

no fixed phase

VC-3-POH

no fixed phase

AU-3
H1 H2 H3

AU-3
H1 H2 H3

AU-3
H1 H2 H3

A B A B C A B C A B C C

A B C

AUG

A B C

Fig. 3-4 Multiplexing of three AU-3s into AUG In order to achieve a relatively uniform distribution of this stuffing information, it is inserted in columns 30 and 59. These extended VC-3s obtain their phase relation to the STM-N signal by adding an AU-3 pointer. The three AU-3s generated have the same fixed phase relation to the STM-N signal. The structure of the AUG is filled by multiplexing the three AU-3s byte by byte.

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The AUGs thus generated can now be assembled in an STM-1 frame by mapping in an AUG directly or in a STM-N frame by multiplexing N x AUGs byte by byte. In this connection, it is of no importance whether the AUGs contain AU-3s or AU-4s, since the structure (261 columns each with 9 rows + 9 bytes for pointer) is always the same.

Phase relation
The phase of the VC-3 has no fixed relation to the STM-N frame. The AU-3 pointer indicates the frame start of the VC-3. This pointer is transmitted in the STM-N signal and establishes thus the phase relation to the STM frame. For each VC-3, the STM-N transmits one pointer, i.e. it contains a total of three pointers. The AU-3 pointer has a defined phase relation to the AUG and thus to the STM-N frame.

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3.4 Two-step multiplexing of C-3 into STM-N

xN STM-N N=1, 4 AUG

x1 AU-4 VC-4 x3 x1 TUG-3 TUG-3 TU-3 VC-3 VC-3 44.736 Mbit/s C-3 34.368 Mbit/s

The 34.368 Mbit/s signal (44.736 Mbit/s) is assembled in a C-3 container. Then the VC-3 is generated by adding the POH. This virtual container is composed of 85 columns, each consisting of 9 rows. By providing the VC-3 with a pointer, the TU-3 Tributary Unit is generated. This TU-3 is then converted into a TUG-3 arrangement by adding stuffing information. A TUG-3 is composed of 86 columns. Up to three TUG-3s can be multiplexed into one VC-4. A VC-4 has a POH and is composed of 261 columns. Behind the POH of the VC-4, two columns with fixed stuffing information (pos. justification bits) are inserted. In the remaining 258 columns, the three TUG-3s are multiplexed by turns into the VC-3 byte by byte. This process results in a total of 3 x 86 + 2 + 1 = 261 columns.
1 86 1 86 1 86

TUG-3 (A)

TUG-3 (B)

TUG-3 (C)

Stuffing information

P O H

VC-4
A B C A B C A B C A B C A B C

1 2 3 4 5 6 7 8 9 10 11 12

261

Fig. 3-5 Multiplexing of one TUG-3 into one VC-4

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Phase relation
In the first three bytes of the first column, the TU-3 pointer sets up the phase relation between VC-3 and TUG-3. 86 columns TU-3 pointer
H1 H2 H3

TUG-3 85 columns
J1 B3 C2 G1 F2 H4 F3 K3 N1

Stuffing bits

C-3

VC-3

VC-3-POH

Fig. 3-6 TU-3 pointer TUG-3 has a fixed phase relation to VC-4. AU-4 sets up the phase relation to the STM-N signal.

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3.5 C11, C12 and C2 to TUG-2

x1 x3 TUG-2 x4

TU-2

VC-2

C-2

6.312 Mbit/s 2.048 Mbit/s 1.544 Mbit/s

TU-12

VC-12

C-12

TU-11

VC-11

C-11

Depending on their bit rate, the payload signals are assembled in containers C-n of appropriate size. The Virtual Containers (VC-n) are generated by adding the POHs. By providing these VC-n containers with their pointers, the TU-n Tributary Units are generated. Since all SDH stuctures are based on a structure composed of 9 rows, the TUs can be described as a structure with a certain number of columns and nine rows.

TU-11
The capacity of a TU-11 is 1,728 kbit/s = 27 bytes per 125 s. A TU-11 can be described as a structure composed of three columns and nine rows.

1 2 9 rows

3 columns 1 2 3 1,728 kbit/s

TU-11 27 bytes

27

27 125 s Fig. 3-7 TU-11 Tributary Unit

TU-12
The capacity of a TU-12 is 2,304 kbit/s = 36 bytes per 125 s. A TU-12 can be described as a structure composed of four columns and nine rows.

3-8

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1 2 9 rows

4 columns 1 2 3 4 2,304 kbit/s

TU-12 36 bytes

36

36 125 s Fig. 3-8 TU-12 Tributary Unit

TU-2
The capacity of a TU-2 is 6,912 kbit/s = 108 bytes per 125 s. A TU-2 can be described as a structure composed of 12 columns and nine rows. 1 2 9 rows 12 columns 1 2 3 4 5 6 7 8 9 10 11 12

TU-2 108 bytes

108

6912 kbit/s 108 125 s Fig. 3-9 TU-2 Tributary Unit

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Multiplex paths in the SDH

TUG-2
A TUG-2 is generated by multiplexing 4 x TU-11 or 3 x TU-12 or 1 x TU-2 column by column. Thus, the TUG-2 frame represents an arrangement in which each byte of a TU has its fixed position. TU-11 TU-12 TU-2

4x
1 1 2 3 4 2 3 4 1 2

3x
1 2 3 4 3 1 2 3 1 2 3 1 2

1x

TUG-2

Fig. 3-10 Multiplexing TU-11, TU-12 and TU-2 into TUG-2

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3.6 TUG-2 to TUG-3

TUG-3 x7

x1 x3

TU-2

VC-2

C-2

6.312 Mbit/s 2.048 Mbit/s 1.544 Mbit/s

TUG-2 x4

TU-12

VC-12

C-12

TU-11

VC-11

C-11

A TUG-3 frame can be filled by multiplexing seven TUG-2 frames byte by byte. The first two columns are contain stuffing information. TU-11 TU-12 TU-2

1 2 3 4 2 3 4

1 2 3 4

1 2 3

1 2 3

1 2 3

1 2 3

TUG-2

(1)

(2)

(3)

(7)

1 2 Stuffing info 3 4 5 6 7 1 234 . . .

1 2 3 4 5 6 7

1 2 3 4 5 6 7

1 2 3 4 5 6 7

1 2

TUG-3

3 4 5 6 7 82 84 86

Fig. 3-11 Multiplexing seven TUG-2s into one TUG-3

Phase relation
The TU-11, TU-12 and TU-2 Tributary Units and the TUG-2 and TUG-3 Tributary Unit Groups have a fixed phase relation to each other. A direct multiplexing process without pointer matching is therefore possible.

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Multiplex paths in the SDH

3.7 TUG-2 to VC-3

VC-3

x7

x1 x3

TU-2

VC-2

C-2

6.312 Mbit/s 2.048 Mbit/s 1.544 Mbit/s

TUG-2 x4

TU-12

VC-12

C-12

TU-11

VC-11

C-11

A VC-3 Virtual Container can be filled by multiplexing seven TUG-2 frames byte by byte. In doing this, seven TUG-2s are multiplexed into columns 2 to 85. The VC-3 POH occupies column 1 of the VC-3. TU-11 TU-12 TU-2

1 2 3 4 2 3 4

1 2 3 4

1 2 3

1 2 3

1 2 3

1 2 3

TUG-2

(1)

(2)

(3)

(7)

VC-3 POH

1 2 3 4 5 6 7 1 234 . . .

1 2 3 4 5 6 7

1 2 3 4 5 6 7

1 2 3 4 5 6 7

1 2 3

VC-3

4 5 6 7 81 83 85

Fig. 3-12 Multiplexing seven TUG-2s into one VC-3

3-12

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4 Mapping procedures
For all defined PDH bit rates there are mapping procedures which permit the plesiochonous bit rates to be assembled in the corresponding containers. These mapping procedures are always based on a positive justification process, i.e. the transmission capacity of the container is larger than the maximum amount of information received. In order to compensate the difference between the information received and transmitted, useful information or stuffing information must be inserted at defined points. In the following sections, the mapping procedures available for signals with bit rates normally used in Europe are described.

4.1 Asynchronous mapping of 140 Mbit/s signals into VC-4

A VC-4 is composed of 261 columns, each consisting of 9 rows. The first column is occupied by the VC-4 POH. Each row is split up into 20 blocks of 13 bytes each. With nine rows, this results in a total number of 20 x 9 = 180 blocks (see marks in figure below). The overhead bytes are not taken into account here.

Block 1

Block 2

Block 20

VC-4 POH

1 J1 B3 C2 G1 F2 H4 F3 K3 N1

10

11

12

13

14

... 256 257 258 259 260 261

Block 180 Fig. 4-1 Splitting up VC-4 into 13-byte blocks The first byte of each block is a special byte, the following 12 bytes contain (12 x 8) = 96 information bits. The special bytes are referred to as W, X, Y and Z and have the following order: W is a normal information byte. Y is a stuffing byte, i.e. its contents are not defined. The bits of the X byte are assigned as follows: C R R R R R O O The O bits can be used as overhead bits for the PDH. Five R bits are filled

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Mapping procedures

with undefined stuffing information. The C bit is a stuffing check bit which includes the information as to whether this row contains traffic or justification information in the stuffing position. If the C bit is 0, the stuffing bits are real traffic bits. If it is 1, the stuffing information consists of justification bits only. Since the X byte is transmitted 5 times per row, five stuffing check bits are available. On the Rx side, a majority decision prevents transmission errors from leading to a false interpretation of the stuffing bit contents. The Z byte is occupied as follows: I I I I I I S R It contains six information bits (I), one fixed stuff bit (R) as well as the justification bit (S) that can be used for real or stuffing information. The following figure shows the first row of VC-20 divided up into 20 blocks.
1 12 bytes

J1 W

96 I

96 I

96 I

96 I

96 I

POH byte

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

96 I

Fig. 4-2 Asynchronous mapping of 140 Mbit/s signals into VC-4

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An evaluation of this assignment leads to the following result: Bytes 240 x Inf 1xW 13 x Y 5xX 1xZ x9 260 2340 Information bits 1.920 8 6 1.934 17.406 139,248 104 25 1 130 1.170 9,360 360 5 1 5 45 72 1 9 720 10 90 10 Fixed stuffing bits Stuffing check bits Possible justifi- Overhead bits cation bits

Bit rate [kbit/s]

VC-4 sum bit rate = 149,760 kbit/s VC-4 sum bit rate = 149,760 kbit/s Nominal bi trate fs 139,264 kbit/s

Bit rate w/o stuffing positions 139,248 kbit/s = fs - 1 x 10-4 Bit with stuffing positions 139,320 kbit/s = fs + 4 x 10-4

The nominal bit rate is achieved on transmission of 2 x information and 7 x justification bits in the nine possible stuffing positions.

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4.2 Asynchronous mapping of 34 Mbit/s signals into VC-3

The VC-3 is composed of 85 columns of 9 rows each. The first row is occupied by the VC-3 POH. For the mapping process, all other rows are combined so that always three of them form one partial frame.

VC-3 POH

1 J1 B3 C2 G1 F2 H4 F3 K3 N1

... ... ... ... ... ... ... ... ... ...

80

81

82

83

84

85

Partial frame 1 Partial frame 2 Partial frame 3

Fig. 4-3 VC-3 divided up into three partial frames The assignment of these partial frames is depicted in the following diagram. Columns 39 and 82 contain the C bytes which include the stuffing check bits C1 and C2. The A and B bytes (columns 83, 84) contain the stuffing positions S1 and S2. All partial frames are occupied in the same way. In contrast to the VC-4 mapping procedure, two stuffing positions, i.e. S1 and S2, with the associated five stuffing check bits C1 and C2 are transmitted here. Additional overhead bytes are not provided.

... ... ... ...

17

18

... ... ... ...

39 C C C

... ... ... ...

58

59

60

61

... ... ... ...

81

82 C C

83

84

85

R: Fixed stuffing bits C1, C2: Stuffing check bit S1, S2: Possible stuffing bits I: Information bit R R R R R R R R I I I I I I I I

Byte C Bytes A, B

R R R R R R C1 C2 R R R R R R R S1 S2 I I I I I I I

Fig. 4-4 Asynchronous mapping of 34 Mbit/s signals into VC-3

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Mapping procedures

The evaluation of the information transmitted in each partial frame leads to the following result: Information bits 1.431 4.293 x3 Bit rate [kbit/s] 34,344 13,752 240 48 0 Fixed stuffing bits 573 1.719 Stuffing check bits 10 30 Possible justifi- Overhead bits cation bits 2 6 0 0

VC-3 sum bit rate = 48,384kbit/s VC-3 sum bit rate = 48,384 kbit/s Nominal bit rate fs Bit rate w/o stuffing positions Bit rate with stuffing positions 34.368 kbit/s 34.344 kbit/s = fs - 7 x 10-4 34.392 kbit/s = fs + 7 x 10-4

The nominal bit rate is achieved on transmission of 1 x information and 1 x justification bit in the two possible stuffing positions.

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Mapping procedures

4.3 Asynchronous mapping of 2 Mbit/s signals into VC-12

The VC-12 consists of 140 bytes per 500 s multiframe (4 x 125 s frames). They are used as shown in the following diagram. V5 R 32 bytes R J2 C1 C2 O O O O R R 32 bytes R 140 N2 bytes C1 C2 O O O O R R 32 bytes R K4 C1 C2 R R R R R S1 S2 I I I I I I I 31 bytes R 500 s Fig. 4-5 Asynchronous mapping of 2 Mbit/s signals into VC-12 The VC-12 has two stuffing positions (S1, S2). They are controlled by the two stuffing bits (C1, C2). On evaluation of the stuffing check bits C1 and C2, a majority decision is performed on the receive side. The evaluation of the information transmitted in each multiframe leads to the following result: Information bits 1.016 7 Bits/500 s Bit rate [kbit/s] 1.023 2.046 Fixed stuffing bits 64 9 73 146 Stuffing check bits 6 6 12 Possible justifi- Overhead bits cation bits 2 2 4 8 8 16 R: Fixed stuffing bits (info) O: Overhead bits C1, C2: Stuffing check bit S1, S2: Possible stuffing bits I: Information bit

VC-12 sum bit rate = 2.224 kbit/s Nominal bit rate fs Bit rate w/o stuffing positions Bit rate with stuffing positions 2.048 kbit/s 2.046 kbit/s = fs - 1 x 10-3 2.050 kbit/s = fs + 1 x 10-3

The nominal bit rate is achieved on transmission of 1 x information and 1 x justification bit in the two possible stuffing positions.

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4.4 Asynchronous mapping of 1.5 Mbit/s signals into VC-11

The VC-11 consists of 104 bytes per 500 s multiframe. They are used as shown in the following diagram. V5 R R R R R R I R 24 bytes J2 C1 C2 O O O O I R 140 bytes 24 bytes N2 C1 C2 O O O O R R 24 bytes K4 C1 C2 R R R S1 S2 R 24 bytes 500 s Fig. 4-6 Asynchronous mapping of 1.5 Mbit/s signals into VC-11 The two stuffing positions S1 and S2 are controlled by three stuffing check bits C1 and C2 each. A majority decision performed on the receive side with regard to the three check bits determines as to whether the associated stuffing position S is interpreted as information bit or as justification bit. The evaluation of the information transmitted leads to the following result: Information bits 768 3 Bits/500 s Bit rate [kbit/s] 771 1.542 Fixed stuffing bits 24 13 37 74 Stuffing check- Possible justifi- Overhead bits bits cation bits 6 6 12 2 2 4 8 8 16 R: Fixed stuffing bits O: Overhead bits C1, C2: Stuffing check bit S1, S2: Possible stuffing bits I: Information bit

VC-12 sum bit rate = .,648 kbit/s Nominal bit rate fs Bit rate w/o stuffing positions Bit rate with stuffing positions 1.544 kbit/s 1.542 kbit/s = fs - 1.3 x 10-3 1.546 kbit/s = fs + 1.3 x 10-3

The nominal bit rate is achieved on transmission of 1 x information and 1 x justification bit in the two possible stuffing positions.

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Mapping procedures

4.5 Mapping 1.5 Mbit/s signals into VC-12

In order to be able to process 1.5 Mbit/s signals in SDH environments just like 2 Mbit/s signals, it is possible to transport both VC-11 and VC-12 Virtual Containers as TU-12. For this purpose, a VC-11 is generated first of all. This VC-11 consists of 104 bytes which are located in 36 rows (4 basic frames) with 3 columns each. In each row, the 9th byte of the third column is missing. On providing a column with fixed stuffing bytes (with even parity!) between column 2 and 3, the 140 bytes of a VC-12 are obtained. In the entire network, the VC-12 generated this way cannot be distinguished from a normal VC-12. Only in the receiver, the initial VC-11 is recovered by extracting the stuffing information.

V5

V5

J2

J2

N2

N2

K4

K4

500 s Fixed stuffing information with even parity Fig. 4-7 Conversion of a VC-11 into a VC-12 (1.5 Mbit/s in VC-12)

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Overhead

5 Overhead
For monitoring and controlling the SDH network, additional information is transmitted together with the traffic data (payload). This additional information, called Overhead, is divided up into two main groups, i.e. the Section Overhead and the Path Overhead.

5.1 Section Overhead

Together with the payload, the Section Overhead (SOH) forms an STM-N frame. This frame contains all information required for frame synchronization, maintenance, performance monitoring and various other functions. The SOH is composed of a block consisting of nine rows of N x 9 columns each (N = 1, 4, 16). For operation, a distinction is made between the Regenerator Section Overhead (RSOH) composed of rows 1 to 3 and the Multiplex Section Overhead (MSOH) consisting of rows 5 to 9. Row 4 of the SOH contains the AU pointer bytes. While the RSOH is terminated (i.e. disassembled, evaluated and newly generated) at each regenerator point, the MSOH passes the regenerator without being modified and is only terminated at the multiplexers (where the payload is assembled or disassembled). On generation of STM-4 and STM-16, the number of SOH columns increases by 4 and 16, respectively.
Frame alignment signal STM identifier

261 bytes AU-4

Service channel

RSOH

BER monitoring

A1 A1 A1 A2 A2 A2 J0/ C1 B1 E1 F1 Voice D1 D2 D3 H1 Pointer H2

STM-1
Autom. prot. switch. sign.

H3 H3 H3 K2 D6 D9 D12 Z2 M1 E2

B2 B2 B2 K1 D4 D5 D8 D11

Connection check BER monitoring Ident. of VC contents Path status User channel

J1 B3 C2 G1 F2 H4 F3

MSOH

D7 D10

C-4 Payload

S1 Z1 Z1 Z2

Synchronization status

Future purposes

Voice Section REI

Multiframe indic. User channel

VC-4

Autom. prot. switching K3

D..

Data transmission Spare channels

Managem. purposes

K4

Fig. 5-1 Overhead bytes

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Overhead

5.1.1 Regenerator Section Overhead (RSOH)

A1, A2 Frame alignment signal STM-N identifier Path Trace BIP-8 monitoring Assignment: A1 = 1111 0110 A2 = 0010 1000

C1

The C1 byte can be used to check an STM-N connection between two multiplexers (old meaning, new see J0). 16 byte telegram for connection check

J0

B1

Only defined in STM-1 no. 1. This byte is used for error monitoring on the Regenerator Section. The BIP-8 value is calculated over all bits of the current STM-N frame to receive an even parity and is inserted in the next frame. Only defined in STM-1 no. 1. This byte can be used to generate a 64 kbit/s voice channel for service channel purposes. This channel is accessible at all regenerators and the associated multiplexers. Only defined in STM-1 no. 1. This byte is reserved for network operator purposes. This channel is accessible at all regenerators and the associated multiplexers. Only defined in STM-1 no. 1. These three bytes form a common DCCR data channel with a capacity of 192 kbit/s for the regenerator section. This channel is used to exchange management information.

E1

Regenerator service channel User channel

F1

D1, D2, D3

Data Communication Channel (DCC)

5.1.2 Multiplex Section Overhead (MSOH)

B2 BIP-N x 24 monitoring N x 3 bytes for bit error monitoring of the multiplex section. The BIP-Nx24 value is calculated to obtain an even parity over all bits of the current STM-N frame with the exception of the RSOH rows (row 1 to 3) and is inserted in the next frame. Only defined in STM-1 no. 1. These two bytes can be used to control automatic protection switching processes. The assignment of these bytes is defined for different protection switching configurations (1+1, 1:n). Bits 6, 7 and 8 of the K2 byte are reserved for future applications. The following assignments have been defined: 111 for Multiplex Section AIS MS-AIS, MS-RDI.

K1, K2

Autom. protection switching

110 for Multiplex Section Remote Defect Indication D4...D12 Data Communication Channel (DCC)

Only defined in STM-1 no. 1. These eight bytes form a common data channel ( DCCM) with 576 kbit/s for the Multiplex Section.

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Overhead

S1

Synchronization status (Synchronization Status Message (SSM)) Spare bytes Section REI Multiplexer service channel

Only defined in STM-1 no. 1. The SSM informs the operator on the performance of the clocks used in the unit.

Z1,Z2 M1 E2

These N x 4 bytes are reserved for future applications. Remote Error Indication for the Multiplex Section. Only defined in STM-1 no. 1. This byte can be used to form a 64 kbit/s voice channel for service channel purposes. This channel is accessible only at multiplexers.

5.2 Path Overhead

Together with Container C, the Path Overhead (POH) forms the Virtual Container VC. The POH capacity depends on the path level. While the higherorder POH is composed of 9 bytes (1 row), only four bytes are available for the lower-order POH.

5.2.1 Higher-order POH (VC-3/VC-4)

The higher-order POH is located in the first column (9 bytes) of VC-3 or VC-4. It is formed on generation of the VC-3 (VC-4) and remains unchanged (exception: N1 byte) until the Virtual Container is disassembled in order to be able to monitor the complete path. J1 B3 C2 G1 F2 H4 F3 K3 N1 C-4 Payload

Connection check BER monitoring Identif. of VC contents Path status User channel Multiframe indicator User channel Autom. prot. switch. Managem. purposes Fig. 5-2 Higher-order POH

The following bytes have been defined:

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Overhead

J1 Path Trace

This is the first byte in the VC-3/VC-4. Its position is indicated by the pointer and represents thus the reference point of the VC-3/VC-4 structure. This byte can be used to transmit either a repetitive telegram with a length of 64 bytes in any format or a 16-byte telegram in the so-called E.164 format. The Path Trace permits the link to be checked over the complete path. E.164 format: The first byte marks the beginning of the frame. It includes the result of a CRC-7 calculation performed for the previous frame. The following 15 bytes are used to transmit the ASCII signs. If the 16-byte format shall be transmitted in a 64-byte format, it must be repeated four times.

B3 BIP-8 monitoring

This byte is used for error monitoring over the complete path. The BIP-8 value is calculated over all bits of the current VC3/VC-4 to obtain an even parity and is inserted into the next VC3/VC-4. This byte is used as identifier for the VC contents. The following table gives an overview of the defined codings of the C2 byte.
MSB 1 2 3 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB 1 2 3 4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 Hex. code 00 01 02 03 04 Explication Unequipped Equipped - non specific TUG structure Locked TU Asynchronous mapping of 34,368 kbit/s or 44,736 kbit/s into Container-3 Asynchronous mapping of 139,264 kbit/s into Container-4 ATM mapping MAN (DQDB) mapping FDDI mapping

C2 Contents identifier

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1

12 13 14 15

MAN: Metropolitan Area Network DQDB: Dual Queue Dual Bus FDDI: Fibre Distributed Data Interface

Table 5-1 C2 byte mapping code G1 Path status Via this byte, the transmission performance data are reported by the path end to the VC source. Thus, it is possible to monitor the complete path from any point or from any of the two ends.

REI

RDI

(not used)

Fig. 5-3 VC3/VC4 path status (G1) The following information is transmitted:

5-4

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Overhead

Bit 1..4

VC Path Remote Error Indication (REI).

The binary value transmitted corresponds to the number of parity violations detected on comparison of B3 with BIP-8. Numbers higher than 8 are evaluated as 0 errors, since the BIP-8 error monitoring method does not permit errors > 8 to be detected. Bit 5 VC Path Remote Defect Indication (RDI)

This signal is returned whenever the VC-3/VC-4 assembler does not receive a valid signal. The following conditions have been defined: a) Path AIS b) Loss of signal c) Wrong path trace (J1 byte) In each of these cases, bit 5 is set to logic 1, otherwise it is 0. Bit 6...8 F2 User channel not yet defined.

This 64 kbit/s channel is available for communication between the path start and path end for user purposes. On generation of a payload multiframe, this byte is used in the lower-order VC for multiframe synchronization. It is therefore payload-specific.
500 s TU multiframe

H4 Multiframe indicator

P1

P1

SL2

SL1

C3

C2

C1

Fig. 5-4 TU multiframe indicator H4 F3 User channel This 64 kbit/s channel is available for communication between the path start and path end for user purposes. Bits 1 to 4 are provided for controlling automatic protection switching processes at the higher-order level. Bits 5 to 8 are reserved for future applications. This byte is provided for management purposes, e.g. Tandem Connection Maintenance.

K3 Autom. protection switching N1 Network operator byte

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Overhead

5.2.2 Lower-order POH (VC-1x/VC-2)

The lower-order POH is composed of the V5, J2, N2 and K4 bytes. These are transmitted in four consecutive frames forming a 500 s multiframe. V5 Frame 1 J2 Frame 2 POH N2 Frame 3 K4 Frame 4 500 s Fig. 5-5 Lower Order POH V5 V5 is the first byte in VC-1x/VC-2. The TU-1x/TU-2 pointer points at this byte and represents thus the reference point of the lower-order VC. V5 is used for transmitting the following information:

BIP-2

REI

RFI

Signal Label

RDI

Fig. 5-6 Bit assignment of the V5 byte Definitions: Bit 1, 2 BIP-2 monitoring These two bits are used for error monitoring over the complete lower-order path. The result is calculated to obtain an even parity. The calculation is performed for the complete VC-1/VC-2 including the POH bytes, however, without bytes V1 to V4 of the TU-1/TU-2 pointer. If information is transmitted in byte V3 in negative justification processes, this byte is included in the calculation. By setting this bit to logic 1, the VC source is informed that one or several parity violations were detected in the BIP-2 calculation. If there are no errors, this bit is logic 0. On detection of a fault or failure, this bit is set to logic 1. RFI is sent back to the VC source.

Bit 3

Remote Error Indication (REI) Remote Failure Indication (RFI)

Bit 4

5-6

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Overhead

Bit 5, 6, 7 Contents identifier

These three bits correspond with the C2 byte of the higher-order POH. The use of the three special mapping indicators 010, 011 and 100 is optional. However, these values must not be used for other purposes. b5 0 0 0 0 1 1 1 1 b6 0 0 1 1 0 0 1 1 b7 0 1 0 1 0 1 0 1 equipped - unused Meaning Unequipped Equipped - non specific Asynchronous Bit-synchronous Byte-synchronous

Fig. 5-7 V5[5-7] Mapping Code Bit 8 VC-Path Remote Defect Indication (RDI) Path Trace This bit is sent back to the VC source. In normal operation, it is logic 0. On reception of TU1x/TU2 Path AIS or detection of LOS or wrong path trace (J2), it is set to logic 1.

J2

The function of this byte is identical with that of byte J1 of the higher-order POH. This byte can be used to transmit a 16 byte telegram in the E.164 format. Using the Path Trace, it is possible to check the link over the complete path. Bits 1 to 4 are provided for controlling automatic protection switching processes at the lower-order level. Bits 5 to 8 are reserved for future applications.

K4

Autom. protecting switching Network operator byte

N2

This byte is provided for management purposes, e.g. Tandem Connection Maintenance.

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Overhead

5-8

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Pointers

6 Pointers
A worldwide synchronous network represents an ideal condition that can in practise not always be achieved. In synchronous networks, failures can lead to islands without clock connection. In this case, a free-running oscillator must supply these islands with the required clock information. The introduction of pointers in the SDH created the possibity to maintain the synchronous character of the transported information in a not clock-synchronous environment. The information sent to such an island can thus be processed without any loss of information and can be passed on although the clock bit rates are not identical. The payload has no fixed phase relation to the frame. In order to be able to access the payload, a pointer is transmitted in the overhead block. It permits the dynamic adaptation of the phase of the Virtual Container to the frame. In this connection, dynamic means: 1. The phase of the Virtual Container can differ from that of the frame. 2. At different frequencies, the phase position can continuously vary without causing any loss of information.

6.1 Pointer value modification

There are two possibilities of modifying the pointer value: a) Setting a new pointer value b) Frequency matching.

6.1.1 Setting a new pointer value

In case of modifications of the payload, it may be necessary to set a new pointer value. In order to indicate this change, the so-called New Data Flag (NDF) is set. Then the new pointer value is transmitted. On the receive side, the NDF is evaluated. The new pointer value received indicates the new position of the Virtual Container. The NDF with the new pointer value is transmitted only once, i.e. in the first frame. There must not be any further pointer operations within the next three frames.

6.1.2 Frequency matching

If the frequency of the STM-N frame is not exactly identical with the one of the VC frame, the pointer value is increased or decreased by 1 at regular intervals, while frame matching is simultaneously performed by a positive or negative justification process. After each pointer correction, at least three frames must be transmitted without pointer modification. The frequency matching process for AU pointers is explained in the following section. The process for the TU pointers is identical.

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Pointers

Positive justification If the frame frequency of the VC is lower than that of the STM-N frame, stuffing bytes must be inserted and the pointer value must be increased by 1 at regular intervals.
STM-1 frame 1 9 270

Pointer (P) H1 H2 H3

Beginning of VC-4 Frame n

125 s

Pointer (P)

H1 H2 H3

Frame n+1

250 s Pos. stuffing byte(s) Pointer (P) H1 H2 H3 Frame n+2

375 s

New pointer (P+1)

H1 H2 H3

Frame n+3

500 s

Fig. 6-1 Pointer modification (positive justification) The stuffing bytes are inserted directly behind the last H3 byte. For an AU-3 one stuffing byte, for an AU-4 three stuffing bytes are inserted. The new pointer (P+1) is then transmitted starting at the next frame. The next VC starts at the position indicated by the new pointer.

6-2

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Negative justification If the frame frequency of the VC is higher than that of the STM-N frame, additional information of the VC must be transmitted in the H3 bytes and the pointer value must be decreased by 1 at regular intervals.
STM-1 frame 1 9 270

Pointer

H1 H2 H3

Beginning of VC-4 Frame n

125 s

Pointer (P)

H1 H2 H3

Frame n+1

250 s Pointer (P) H1 H2 Neg. justification bytes (data) Frame n+2

375 s

New pointer (P-1)

H1 H2 H3

Frame n+3

500 s

Fig. 6-2 Pointer modification (negative justification) The following three H3 bytes are filled with information. With AU-3, only the H3 byte belonging to the VC to be stuffed is filled with information. The new pointer (P-1) is transmitted starting at the next frame. The next VC starts at the position indicated by the new pointer.

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Pointers

6.2 Pointer types

In the Synchronous Digital Hierarchy (SDH), there are two pointer types: the AU pointer and the TU pointer: AU pointer: AU-3, AU-4 pointer TU pointer: TU-3, TU-2, TU-11, TU-12 pointer

6.2.1 AU-3 pointer

The AU-3 pointer permits a dynamic adaptation of the phase of a VC-3 to the frame of the Administrative Unit AU (and thus to the STM frame). In this connection, dynamic means: 1. The phase of VC-3 can differ from that of the STM frame. 2. At different frequencies, the phase position can continuously vary without causing any loss of information. The AU-3 pointer is located in the 4rth row of the SOH. It is composed of three bytes referred to as H1, H2 and H3. The three bytes with number 0 start to the right of the last pointer byte (H3). The byte nos. 522 to 782 are located in front of the pointer. Consequently, pointer values higher than 521 point to the next STM-1 frame.
1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 H1 H1 H1 H2 H2 H2 H3 H3 H3 H1 H1 H1 H2 H2 H2 H3 H3 H3 2 3 4 5 6 7 8 9 10 11 12 13 14 . . . . ... . . . . 269 270

522 522 522 523 523 523 524 524 524 ... 607 607 607 608 608 608 609 609 609 610 610 610 611 611 611 ... 694 694 694 695 695 695

696 696 696 697 697 697 698 698 698 ... 781 781 781 782 782 782 0 87 0 87 0 87 1 88 1 88 1 88 2 89 2 89 2 89 ... 85 85 85 86 86 86

... 172 172 172 173 173 173

174 174 174 175 175 175 176 176 176 ... 259 259 259 260 260 260 261 261 261 262 262 262 263 263 263 ... 346 346 346 347 347 347 348 348 348 349 349 349 350 350 350 ... 433 433 433 434 434 434 435 435 435 436 436 436 437 437 437 ... 520 520 520 521 521 521 522 522 522 523 523 523 524 524 524 ... 607 607 607 608 608 608 609 609 609 610 610 610 611 611 611 ... 694 694 694 695 695 695

696 696 696 697 697 697 698 698 698 ... 781 781 781 782 782 782 0 87 0 87 0 87 1 88 1 88 1 88 2 89 2 89 2 89 ... 85 85 85 86 86 86

... 172 172 172 173 173 173

Fig. 6-3 AU-3 pointer

6-4

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Pointers

The three AU-3 pointers are interleaved byte by byte and arranged as follows:

H1(a) H1(b) H1(c) H2(a) H2(b) H2(c) H3(a) H3(b) H3(c)

Pointer a Pointer b Pointer c

The three pointers are independent of each other and indicate the beginning of the corresponding VC, only the bytes of this VC being counted and those of all others being skipped. H1, H2 H1 and H2 are read as a 16-bit data word. Bits 1 to 4 form the so-called New Data Flag NDF. The NDF indicates as to whether a new pointer value has to be set. Two values have been defined: NDF 0110 = disabled NDF 1001 = enabled Maintain pointer value Set new pointer value

Bits 5 and 6 are referred to as S S. They are set to S S = 10. Bits 7 to 16 represent the pointer value. As a binary value, the pointer value indicates the offset between the VC start and the reference point expressed in bytes. The bits are by turns referred to as I bit and D bitt (Increment and Decrement). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15). On the decoder side, an inversion of the I bits is followed by a majority decision, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the current VC are ignored. In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated and the information contained in H3 is inserted into the payload of the current VC.
N N N N S S I D I D I D I D I D

New Data Flag

Pointer value

H3

H3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC frame frequency higher than STM frame frequency). In all other cases of application, the content of this byte is not defined.

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6.2.2 AU-4 pointer

In the AU-4, only every third byte is provided with a counting no.. The three bytes with number 0 start to the right of the last pointer byte (H3). The byte nos. 522 to 782 are located in front of the pointer in rows 1 to 3. Consequently, pointer values higher than 521 point to the next STM-1 frame.
1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 H1 Y Y H2 1* 1* H3 H3 H3 H1 Y Y H2 1* 1* H3 H3 H3 2 3 4 5 6 7 8 9 10 522 609 696 0 87 174 261 348 435 522 609 696 0 87 11 12 13 523 610 697 1 88 175 262 349 436 523 610 697 1 88 14 . . 524 611 698 2 89 176 263 350 437 524 611 698 2 89 . . ... . . . . 608 695 695 86 173 260 347 434 521 608 695 695 86 173 269 270 -

... 607 ... 694 ... 781 ... 85

... 172 ... 259 ... 346 ... 433 ... 520 ... 607 ... 694 ... 781 ... 85

... 172

Fig. 6-4 AU-4 pointer H1, H2 H1 and H2 are read as a 16-bit data word. It includes the New Data Flag NDF and the pointer value. NDF 0110 = disabled NDF 1001 = enabled Maintain pointer value Set new pointer value

The bits S S are set to 1 0. Bits 7 to 16 represent the pointer value. As a binary value, the pointer value indicates the offset between the VC-4 start (J1 byte) and the reference point in 3-byte increments. The bits are by turns referred to as I bit and D bit (Increment and Decrement). If the pointer value is to be increased by a positive justification process, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15). On the decoder side, an inversion of I bits is followed by a majority decision, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the current VC-4 are ignored. In negative justification processes, the five D bits (bit 8, 10, 12,14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and

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the information contained in H3 is inserted into the payload of the current VC-4.
N N N N S S I D I D I D I D I D

New Data Flag

Pointer value

H3

H3 is the Pointer action byte. In negative justification processes, it is used for transmitting the additional information byte. In all other cases of application, the content of this byte is not defined. The H1 and H2 bytes not required have been defined as follows: H1 1 0 0 1 S S 1 1 (S bits not defined, in Fig. AU-4 pointer on page 6 referred to as Y) H2 1 1 1 1 1 1 1 1 (in Fig. AU-4 pointer on page 6 referred to as 1*) The bit combination H1 and H2 thus corresponds with the Concatenation Indication CI, i.e. an AU-4 is treated just like three concatenated AU-3s. If the pointer value is 0, it indicates that the VC starts with the byte directly following the last H3 byte.

AU-4 concatenation

In case of large payload amounts, several AU-4 Administrative Units are concatenated. The first AU-4 contains a normal pointer. The associated following AU-4s include the CI instead of the pointer value. This CI indicates that these AU-4s are to be treated in the same way as the previous ones.
1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1

Concatenation Indication CI

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6.3 TU-3 pointer

The TU-3 pointer permits a dynamic adaptation of the phase of a VC-3 to the TUG-3 frame. In this connection, dynamic means: 1. The phase of VC-3 can differ from that of the TUG-3 frame. 2. At different frequencies, the phase position can continuously vary without causing any loss of information.
86 columns
H1 H2 H3 S T U F F I N G J1 B3 C2 G1 F2 H4 F3 K3 N1

TUG-3

TU-3 pointer

85 columns

VC-3
C-3

VC-3 POH Fig. 6-5 Multiplexing a VC-3 into a TUG-3 The TU-3 pointer is located in the first column of the TUG-3 frame. It is composed of three bytes referred to as H1, H2 and H3. H1, H2 H1 and H2 are read as a 16-bit data word. Bits 1 to 4 represent the New Data Flag NDF. The NDF indicates as to whether a new pointer value must be set or not. The following two values have been defined: NDF 0110 = disabled NDF 1001 = enabled Maintain pointer value Set new pointer value

Bits 5 and 6 are referred to as S S. They are set to S S = 10. Bits 7 to 16 represent the pointer value. As binary value, the pointer value indicates the offset between the VC-3 start (J1 byte) and the reference point expressed in bytes. The bits are by turns referred to as I bit and D bitt (Increment and Decrement). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15). On the decoder side, an inversion of the I bits is followed by a majority decision, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the current VC-3 are ignored.

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In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in H3 is inserted into the payload of the current VC-3.
N N N N S S I D I D I D I D I D

New Data Flag

Pointer value

H3

H3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC-3 frame frequency higher than STM frame frequency). In all other cases of application, the content of this byte is not defined. If the pointer value is 0, it indicates that the VC-3 starts with the byte directly following the H3 byte. The values for the TU-3 pointer range from 0 to 764. Pointer values between 595 and 764 point to the next TUG-3 frame!
1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 2 3 4 5 6 ... 82 83 84 85 86

H1 595 596 597 598 599 H2 680 681 682 683 684 H3 S T U F F I N G 0 85 1 86 2 87 3 88 4 89

... 675 676 677 678 679 ... 760 761 762 763 764 ... 80 81 82 83 84

... 165 166 167 168 169 ... 250 251 252 253 254 335 336 337 338 339 ... 420 421 422 423 424 ... 505 506 507 508 509 ... 590 591 592 593 594 ... 675 676 677 678 679 ... 760 761 762 763 764 ... ... 80 81 82 86 83 84 -

170 171 172 173 174 255 256 257 258 259 340 341 342 343 344 425 426 427 428 429 510 511 512 513 514

H1 595 596 597 598 599 H2 680 681 682 683 684 H3 0 0 85 1 86 2 87 3 1 88 4 89

... 165 166 167 168 169

Fig. 6-6 TU-3 pointer

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6.4 TU-2 pointer

The TU-3 pointer permits a dynamic adaptation of the phase of a VC-2 to the TUG-2 frame. In this connection, dynamic means: 1. The phase of VC-2 can differ from that of the TUG-2 frame. 2. At different frequencies, the phase position can continuously vary without causing any loss of information. The bytes required for the pointer operations are referred to as V1, V2, and V3. These bytes are located in the first byte position of four consecutive TU-2s. The definition of the byte available in the current TU-2 is performed by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.

V1 321 322

... 426 427 V2

... 105 106 V3 107 108

... 212 213 V4 214 215

... 319 320

V1, V2= Pointer byte V3= Pointer action byte V4= Spare byte Fig. 6-7 TU-2 pointer V1, V2 V1 and V2 can be read as a 16-bit data word. Bits 1 to 4 represent the New Data Flag NDF. The following two values have been defined: NDF 0110 = disabled NDF 1001 = enabled Bits 5 and 6 are referred to as S S and indicate the type of the TU. TU-2: S S = 0 0 Bits 7 to 16 represent a 10-bit word, the so-called pointer value. As a binary value, the pointer value indicates the offset between the VC-2 start and the reference point in bytes. The bits are by turns referred to as I and D bit (Increment and Decrement). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15). On the decoder side, an inversion of the I bits is followed by a majority decision, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the current VC-2 are ignored. In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in V3 is inserted into the payload of the current

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VC-2.
N N N N S S I D I D I D I D I D

New Data Flag

Pointer value

V3

V3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC-2 frame frequency higher than TU-2 frame frequency). In all other cases of application, the content of this byte is not defined. If the pointer value is 0, it indicates that the VC-2 starts with the byte directly following the V2 byte. The values for the TU-2 pointer range from 0 to 427. Pointer values between 321 and 427 point to the next TUG-2 frame!

V4 TU-2 concatenation

V4 not yet defined.

In order to be able to transport bit rates not defined by ITU-T within the Synchronous Digital Hierarchy (SDH), several TU-2 Tributary Units can be concatenated to TU-2-mc. Thus, it is possible to transport information in multiples of VC-2 within a VC-2-mc. Three different concatenation types are possible: a. Concatenation of consecutive TU-2s in one higher-order VC-3 (contiguous concatenation). b. Sequential concatenation of several TU-2s in one higher-order VC-3 (sequential concatenation). c. Virtual concatenation of TU-2s in one higher-order VC-4 (virtual concatenation). In case of a contiguous concatenation, the first TU-2 receives a valid pointer. All other TU-2s contained in the TU-2-mc receive the Concatenation Indicator (CI) instead of the pointer. The CI indicates that all pointer operations of the first TU-2 are to be performed in the same way in all other TU-2s. The VC-2-mc includes a VC-2 POH which is located in the first VC-2 of the VC-2-mc.
1 0 0 1 S S 1 1 1 1 1 1 1 1 1 1

Concatenation Indication CI

The sequential concatenation permits the simultaneous transport of both TU-2-mc and TU-3 in one VC-4. In case of a virtual concatenation, all VC-2s of a VC-2-mc receive the same pointer at the beginning of the path. The control circuit ensures that all VC-2s belonging together are accommodated in the same VC-4.

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6.5 TU-11 pointer

The TU-11 pointer permits a dynamic adaptation of the phase of a VC-11 to the TUG-2 frame. In this connection, dynamic means: 1. The phase of VC-11 can differ from that of the TUG-2 frame. 2. At different frequencies, the phase position can continuously vary without causing any loss of information. The bytes required for the pointer operations are referred to as V1, V2 and V3. These bytes are located in the first byte position of four consecutive TU-11s. The definition of the byte available in the current TU-11 is performed by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.

V1

78

79

... 102 103 V2

...

24

25

V3

26

27

...

50

51

V4

52

53

...

76

77

V1, V2= Pointer byte V3= Pointer action byte V4= Spare byte Fig. 6-8 TU-11 pointer V1, V2 V1 and V2 can be read as a 16-bit data word. Bits 1 to 4 represent the New Data Flag NDF. The following two values have been defined: NDF 0110 = disabled NDF 1001 = enabled Bits 5 and 6 are referred to as S S and indicate the Type of the TU. TU-11: S S = 1 1 Bits 7 to 16 represent a 10-bit word, the so-called pointer value. As a binary value, the pointer value indicates the offset between the VC-11 start and the reference point expressed in bytes. The bits are by turns referred to as I and D bit (Increment and Decrement). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15). On the decoder side, an inversion of the I bits is followed by a majority decision, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the current VC-11 are ignored. In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in V3 is inserted into the payload of the current VC-11.
N N N N S S I D I D I D I D I D

New Data Flag

Pointer value

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V3

V3 is the Pointer action byte. It is used to transmit the additional information byte in negative justification processes (VC-11 frame frequency higher than TU-11 frame frequency). In all other cases of application, the content of this byte is not defined. If the pointer value is 0, it indicates that the VC-11 starts with the byte directly following the V2 byte. The values for the TU-11 pointer range from 0 to 103. Pointer values between 78 and 103 point to the next TUG-2 frame!

V4

V4 not yet defined.

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6.6 TU-12 pointer

The TU-12 pointer permits a dynamic adaptation of the phase of a VC-12 to the TUG-2 frame. In this connection, dynamic means: 1. The phase of VC-12 can differ from that of the TUG-2 frame. 2. At different frequencies, the phase position can continuously vary without causing any loss of information. The bytes required for the pointer operations are referred to as V1, V2 and V3. These bytes are located in the first byte position of four consecutive TU-12s. The definition of the byte available in the current TU-12 is performed by means of the H4 multiframe indicator of the VC-3 POH or VC-4 POH.

V1 105 106

... 138 139 V2

...

33

34

V3

35

36

...

68

69

V4

70

71

... 103 104

V1, V2= Pointer byte V3= Pointer action byte V4= Spare byte Fig. 6-9 TU-12 pointer V1, V2 V1 and V2 can be read as a 16-bit data word. Bits 1 to 4 represent the New Data Flag NDF. The following two values have been defined: NDF 0110 = disabled NDF 1001 = enabled Bits 5 and 6 are referred to as S S and indicate the type of the TU. TU-12: S S = 1 0 Bits 7 to 16 represent a 10-bit word, the so-called pointer value. As a binary value, the pointer value indicates the offset between the VC-12 start and the reference point expressed in bytes. The bits are by turns referred to as I and D bit (Increment and Decrement). If the pointer value is to be increased by positive justification, this is indicated by the inversion of all five I bits (bits 7, 9, 11, 13 and 15). On the decoder side, an inversion of the I bits is followed by a majority decision, i.e. if at least three I bits have been inverted, the current pointer value is increased by 1 and the justification bytes contained in the payload of the current VC-12 are ignored. In the negative justification process, the five D bits (bits 8, 10, 12, 14 and 16) are inverted. On the decoder side, the D bits are evaluated in the same way and the information contained in V3 is inserted into the payload of the current VC-12.

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New Data Flag

Pointer value

V3

V3 is the Pointer action byte. It is used to transmit an additional information byte in negative justification processes (VC-12 frame frequency higher than TU-12 frame frequency). In all other cases of application, the content of this byte is not defined. If the pointer value is 0, it indicates that the VC-12 starts with the byte directly following the V2 byte. The values for the TU-12 pointer range from 0 to 139. Pointer values between 105 and 139 point to the next TUG-2 frame!

V4

V4 not yet defined.

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6-16

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7 Reference model
International standards set up for the Synchronous Digital Hierarchy (SDH) and the associated equipment units ensure that networks can be established using equipment from different manufacturers. This is achieved thanks to the introduction of application-independent reference models. The general reference model (acc. G.783) specifies both the physical characteristics (bit rates, optical/electrical level, impedances) and definitions regarding the contents of each byte and even bit. These specifications cover the following aspects: Frame structure Identification Scrambling Coding/decoding Mapping procedures Service channel utilization Monitoring and control signals.

The essential parts of signal processing are defined as functions. Regarding external interfaces, previous recommendations were maintained. The reference model is composed of 16 different basic functions. They have an internal function and logic reference points via which the individual blocks communicate with each other. These reference points are no internal test or measuring points and in many cases physically not even obvious. The external interfaces (inputs and outputs), however, are physically defined.
Transport terminal function STM-M T T RST S T MST S T MSP S T MSA S Higher-order path T LPC S T HPA S T HPT S T HPC S T MSA S Transport terminal function T MSP S T MST S DCC M Higher-order path S G.703 T PPI S T LPA T S S S SETS SETPI External synchronization SEMF MCF F interface T RST S DCC R Q interface T STM-N SPI S

SPI S

Lower-order path G.703 T PPI S T LPA S T LPT S

Fig. 7-1 Reference model for the design of SDH units The SDH definitions used in the reference model such as section, lower-

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order path, higher-order path, overhead etc. are generally applicable to both transmission directions. All functional blocks have a clock reference point T and a management reference point S. The reference point T communicates with the functional block referred to as SETS, the reference point S with functional block SEMF.

7.1 Lower-order path functions

PPI PDH Physical Interface This function represents the interface for the information transfer to other transmission systems as defined in ITU-T Rec. G.703 for the PDH. Essential tasks include the electrical isolation, overvoltage protection, exchange cable equalization, line coding/decoding as well as clock recovery and monitoring of the incoming signal. This function defines how plesiochronous signals are mapped into C-n containers (n=11, 12, 2, 3) and the justification procedures necessary for this purpose. This function generates and/or evaluates the VC-Path Overhead. The Path Overhead is carried in the container from its assembly up to its disassembly. This function permits a flexible arrangement of VC-11s, VC-12s, VC-2s and VC-3s within a VC-4 or of VC-11s, VC-12s, VC-2s within a VC-3 via a so-called connection matrix. This function is required only if the time allocation of the VC to the STM signal shall not be defined by the card slot.

LPA Lower-Order Path Adaption

LPT Lower-Order Path Termination LPC Lower-Order Path Connection

7.2 Higher-order path functions

HPA Higher-Order Path Adaption Here the VC-m contents are assembled (m = 3, 4); in addition, the TU pointers are generated or modified. These pointers set up the phase relation between VC-n (n = 11, 12, 2, 3) and VC-m (m = 3, 4). Here the VC-m POH (m = 3, 4) is generated and/or evaluated in accordance with the LPT function. This function permits the flexible arrangement of the VC-m Virtual Containers (m = 3, 4) within an STM-N frame.

HPT Higher-Order Path Termination HPC Higher-Order Path Connection

7.3 Transport terminal functions

MSA Multiplex Section Adaption Here the AU pointers are generated and/or modified. The AU Groups (AUG) thus generated are interleaved byte by byte to obtain the STM-N frame (without Section Overhead SOH). This function includes all aspects necessary to ensure that switchover to protection paths is possible in case of failures on the line side. MSP communication with the opposite station takes place via the K bytes of the Section Overhead. This function generates the MSOH (row 5 to 9 of the SOH) and/or evaluates it on the receive side.

MSP Multiplex Section Protection

MST Multiplex Section Termination

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RST Regenerator Section Termination

This function generates the RSOH (row 1 to 3 of the SOH) and/or evaluates it on the receive side. In addition, the STM-N signal is scrambled in the transmit direction. Frame alignment and descrambling take place in the receive direction. The logic signal is normally converted into an optical STM-N signal appropriate for the transmission medium available. Both signal conversion and clock recovery are performed in the receive direction. This function provides all clocks required by the network element (NE). All functions mentioned above receive the necessary clock signals via the reference points T from the SETS. This is the interface between an external synchronization source and SETS.

SPI SDH Physical Interface

SETSSynchronous Equipment Timing Source SETPI Synchronous Equipment Timing Physical Interface SEMF Synchronous Equipment Management Function

Here the monitoring data (performance data and hardware-specific messages) are converted into object-oriented messages which can be transmitted via the DCC or the Q or F interface to a management system or an Operator Terminal. In the opposite direction, messages from the management system are converted into hardware-specific control signals. The connections to the individual functional blocks are set up via logic reference points S. This function covers all tasks to be fulfilled in conjunction with the transport of TMN messages to or from the management system via DCC channels or via the Q or F interface.

MCF

Message Communication Function

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8 Applications
8.1 Synchronous line equipment
In the SDH, no distinction is made between multiplexers and line terminating units. The synchronous line equipment includes both synchronous multiplexers with integrated optical transmitters and receivers and the associated regenerators.

140/155 Mbit/s 4

622 Mbit/s

140/155 Mbit/s 4

F2in

F1out

Fin1

Fout2 SLR4

Fin1

Fout2 SLR4

F1in

F2out

SLX1/4 4 F2out F1in

SLX1/4 F1out F2in 4

Fout4

Fin3

Fout4

Fin3

140/155 Mbit/s 16

2488 Mbit/s

140/155 Mbit/s 16

F2in

F1out

Fin1

Fout2

Fin1

Fout2

F1in

F2out

SLX1/16 16 F2out F1in

SLR16 Fout4 Fin3

SLR16 Fout4 Fin3

SLX1/16 F1out F2in 16

Fig. 8-1 SLA4 and SLA16 synchronous line equipment (Example)

8.1.1 Synchronous line multiplexer

The SLX1/4 synchronous line multiplexer is described here as an example. This multiplexer combines four STM-1 signals to one STM-4 signal. On the multiplex side, the Section Overheads (SOH) of the individual STM-1 signals are terminated (disassembled and evaluated). The payload signals are multiplexed column by column and a new STM-4 SOH is generated. On the demultiplex side, the STM-4 SOH is terminated, while the payload signals are distributed column by column onto the four STM-1 channels. In addition, a new STM-1 SOH is generated for each STM-1 signal. Besides pointer matching, the different SOH bytes are evaluated: B1 and B2 signal monitoring bytes D1 to D3 management information bytes F1 user channel byte E1 and E2 service channel bytes

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Alternatively, 140 Mbit/s signals can be applied to the synchronous line multiplexer instead of STM-1 signals. In the transmit direction, the asynchronous 140 Mbit/s signals are converted into an STM-1 signal. In the receive direction, the initial 140 Mbit/s signals are extracted from the STM-1 signal. As opposed to the PDH, the conversion of STM-4 signals to STM-16 signals is not performed by a 4 x STM-4 multiplexing process, but 16 STM-1 signals are directly combined to form the STM-16 signal.

622 Mbit/s 4

155.520 Mbit/s

STM-4 4 139.264 Mbit/s

AUG

AU-4

VC-4

C-4

2448 Mbit/s 16

155.520 Mbit/s

STM-16 16 139.264 Mbit/s

AUG

AU-4

VC-4

C-4

Fig. 8-2 Multiplex scheme in compliance with ITU G.707

8.1.2 Synchronous line regenerator

In the PDH, the line regenerator fulfills the function of regenerating the line signal with respect to time and amplitude. In addition, it is responsible for the coding rule check (transmission performance feature) and must support fault location processes. A service channel can be additionally provided for maintenance purposes. The signal contents are transparently switched through without taking into account eventually available signal structures or frames. In the SDH, the tasks of a regenerator are by far more extensive. The signals are descrambled and the STM-N frame structure is analyzed. Since a regenerator section is ending, part of the SOH (RSOH, rows 1 to 3) is terminated, i.e. the transmission quality is determined by means of the B1 byte, the management information contained in bytes D1 to D2 is evaluated,

8-2

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the user channel is made available via byte F1 and the service channel via byte E1. Then the SOH is completed again by forming a new RSOH. Here the new Regenerator Section begins. Fault location is generally performed by a management system using the information supplied by all equipment units available in the network. A special system-internal fault-locating device is therefore not necessary here. The difference between SLA-4 and SLA-16 consists only in the different regenerator bit rates.

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8.2 Multiplexers
Regarding their functions, multiplexers can be divided up into the following three basic types: Terminal Multiplexers Add/Drop Multiplexers Cross-connect Multiplexers

8.2.1 Terminal Multiplexer

Application of a Terminal Multiplexer in the network topology One of the FlexPlex MS1/4 applications is its use as a Terminal Multiplexer. This multiplexer type is required at the end of linear links in SDH networks. It combines the tributary signals supplied by lower-order network elements to an aggregate signal which is passed on to the network. Fig. 8-3 shows a section of a network topology with FlexPlex MS1/4 used as Terminal Multiplexer.
e.g.: 2 Mbit/s 34 Mbit/s 140 Mbit/s

MS1/4 TMS

STM-4 STM-1

STM-1

MS1/4 MS1/4: FlexPlex MS1/4 TMS: Terminal Multiplexer (SDH) STM-4 TMS e.g.: 2 Mbit/s 34 Mbit/s 140 Mbit/s

Fig. 8-3 FlexPlex MS1/4 used as Terminal Multiplexer in an SDH network

8-4

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Functioning of a Terminal Multiplexer

The Terminal Multiplexer can split up the signal available at an aggregate interface into the subsignals contained. These are then passed on to the associated tributary interfaces. In the opposite direction, the Terminal Multiplexer combines the signals received at the tributary interfaces to one signal which is routed to the aggregate interface. Fig. 8-4 shows the functioning of a Terminal Multiplexer with regard to the traffic data to be transmitted.

Aggregate signal (e.g. STM-1, STM-4)

n Tributary signals (e.g. 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, (STM-1))

Fig. 8-4 Functioning of a Terminal Multiplexer On splitup of the signal available at the aggregate interface, the multiplexer extracts the associated Overhead information and routes parts of it accessible to the user and appropriate e.g. for operating a service channel system to the corresponding interfaces. In the outgoing direction, the Terminal Multiplexer generates the Overhead data for the signal sent out at the aggregate interface.

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Applications

8.2.2 Add/Drop Multiplexer

Application of an Add/Drop Multiplexer in the network topology One of the FlexPlex MS1/4 applications in SDH networks is its use as an Add/Drop Multiplexer. The Add/Drop Multiplexer is used as network element in linear transmission links or in ring network configurations. It extracts one or several subsignals from the aggregate-side signals (STM-1 or STM-4) and routes them to the tributary interfaces (drop function). From there they are passed on to lower-order network elements of the network hierarchy. In the opposite direction, the Add/Drop Multiplexer inserts tributary signals supplied by lower-order network elements into the aggregate signals in the form of subsignals (add function) from where they are passed on to the network via the aggregate-side interfaces. Fig. 8-5 shows a section of a network topology with a FlexPlex MS1/4 system functioning as an Add/Drop Multiplexer.

STM-4 MS1/4 AMS

STM-4

STM-1

STM-1

e.g.: 2 Mbit/s 34 Mbit/s 140 Mbit/s

MS1/4: FlexPlex MS1/4 AMS: Add/Drop Multiplexer (SDH)

e.g.: 2 Mbit/s 34 Mbit/s 140 Mbit/s

e.g.: 2 Mbit/s 34 Mbit/s 140 Mbit/s

Fig. 8-5 FlexPlex MS1/4 used as an Add/Drop Multiplexer in an SDH network

8-6

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Applications

Functioning of an Add/Drop Multiplexer

The Add/Drop Multiplexer is an expansion of the Terminal Multiplexer. In contrast to the Terminal Multiplexer, it is equipped with two aggregate-side interfaces for signals of the same hierarchical level. It can split up the signals of the two aggregate interfaces (referred to as "West" and "East") into the subsignals contained and can route individual subsignals to the associated tributary interfaces (drop function). In the opposite direction, it inserts the signals received at the tributary interfaces into the aggregate signals instead of the subsignals extracted (add function). Subsignals not affected by the add/drop functions are switched through from one aggregate interface to the other. On through-connection, the subsignals can be switched at TU-12 level. Fig. 8-6 shows the functioning of an Add/Drop Multiplexer with regard to the traffic data to be transmitted.

TU-12
Aggregate signal West (e.g. STM-1, STM-4) Aggregate signal East (e.g. STM-1, STM-4)

n Tributary signals (e.g. 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, (STM-1))

Fig. 8-6 Functioning of an Add/Drop Multiplexer

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Applications

8.2.3 Cross-connect Multiplexer

Application of a Crossconnect Multiplexer in the network topology One of the FlexPlex MS1/4 applications is its use as a Cross-connect Multiplexer. Within SDH networks, the Cross-connect Multiplexer is used at nodes, in which several signals of the same hierarchy level have to be crossconnected. This cross-connect function is possible for both signals available on the aggregate side and signals available on the tributary side of the multiplexer. The Cross-connect Multiplexer is ideally suited for network nodes located on a linear SDH link to which further SDH signals of the same hierarchy are routed (star topology) or for network nodes representing the interface between two SDH rings. Fig. 8-7 shows the example of a network section with such nodes.

STM-1 STM-4

MS1/4 XMS4

MS1/4 XMS1

STM-1

STM-4

STM-1 MS1/4: FlexPlex MS1/4 XMS1: Cross-connect Multiplexer (STM-1) XMS4: Cross-connect Multiplexer (STM-4)

Fig. 8-7 FlexPlex MS1/4 used as Cross-connect Multiplexer in an SDH network

8-8

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Applications

Functioning of the Cross-connect Multiplexer

The Cross-connect Multiplexer is an expansion of the Add/Drop Multiplexer or Terminal Multiplexer. In contrast to these, it is equipped with up to four aggregate interfaces. They can be referred to as "West1/East1" and "West2/East2", if e.g. the multiplexer is used as network node at the interface between two SDH rings. These interfaces do not have to be used in pairs. In case of a star-shape network node, it is possible to occupy e.g. three of them. The aggregate and tributary interfaces are identical with regard to their crossconnecting capabilities. A FlexPlex MS1/4 configured as Cross-connect Multiplexer is also capable of cross-connecting the individual tributary signals. Thus, it offers maximum flexibility when setting up network structures. Fig. 8-8 shows the functioning of a Cross-connect Multiplexer with respect to the traffic data (payload) to be transmitted.

Aggregate signal West 1 (e.g. STM-1, STM-4)

Aggregate signal East 1 (e.g. STM-1, STM-4)

TU-12
Aggregate signal West 2 (e.g. STM-1, STM-4) Aggregate signal East 2 (e.g. STM-1, STM-4)

n Tributary signals (e.g. 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, (STM-1))

Fig. 8-8 Functioning of a Cross-connect Multiplexer

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Applications

8.3 Networks
If a telecommunications network, e.g. the DBP Telekom network, is divided up into three levels, i.e. the local area network, the regional long-distance network and the supraregional long-distance network (see Fig. 8-6), all three levels can be equipped with SDH units. However, in order to be able to optimally exploit all possiblilities offered by the Synchronous Digital Hierarchy, different equipment types have to be provided for the different network topologies. The synchronous line equipment (SLA) available for the transmission capacities of 622 Mbit/s and 2.5 Gbit/s (SLA 4, SLA 16) is appropriate for the longdistance network levels where the networks are in most cases implemented as line networks with point-to-point connections. The local area network level mostly consists of ring networks implemented using add/drop multiplexers (ADM). Cross-connect systems can be used at all network levels.

Long-distance network 1

Network nodes

SLA4, SLA16 Long-distance network 2 ADM

SLA4, SLA16 Network nodes

Local area network FMUX ADM

Fig. 8-9 Synchronous networks

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Applications

8.3.1 Ring networks

In local area networks, the existing requirements cannot be satisfactorily met by conventional star networks. Especially in this area, the danger of cable breaks and interruptions caused by digging works is considerable. For this reason, the links to the individual stations have to be doubled and routed via different paths. On interconnection of the stations as depicted in Fig. 8-7, a ring network is set up.

to the long-distance network

Fig. 8-10 Single ring network The stations have access to all information available in the ring. Thus, each station can set up a connection to any other station. Furthermore, each station included in the ring can enter the long-distance network. A central station is no longer required for these tasks. Connections within the ring are set up by informing the corresponding stations on which part of the STM-N signal (i.e. time slot) is to be used for the connection.

8.3.2 Double rings

The problem of cable breaks can be solved by setting up a second ring. The same information passes through the second ring in the opposite direction. Since in such configurations, each station transmits and receives the same information into/from two directions (hot standby), the stations affected by a cable break must only switch over to the other receive path. This can be effected automatically and very quickly so that the full operability of the ring is maintained. Since the effects of such failures (cable breaks) are eliminated automatically, these rings are also referred to as self-healing rings. Such self-healing ring toplogies can also be implemented at the long-

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Applications

distance network level.

to the long-distance network

Fig. 8-11 Double ring network

to the long-distance network

self-healing

Interruption/ cable break

self-healing

Fig. 8-12 Interrupted double ring

8-12

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Applications

By a double connection of the two rings via two stations, the reliability can be further increased.

Local area netw.

Long-dist. netw.

Fig. 8-13 Double ring connection of two ring networks

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Applications

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Protection switching

9 Protection switching
9.1 Overview
The reliability and maintenance of transmission networks are two important aspects to be taken into account on installation of SDH multiplexers. In this connection, redundancy plays an important role. Redundancy means that additional functions are made available on a standby basis. Redundancy should be provided for both the transmission channels of the network and the multiplexer modules. If a transmission channel is faulty or disturbed, the data traffic is switched over to an appropriate protection channel (protection switching). If the function of a multiplexer fails, the system switches over to the redundant function available (equipment protection).

9.2 Definitions
1. Single-ended operation (unidirectional operation) On failure of only one direction of transmission, only the protection switches of this direction are switched over. 2. Dual-ended operation (bidirectional operation) On failure of only one direction of transmission, the protection switches of both directions are switched over. 3. Extra traffic Extra traffic occupies redundant transmission channels. In the case of a fault, this traffic is interrupted. 4. Normal traffic Normal traffic is routed via the redundant transmission channels.

9.3 Protection switching

With protection switching, additional, i.e. redundant transmission channels are provided on a standby basis for the transmission channels to be protected. In the event of a failure, the traffic is automatically switched over to a redundant transmission channel. Important aspects for protection switching: 1. Monitoring The traffic must be monitored so that faults and failures are immediately detected. 2. Protection switch

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Protection switching

The traffic must be switched over by appropriate protection switches. 3. Protocol In many protection switching procedures, a protocol is exchanged between the multiplexers. 4. Control The protection switches have to be controlled in an appropriate way. Any fault detected must be signalled by an alarm. For maintenance purposes, it must be possible to switch over traffic even if there is no fault or failure. There are different protection switching procedures. All these procedures are highly reliable and appropriate for saving the complete traffic protected in case of a single fault. With multiple faults, this is not always possible. For some protection switching procedures there are several variants which differ from each other with regard to the following characteristics: 1. Extra traffic Redundant transmission channels can be occupied by low-priority traffic. In the event of a fault, this traffic is interrupted. 2. Revertive/non-revertive operation This option permits the operator to decide whether the system shall switch back to the original transmission channel on elimination of the fault. 3. Single-ended/dual-ended operation This option permits the operator to decide whether both directions of transmission shall be switched over in common.

9-2

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Protection switching

The following table gives an overview of the protection switching procedures currently available. Designation MS 1+1 Protection Operation Single-ended/ dual-ended revertive/nonrevertive Single-ended/ dual-ended revertive/nonrevertive Dual-ended revertive/nonrevertive Dual-ended revertive/nonrevertive Single-ended revertive/nonrevertive Dual-ended revertive/nonrevertive Protocol in K1/K2 bytes Extra traffic not possible

MS 1:n Protection

K1/K2 bytes

possible

MS Shared Protection Ring MS Dedicated Protection Ring

K1/K2 bytes

possible

K1/K2 bytes

possible

not necessary

not possible

Path/Subnetwork Protection

K3/K4 bytes

not possible

Table 9-1 Overview of protection switching procedures

9.3.1 MS 1+1 protection

The transmitter doubles the traffic and sends it out on two lines. The receiver selects one of these two lines. Extra traffic is not possible here. In the most simple case, operation is single-ended and non-revertive. Dualended and/or revertive operation is optionally possible.

Multiplex Section

Operating path Protection path Doubling Selector

Fig. 9-1 MSP 1+1 Multiplex Section Protection

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Protection switching

9.3.2 MS 1:n protection

A number of n operating channels (n = 1,...,14) are sharing a so-called Protection Section. The protection switches of the transmitter and receiver must operate in the same way, however, in the opposite order. Extra traffic is possible on the Protection Section. Operation can be revertive or non-revertive and single- or dual-ended.

Zero channel (0)

0 1 Operating channel 1 1 2 Operating channel 2 2 Operating section 2 Operating section 1

15 Extra traffic channel (15)

15

Protection section (0)

Bridge

Selector

Fig. 9-2 MS 1:n Protection Switch

9.3.3 MS shared protection ring

MS shared protection rings can consist of two or four fibres. Connections are set up in both directions of transmission using the same ring segment. The advantage consists in a higher transmission capacity, which is, however, only available if the traffic is not routed to a certain multiplexer in a star-shape configuration. The transmission capacity of the MS shared protection ring is divided up into two halfs at the AU level. One half is occupied by normal traffic, while the other is provided for protection purposes. Optionally, the latter can also be used for extra traffic. Two-fibre rings on the STM-1 basis are not provided.

9-4

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Protection switching

In the event of a fault, the adjacent multiplexers switch over the normal traffic at the AU level to the half provided for protection. Operation is dual-ended and revertive or non-revertive. In four-fibre rings, there are two protection switching levels. At first the system tries to protect each section of the ring by an own MS 1:1 protection. If the fault cannot be eliminated this way, a loop is switched.
Node 1 N E E Node 2 N Node 1 N Node 2 N Node 1 N Node 2 N

E N Node 4 No failure

E N Node 3 N Node 4 N Node 3 N Node 4 N Node 3

Failure on section between node 1 and 2 N E Add/drop function for normal traffic Add/drop function for extra traffic

Failure of node 2

Fig. 9-3 Example of the traffic flow in an MS shared protection ring

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Protection switching

9.3.4 MS dedicated protection ring

MS dedicated protection rings are composed of two fibres. One of them is used for transmitting the normal traffic, the other remains free. Optionally, the free fibre can be used for transmitting extra traffic. Each connection occupies only one ring line, however, over the entire ring. In the event of a fault or failure, the adjacent multiplexers switch over the normal traffic to the ring line provided for protection purposes. Operation is dualended and optionally revertive or non-revertive.
Node 1 N E E Node 2 N Node 1 N Node 2 N Node 1 N Node 2 N

E N Node 4 No failure

E N Node 3 N Node 4 N Node 3 N Node 4 N Node 3

Failure on section between node 1 and 2 N E Add/drop function for normal traffic Add/drop function for extra traffic

Failure of node 2

Fig. 9-4 Example for the traffic flow in an MS dedicated protection ring

9.3.5 Path/subnetwork protection

With path/subnetwork protection, the payload to be protected is doubled and - assembled in a VC - transmitted via two different interfaces and transmission paths to the receiver. The receiver monitors both VCs and selects one of them. The criteria taken into consideration for this selection are Path AIS, LOP and, optionally, degraded signal. A distinction is made between the following variants of path/subnetwork protection: Path protection The payload is available in the form of a container and is doubled. Then each container is separately assembled in a VC. Thus, there are two independent VCs which are transmitted via separate paths. The payload is available in the form of a VC and is doubled. Thus, there is only one VC which is transmitted two times via separate paths. In the relevant literature, sometimes no distinction is made between the two protection types, i.e. both variants are meant by path protection. Only ETSI differentiates between these two types of protection.

Subnetwork protection

9-6

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Protection switching

Operation is normally single-ended and non-revertive. In dual-ended operation, a protocol is necessary. The advantages of path/subnetwork protection are (1) the low technical complexity, (2) the possibility of application in any network topology and (3) the flexibility regarding the decision on which connections are to be protected. The disadvantages are (1) the relatively high expenditure resulting from the high number of protection switches and (2) the missing possiblity of extra traffic, since the normal traffic to be protected is always transmitted redundantly.
Path Protection: C-xy C-xy C-xy Permanent bridge VC-xy #2 Path termination Path termination C-xy Path selector

VC-xy #1 C-xy C-xy

Subnetwork Protection:

VC-xy

C-xy

VC-xy

VC-xy

C-xy

Path termination

Permanent bridge

VC-xy

Path selector

Path termination

Fig. 9-5 Path und subnetwork protection

9.3.6 Protocols
Protocols exchanged between the multiplexers are used to control the protection switching processes. Appropriate channels are required for transmitting these protocols. In the Section Overhead, there are the K1/K2 bytes. They are used for the protocols of the following protection types: MS 1+1 protection, MS 1:n protection, MS shared protection ring, MS dedicated protection ring.

For path protection, a separate protocol is required for each virtual container (VC). For this reason, path protection protocols can be appropriately transmitted in the Path Overhead only (bytes K3, K4).

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9-7

Protection switching

9.4 Network topologies

The following sections describe different network topologies appropriate for protection switching.

Linear chain
In a linear chain, the multiplexers are connected in series via Aggregate Interfaces. The multiplexers at both ends of the chain are Terminal Multiplexers, those in between are Add/Drop Multiplexers. In order to increase reliability, the transmission lines between two neigbouring multiplexers are doubled. The transmission lines are operated as MS 1:1, MS 1+1 protection (or path protection). The chain is thus protected against faults occurring on individual transmission lines or Aggregate Interfaces. However, there is no protection against an interruption (cut) of all connection cables between two multiplexers or a total failure of a multiplexer in such a chain configuration. Ring configuration offers better protection features. With path protection in a chain configuration of multiplexers, the following two variants can be implemented: Variant 1 - The protection switches are located only in the multiplexers dropping the path to be protected (see Fig. 9-6). Variant 2 - Each multiplexer through which the path to be protected is running is equipped with protection switches (see Fig. 9-7). Variant 1 can be implemented in each multiplexer which supports path protection for signals available at the Tributary Interfaces. For variant 2, the multiplexer must also support path protection at the Aggregate Interfaces. The reliability of variant 2 is higher, since it also copes with multiple faults on condition that only one single fault occurs on each section.

9-8

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Protection switching

4 x STM-N

TM #1

ADM #2

ADM #3

TM #4

TR

TR TR ... TM ... Tributaries Terminal multiplexer

TR

TR

ADM ... Add/drop muliplexer

Fig. 9-6 Linear multiplexer chain with redundancy

ADM #1 (path switched through) ADM #2 (path dropped) VC-xy VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

Tributary Interface

Fig. 9-7 Path protection in a multiplexer chain

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VC-xy

Aggregate Interface

Aggregate Interface

9-9

Protection switching

Rings
Add/drop multiplexers can be operated in a ring (see Fig. 9-8). Between each multiplexer pair located in a ring, there are two separate transmission paths. For this reason, rings are especially appropriate for setting up reliable subnetworks. These rings can include two or four fibres.

Interconnected rings
Rings can be connected with each other so that (1) the connecting lines are protected and (2) protection switching can be performed independently for both rings (see Fig. 9-9). The two multiplexers serving one connecting line form a so-called Serving Node. It is possible to combine the two multiplexers and their connecting line to one multiplexer. All ring types available can be interconnected (see Fig. 9-10 and 9-11). Even connections between different ring types are possible. A complete recovery of the traffic signals failed is possible, if not more than one single fault occurs in each ring and with only one single fault in the Serving Nodes.

9-10

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Protection switching

TR

ADM #1

TR

ADM #2

Two-fiber ring

ADM #4

TR

ADM #3

TR TR

ADM ... Add/drop multiplexer TR ... Tributaries

ADM #1

TR

ADM #2

Four-fiber ring

ADM #4

TR

ADM #3

TR

Fig. 9-8 Examples for multiplexer rings with two and four connecting lines

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Protection switching

ADM

ADM Serving nodes

ADM

ADM

ADM

ADM

ADM

ADM

ADM

ADM

Fig. 9-9 Example for protection switching in interconnected rings

9-12

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Protection switching

Path protection ring

VC-xy

ADM #1 VC-xy

ADM #3

VC-xy

VC-xy VC-xy VC-xy

VC-xy

VC-xy

VC-xy

VC-xy VC-xy VC-xy VC-xy ADM #2 ADM #4 VC-xy

VC-xy

Path protection ring

ADM: Add/drop multiplexer

Fig. 9-10 Interconnection of two rings with path protection

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VC-xy

9-13

Protection switching

MS shared protection ring

VC-xy

ADM #1 VC-xy

ADM #3

VC-xy VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

VC-xy

ADM #2

ADM #4

MS shared protection ring

ADM: Add/drop multiplexer MS: Multiplex section

Fig. 9-11 Interconnection of two rings with MS shared protection

9-14

VC-xy

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Protection switching

9.5 Equipment protection

With Equipment Protection, multiplexers are equipped with additional (redundant) functions which are made available on a standby basis for the functions to be protected. The redundant function can assume the task of a disturbed function. This results in an increase in reliability. Aspects to be considered for Equipment Protection: 1. Monitoring The functions have to be monitored so that faults or failures are immediately detected. This also applies to functions which are currently not required. 2. Protection Switch It must be possible to enable or disable the functions via appropriate protection switches. 3. Control The protection switches have to be appropriately controlled. Any failure must be signalled by an alarm. In addition, it must be possible to localize any faulty function. For maintenance purposes it must be possible to disable individual functions even if there is no fault or failure. Most of the Equipment Protection procedures offer several variants. These differ from each other to respect to the following features: Revertive/non-revertive operation

This option permits the operator to decide whether the system shall switch back to the original function on elimination of the fault. The following table gives an overview of Equipment Protection procedures available: Designation Equipment 2+1 protection Equipment 1+1 protection Equipment 1:1 protection Equipment 1:n protection Operation Majority decision Revertive/non-revertive Revertive/non-revertive Revertive/non-revertive

Table 9-2 Overview of equipment protection procedures

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Protection switching

9-16

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Literature

10 Literature
[1] ITU-T Recommendation G.702: Digital Hierarchy Bit Rates (Blue Book) [2] ITU-T Recommendation G.703: Physical/Electrical Characteristics of Hierarchical Digital Interfaces (Blue Book) [5] ITU-T Recommendation G.707: Network Node Interface fo rthe SDH [6] ITU-T Recommendation G.773: Protocol Suites for Q Interfaces for Management of Transmission Systems [7] ITU-T Recommendation G.781: Structure of Recommendations on Multiplexing Equipment for the Synchronous Digital Hierarchy (SDH) [8] ITU-T Recommendation G.782: Types and General Characteristics of Synchronous Digital Hierarchy (SDH) Multiplexing Equipment [9] ITU-T Recommendation G.783: Characteristics of Synchronous Digital Hierarchy (SDH) Multiplexing Equipment Functional Blocks [10] ITU-T Recommendation G.784: Synchronous Digital Hierarchy (SDH) Management

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Literature

10-2

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Index

Index
A
A byte 4-4 A1 byte (RSOH) 5-2 A2 byte (RSOH) 5-2 Administrative Unit (AU) 2-6 Administrative Unit Group (AUG) 2-8 AU 2-6 AU pointer 2-6 AU-3 pointer 6-4 D bit 6-5, 6-8 H1, H2 pointer bytes 6-5 H3 pointer action byte 6-5 I bit 6-5, 6-8 NDF 6-5 AU-4 concatenation 6-7 AU-4 pointer 6-6 Concatenation 6-7 D bit 6-6 H1, H2 pointer bytes 6-6 I bit 6-6 NDF 6-6 AUG 2-8 Autom. protection switching (K4 byte) 5-7 Autom. protection switching bytes K1, K2 5-2 Automatic protection switching at the higher-order path 5-5

CI 2-13 , 6-7 Concatenation 2-13 , 6-11

Continuous concatenation 6-11 Sequential concatenation 6-11 Virtual concatenation 6-11 Concatenation Indication 2-13, 6-7
Concatenation of containers 1-6 Container C Container sizes 2-4 Container chain 1-6 Containers 1-3 Contents identifier (higher-order POH) 5-4 Contents identifier (lower-order POH) 5-7 Conveyor belt 1-3 Cross-connect Multiplexer XMS 8-8

D
D bit (Decrement) 6-5, 6-8 D1...D3 byte (RSOH) 5-2 D4...D12 byte (MSOH) 5-2 Data Communication Channel 5-2 DCC 5-2 DCCM 5-2 DCCR 5-2 Descrambling 2-17 Double ring connection 8-13 Double rings 8-11 Dual-ended operation 9-1

E
E.164 format 5-4 E1 byte (RSOH) 5-2 E2 byte (MSOH) 5-3 Equipment protection 9-15 Error monitoring byte B3 5-4 Error monitoring byte V5 (Bit 1, 2) 5-6 Error monitoring using BIP-X 2-17 Extra traffic 9-1, 9-2

B
B byte 4-4 B1 byte 5-2 B2 byte (MSOH) 5-2 B3 byte (higher-order POH) 5-4 BIP 2-17 BIP values 2-17 BIP-2 monitoring (lower-order POH) 5-6 BIP-8 monitoring 5-2 BIP-8 monitoring (higher-order POH) 5-4 BIP-N x 24 monitoring 5-2 Bit errors 2-17 Bit Interleaved Parity 2-17 Bit rates of the STM-1 frame 2-2 Block structure 2-4

F
F1 byte (RSOH) 5-2 F2 byte (higher-order POH) 5-5 Floating mode 2-15 Frame alignment signal 5-2

G C
C bit 4-2 C1 bit 4-4, 4-6, 4-7 C1 byte (RSOH) 5-2 C2 bit 4-4, 4-6, 4-7 C2 byte (higher-order POH) 5-4 G1 byte (higher-order POH) 5-4

H
H1, H2 byte 6-5, 6-6, 6-8 H3 byte 6-5, 6-7, 6-9 H4 byte 2-15 , 5-5

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I-1

Index

Hierarchy level 1-7 Higher-order path 3-1 HPA 7-2 HPC 7-2 HPT 7-2 Higher-order path functions (reference model) 7-2 Higher-order POH 5-3 B3 byte (BIP-8 monitoring) 5-4 C2 byte (contents identifier) 5-4 F2 byte (user channel) 5-5 F3 bytes (User Channel) 5-5 G1 byte (path status) 5-4 H4 byte (multiframe indicator) 5-5 J1 byte (Path Trace) 5-4

5-7

M
M1 byte (MSOH) 5-3 Mapping 2-4 Mapping procedures 4-1 4-8

Asynchronous mapping of 1.5 Mbit/s signals into VC-11 4-7 Asynchronous mapping of 140 Mbit/s into VC-4 4-1 Asynchronous mapping of 2 Mbit/s signals into VC-12 4-6 Asynchronous mapping of 34 Mbit/s signals into VC-3 4-4 Mapping of 1.5 Mbit/s signals into VC12
4-8 MS 1

I
I bit 4-2

J
J0 byte 5-2 J1 byte (higher-order POH) 5-4 J2 byte 5-7 Justification information 1-2, 4-2

K
K1, K2 byte (MSOH) 5-2 K3 byte 5-5 K4 byte (lower-order POH) 5-7

L
Label 1-3 Local area network 8-10, 8-11 Long-distance network 8-10, 8-11 Loss of signal 5-5 Lower-order path 3-1 LPA 7-2 LPC 7-2 LPT 7-2 PPI 7-2 Lower-order path functions (reference model) 7-2 Lower-order POH 5-6 J2 byte 5-7

n protection 9-4 MS 1+1 protection 9-3 MS dedicated protection ring 9-6 MS shared protection ring 9-4 MSOH 5-2 Multiframe 4-6, 4-7 Multiframe generation 2-15 Multiframe indicator (H4) 2-15, 5-5 Multiplex paths 3-1 AU-4 to AUG 3-2 AUG to STM-N 3-3 C11, C12 and C2 to TUG-2 3-8 C-3 to STM-N 3-4, 3-6 C-4 to STM-N 3-2 TUG-2 to TUG-3 3-11 TUG-2 to VC-3 3-12 Multiplex scheme 3-1 Multiplex scheme in compliance with ITU-T G.709 3-1 Multiplex Section Overhead 5-2 Multiplexer Cross-connect Multiplexer XMS 8-8 Multiplexer service channel 5-3 N
N1 byte 5-5 N2 byte (lower-order POH) 5-7 NDF 6-1, 6-5 Negative justification 6-3 Network operator byte 5-5 Networks, synchronous 8-10 New Data Flag 6-1, 6-5 Normal traffic 9-1

V5 byte Bit 1, 2 (BIP-2 monitoring) 5-6 Bit 3 (REI) 5-6 Bit 4 (RFI) 5-6 Bit 8 (RDI) 5-7 V5 byte Bit 5, 6, 7 (contents identifier)

I-2

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Index

O
O bit 4-1, 4-6, 4-7 Offset 1-9 Overhead 5-1 5-7

Path Overhead (POH) 5-1 Section Overhead (SOH) 5-1 Overhead bit 4-1, 4-6, 4-7
Overhead capacity 2-2

P
Parittsverletzung 2-17 Parity violations 2-17 Path AIS (P AIS) 5-5 Path monitoring 5-4 Path Overhead 2-2, 2-5, 5-3 5-7 Path status 5-4 Path Trace 5-2 Path Trace J1 (higher-order POH) 5-4 Path Trace J2 (lower-order POH) 5-7 Path/subnetwork protection 9-6 Payload 1-3, 2-2 POH 2-5 Pointer action byte 6-5 Pointer modification 6-1 Frequency matching 6-1 H3 byte 6-2, 6-3 Negative justification 6-3 Positive justification 6-2 Setting a new pointer 6-1 Pointer types 6-4 AU pointer 6-4 TU pointer 6-4 Pointers 6-1 6-15

RDI (lower-order POH) 5-7 Reference model 7-1 Reference points 7-1 Regenerator Section Overhead 5-2 Regenerator service channel 5-2 REI 5-3, 5-5 REI (lower-order POH) 5-6 Remote Defect Indication (RDI) 5-5 Remote Defect Indication (VC path) 5-7 Remote Error Indication (REI) 5-3, 5-5 Remote Error Indication (REI) (lower-order POH) 5-6 Remote Failure Indication (RFI) 5-6 Revertive/non-revertive operation 9-2 RFI 5-6 Ring network 8-11 Rings, self-healing 8-11 RSOH 5-2

S
S bit 4-2 S1 bit 4-4, 4-6, 4-7 S1 byte (MSOH) 5-3 S2 bit 4-4, 4-6, 4-7 Scrambler 2-17 Scrambling 2-17 SDH multiplex elements 2-4 2-8 Section Overhead 1-7, 5-1 Section REI 5-3 Setting a new pointer value 6-1 Setting the pointer by frequency matching 6-1 Single ring 8-11 Single-ended operation 9-1 Single-ended/dual-ended operation 9-2 SOH 5-1

AU pointer AU-3 pointer 6-4 AU-4 pointer 6-6 TU pointer TU-11 pointer 6-12 TU-12 pointer 6-14 TU-2 pointer 6-10 TU-3 pointer 6-8
Point-to-point connections 8-10 Positive justification procedure 6-2 Protection switching 9-1 Protection switching in interconnected rings 9-10 Protection switching in linear chains 9-8 Protocols for protection switching 9-7

MSOH B2 byte (BIP-N x 24 monitoring) 5-2 D4 to D12 (DCCM) 5-2 E2 byte (multiplex service channel)
5-3

K1, K2 byte (automatic protection switching) 5-2 M1byte (section FEBE) 5-3 S1 byte (timing marker) 5-3 Z1, Z2 byte (spare bytes) 5-3 RSOH A1, A2 byte (frame alignment signal)
5-2

R
R bit 4-2 RDI 5-5

B1 byte (BIP-8 monitoring) 5-2 D1 to D3 (DCCR) 5-2 E1 byte (regenerator service channel)

62.1011.105.11-A001

I-3

Index

5-2

F1 byte (user channel) 5-2 J0 byte (STM-N identifier) 5-2

Spare bytes 5-3 SSM 5-3 STM-1 Frame 2-1 Structure 2-1 STM-N 2-1 STM-N identifier 5-2 Stuffing byte 4-1 Stuffing check bit 4-4, 4-6, 4-7 Stuffing check bit (C bit) 4-2 Stuffing position 4-2, 4-6, 4-7 Synchronization status 5-3 Synchronization Status Message (SSM) 5-3 Synchronous line equipment 8-1 Synchronous line multiplexer 8-1 Synchronous line regenerator 8-2 Synchronous multiplexing 2-14 Synchronous Tranport Module STM-1 2-1

NDF 6-14 V3 pointer action byte 6-15

TU-14 pointer

V4 byte 6-15 TU-2 concatenation 6-11 TU-2 pointer 6-10 D bit 6-10 I bit 6-10 NDF 6-10 V1, V2 pointer bytes 6-10 V3 byte 6-11 V3 pointer action byte 6-11
TU-3 pointer 6-8 D bit 6-9

H1, H2 pointer bytes 6-8 H3 pointer action byte 6-9 NDF 6-8
TUG 2-8

U
User channel 5-2

T
Terminal Multiplexer (TMS) 8-4 Transport frame 1-7 Transport terminal functions MCF 7-3 MSA 7-2 MSP 7-2 MST 7-2 RST 7-3 SEMF 7-3 SETPI 7-3 SETS 7-3 SPI 7-3 Transport terminal functions (reference model) 7-2 Tributary Unit (TU) 2-6 Tributary Unit Group (TUG) 2-8 TU pointer 2-6 TU size 6-10 , 6-12, 6-14 TU-11 pointer 6-12 D bit 6-12 I bit 6-12 NDF 6-12 V1, V2 pointer bytes 6-12, 6-14 V3 pointer action byte 6-13 V4 byte 6-13 TU-12 pointer 6-14 D bit 6-14 I bit 6-14

V
V1, V2 byte 6-10, 6-12, 6-14 V3 byte 6-11, 6-13, 6-15 V4 byte 6-11, 6-13, 6-15 V5 5-6 VC-12 4-6 VC-3 4-4 VC-3 POH 4-4 VC-3/VC-4 assembler 5-5 VC-4 4-1 VC-4 POH 4-1 Virtual Container (VC) Formats 2-5 Voice channel 5-3

W
W byte 4-1

X
X byte 4-1

Y
Y byte 4-1

Z
Z byte 4-2 Z1, Z2 byte (MSOH) 5-3

I-4

62.1013.105.11-A001