Amdahl's Law is a law governing the speedup of using parallel processors on a problem, versus using only one serial

processor.

Speedup: The speed of a program is the time it takes the program to excecute. This could be measured in any increment of time. Speedup is defined as the time it takes a program to execute in serial (with one processor) divided by the time it takes to execute in parallel (with many processors). The formula for speedup is: T(1) S = ------------T(j) Where T(j) is the time it takes to execute the program when using j processors. Efficiency is the speedup, divided by the number of processors used. This is an important factor to consider. Now, if we assume the strictly serial part of the program is performed in B*T(1) time, then the strictly parallel part is performed in ((1-B)*T(1)) / N time. With some substitution and number manipulation, we get the formula for speedup as: N S = ----------------------(B*N)+(1-B) A protocol for managing the caches of a multiprocessor system so that no data is lost or overwritten before the data is transferred from a cache to the target memory. When two or more computer processors work together on a single program, known as multiprocessing, each processor may have its own memory cache that is separate from the larger RAM that the individual processors will access.( A memory cache, sometimes called a cache store or RAM cache, is a portion of memory made of high-speed static RAM (SRAM) instead of the slower and cheaper dynamic RAM (DRAM) used for main memory. Memory caching is effective because most programs access the same data or instructions over and over. By keeping as much of this information as possible in SRAM, the computer avoids accessing the slower DRAM). When multiple processors with separate caches share a common memory, it is necessary to keep the caches in a state of coherence by ensuring that any shared operand that is changed in any cache is changed throughout the entire system. This is done in either of two ways: through a directory-based or a snooping system. In a directory-based system, the data being shared is placed in a common directory that maintains the coherence between caches. The directory acts as a filter through which the processor must ask permission to load an entry from the primary memory to its cache. When an entry is changed the directory either updates or invalidates the other caches with that entry.

In a snooping system, all caches on the bus monitor (or snoop) the bus to determine if they have a copy of the block of data that is requested on the bus. Every cache has a copy of the sharing status of every block of physical memory it has. Cache misses and memory traffic due to shared data blocks limit the performance of parallel computing in multiprocessor computers or systems. Cache coherence aims to solve the problems associated with sharing data.

Define Hit and Miss? The performance of cache memory is frequently measured in terms of a quantity called hit ratio. When the CPU refers to memory and finds the word in cache, it is said to produce a hit. If the word is not found in cache, then it is in main memory and it counts as a miss. Write the formula for the average access time experienced by the processor in a system with two levels of caches. Ans: The formula for the average access time experienced by the processor in a system with two levels of caches is t ave= h1C1+(1-h1)h2C2+(1-h1)(1-h2)M
h1= hit rate in the L1 cache. h2= hit rate in the L2 cache. C1=time to access information in the L1 cache. C2= time to access information in the L1 cache. M= time to access information in the main memory.

What are the enhancements used in the memory management?

Ans: 1) Write Buffer 2) Pre fetching 3) Look- up Cache. What is cache memory? Ans: It is a fast memory that is inserted between the larger slower main memory and the processor. It holds the currently active segments of a program and their data. Difference between spatial locality of reference and temporal locality of reference? Locality of reference The locality of reference, also known as the locality principle [1], is the phenomenon, that the collection of the data locations referenced in a short period of time in a running computer, often consists of

relatively well predictable clusters. Important special cases of locality are temporal, spatial, equidistant and branch locality.

Temporal locality: if at one point in time a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future. There is a temporal proximity between the adjacent references to the same memory location. In this case it is common to make efforts to store a copy of the referenced data in special memory storage, which can be accessed faster. Temporal locality is a very special case of the spatial locality, namely when the prospective location is identical to the present location. Spatial locality: if a particular memory location is referenced at a particular time, then it is likely that nearby memory locations will be referenced in the near future. There is a spatial proximity between the memory locations, referenced at almost the same time. In this case it is common to make efforts to guess, how big neighbourhood around the current reference is worthwhile to prepare for faster access.

HARD real time system system is said to be real-time if the total correctness of an operation depends not only upon its logical correctness, but also upon the time in which it is performed. The classical conception is that in a hard real-time or immediate real-time system, the completion of an operation after its deadline is considered useless - ultimately, this may cause a critical failure of the complete system. A soft real-time system on the other hand will tolerate such lateness, and may respond with decreased service quality Hard real-time systems are used when it is imperative that an event is reacted to within a strict deadline. VLIW Architecture VLIWs use multiple, independent functional units. Rather than attempting to issue multiple, independent instructions to the units. VLIW (very long instruction word) instruction sets. VLIW architectures are characterized by instructions that each specify several independent operations. The key to higher performance in microprocessors for a broad range of applications is the ability to exploit fine-grain, instruction-level parallelism. Some methods for exploiting fine-grain parallelism include: + pipelining + multiple processors + superscalar implementation + specifying multiple independent operations per instruction Pipelining is now universally implemented in high-performance processors. Little more can be gained by improving the implementation of a single pipeline. Instruction lavel parallelism

Pipelining can overlap the execution of instructions when they are independent of one another. This potential overlap among instructions is called instruction-level parallelism (ILP) since the instructions can be evaluated in parallel. Multi tasking and multi programming

Consistency versus Coherence