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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 2, FEBRUARY 2012

Asymmetrical Full-bridge Converter With High-Voltage Gain

Hyun-Lark Do
AbstractThis paper proposes an asymmetrical full-bridge converter with high-voltage gain. The control of the proposed converter is implemented with the asymmetrical pulsewidth modulation technique. The proposed converter achieves zero-voltage switching (ZVS) of all power switches. Zero-current switching (ZCS) of output diodes is also achieved. The proposed converter can provide high-voltage gain and the voltages across the semiconductor devices are effectively clamped. Steady-state analysis of the proposed converter is presented. A laboratory prototype of the proposed converter is developed, and its experimental results are presented for validation. Index TermsDCDC converter, high-voltage gain, soft switching, zero-voltage switching (ZVS), zero-current switching (ZCS).

I. INTRODUCTION IGH-EFFICIENCY dcdc converters with high-voltage gain have been researched due to increasing demands. They are required as an interface system between the lowvoltage sources and the load which requires higher voltage in many applications such as electric vehicles, uninterruptible power supplies, fuel cells, and photovoltaic systems [1][7]. A conventional boost converter is often used in step-up applications due to its simple structure and low cost. However, it is not suitable for high step-up applications. This is because the conventional boost converter requires an extreme duty cycle to obtain high-voltage gain and its voltage gain is limited due to its parasitic components [8]. Also, the severe reverse-recovery problem of the output diodes degrades system performance such as efciency and electromagnetic noises. In order to remedy these problems, high step-up dcdc converters using coupled inductors have been suggested in [9] and [10]. However, they have parasitic oscillations across the switches and diodes due to a resonance between the leakage inductance of a coupled inductor and parasitic capacitances of the semiconductor devices. Also, the galvanic isolation between the input and output stages of the power converters needs to be provided to meet safety standards

Manuscript received March 24, 2011; revised May 25, 2011; accepted July 4, 2011. Date of current version January 9, 2012. Recommended for publication by Associate Editor M. Vitelli. The author is with the Department of Electronic and Information Engineering, Seoul National University of Science and Technology, Seoul 139-743, Korea (e-mail: hldo@ snut.ac.kr). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2011.2161777

The current-fed converters are often used in high step-up applications due to their inherent low input current ripple characteristic and high-voltage gain [11], [12]. However, in the currentfed converters, the voltage stresses of the switches are serious. In order to clamp the voltages across the switches and provide zero-voltage switching (ZVS) features, active snubbers are often employed. The snubbers require additional switches and cause additional conduction losses. As a result, the system efciency decreases. On the other hand, the voltage-fed converters such as phase-shift full-bridge (PSFB) converters, which are widely used, show low-voltage stress of the switching devices. PSFB converters feature xed switching frequency and ZVS of power switches. However, they have some drawbacks including large conduction loss due to circulating current, duty cycle loss, and the voltage spikes across output rectiers. The large voltage spikes of the output rectiers are serious problems especially in high-voltage applications. To remedy these problems, many topologies have been proposed in [13][18]. In some of them, auxiliary snubber circuits are employed to suppress the voltage spikes at the secondary side. However, the complexity and the overall cost are increased while the system efciency decreases due to the additional circuits. The asymmetrical pulsewidth modulation (APWM) technique was introduced in [19]. The APWM technique has various advantages such as zero switching loss, no conduction loss penalty, and xed switching frequency. In [19], full-bridge and half-bridge converters with APWM control were suggested. Their main drawback is that the maximum duty cycle is limited to 0.5 and a large turn ratio of a transformer is required to obtain high-voltage gain. Modied APWM control scheme for the asymmetrical full-bridge converter was proposed in [20]. And new asymmetrical full-bridge converter was proposed in [21]. Without considering the transformer turn ratio, the converters in [20] and [21] are buck-type converters. Therefore, they are not suitable for high step-up applications. In order to overcome these problems, an asymmetrical fullbridge converter with high-voltage gain is proposed and shown in Fig. 1. The APWM technique is applied to the proposed converter to eliminate switching losses and maintain low conduction loss. The limitation of the maximum duty cycle disappears in the proposed topology. The proposed converter features high-voltage gain, xed switching frequency, soft-switching operations of all power switches and output diodes, and clamped voltages across power switches and output diodes. The reverserecovery problem of the output diodes is signicantly alleviated due to an additional inductor at the secondary side. Therefore, the proposed converter shows high efciency and it is suitable for high-voltage applications.

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Fig. 1.

Circuit diagram of the proposed converter.

Fig. 2.

Equivalent circuit of the proposed converter.

II. PRINCIPLE OF OPERATION A. Circuit Description Fig. 1 shows the circuit diagram of the proposed converter with high-voltage gain. The proposed converter has four power switches S1 through S4 . There is also the clamping capacitor Cc between top side switches S1 and S3 of two switch bridges. The voltages across the switches S1 and S2 in the rst bridge are conned to the input voltage Vin . The clamping capacitor Cc can clamp the voltages across the switches S3 and S4 in the second bridge. The output stage of the proposed converter has a voltage doubler structure that consists of the secondary winding N2 of the transformer T, the serial inductor Ls , the output capacitors Co 1 , and Co 2 , and the output diodes Do 1 and Do 2 . According to the voltage doubler structure, the voltage gain increases and the voltage stresses of the output diodes are conned to the output voltage Vo without any auxiliary circuits. The equivalent circuit of the proposed converter is shown in Fig. 2. The diodes D1 through D4 are the intrinsic body diodes of all switches. The capacitors C1 through C4 represent their parasitic output capacitances. The transformer T is modeled as the magnetizing inductance Lm and the ideal transformer that has a turn ratio of 1:n (n = N2 /N1 ). Its leakage inductance is included in the

serial inductor Ls . To simplify the analysis, it is assumed that the clamping capacitor Cc has a large value and the voltage across Cc is constant as Vc under a steady state. Similarly, the output capacitor voltages are assumed to be constant as Vo 1 and Vo 2 , respectively. The theoretical waveforms of the proposed converter are shown in Fig. 3. The switch S1 (S4 ) and the switch S2 (S3 ) are operated asymmetrically and the duty cycle D is based on the switch S1 (S4 ). A small delay between driving signals for S1 (S4 ) and S2 (S3 ) is a deadtime for the switches. It prevents cross conduction and allows ZVS. B. Modal Analysis The operation of the proposed converter during a switching period Ts is divided into four modes as shown in Fig. 4. Before t0 , the switches S2 and S3 , and the output diode Do 1 are conducting. At t0 , the magnetizing current im and the secondary current is arrive at their minimum values Im 2 and ID o 1 , respectively. Mode 1 [t0 , t1 ]: At t0 , the switches S2 and S3 are turned OFF. Then, the energy stored in the magnetic components starts to charge/discharge the parasitic capacitances C1 through C4 . Therefore, the voltages vS 2 and vS 3 start to rise from zero. Similarly, the voltage vS 4 starts to fall from Vin + Vc and the

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Fig. 3.

Theoretical waveforms.

voltage vS 1 starts to fall from Vin . Since all the parasitic output capacitances C1 through C4 are very small, this transition time interval is very short and it is ignored in Fig. 3. When the voltages vS 1 and vS 4 arrive at zero, their body diodes D1 and D4 are turned ON. Then, the gate signals are applied to the switches S1 and S4 . Since the currents have already own through D1 and D4 and the voltages vS 1 and vS 4 are clamped as zero before the switches S1 and S4 are turned ON, zero-voltage turn-ON of S1 and S4 is achieved. With the turn-ON of S1 and S4 , the primary voltage vp across Lm is Vin . Then, the magnetizing current im increases linearly from its minimum value Im 2 as follows: Vin (t t0 ) . Lm

Since the voltage vL s across Ls is nVin +Vo 1 , the secondary current is increases from its minimum value ID o 1 as follows: is (t) = ID o1 + by iS 1 (t) = iS 4 (t) = Im 2 nID o1 + Vin n (nVin + Vo1 ) + Lm Ls (t t0 ) . (3) nVin + Vo1 (t t0 ) . Ls (2)

In this mode, the switch currents iS 1 and iS 4 can be written

im (t) = Im 2 +

(1)

Mode 2 [t1 , t2 ]: At t1 , the currents is and iD o 1 arrive at zero and the diode Do 1 is turned OFF. Then, the output diode Do 2 is turned ON and its current increases linearly. Since the current changing rate of Do 1 is controlled by the serial inductor Ls , its

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charged from zero, whereas the parasitic capacitors C2 and C3 start to be discharged from Vin and Vin + Vc , respectively. With the same assumption as mode 1, this transition time interval is very short and it is ignored in Fig. 3. After the parasitic capacitors are fully charged and discharged, the voltages vS 2 and vS 3 become zero and the body diodes D2 and D3 are turned ON. Then, the gate signals are applied to the switches S2 and S3 . Since the currents have already own through D2 and D3 and the voltages vS 2 and vS 3 are clamped as zero, zero-voltage turn-ON of S2 and S3 is achieved. With the turn-ON of S2 and S3 , the voltage vp across Lm is (Vin +Vc ). Then, the current im decreases linearly from its maximum value Im 1 as follows: im (t) = Im 1 Vin + Vc (t t2 ) . Lm (6)

Since the voltage vL s across Ls is (n(Vin + Vc ) +Vo 2 ), the current is decreases from its maximum value ID o 2 as follows: is (t) = ID o2 n (Vin + Vc ) + Vo2 (t t2 ) . Ls (7)

In this mode, the switch currents iS 2 and iS 3 can be written by iS 2 (t) = iS 3 (t) = Im 1 nID o2 + (Vin + Vc ) n (n (Vin + Vc ) + Vo2 ) + Lm Ls (t t2 ) . (8) Mode 4 [t3 , t4 ]: Similar to mode 2, the currents is and iD o 2 arrive at zero and the diode Do 2 is turned OFF at t3 . Then, the output diode Do 1 is turned ON and its current increases linearly. Since the current changing rate of Do 2 is controlled by Ls , its reverse-recovery problem is signicantly alleviated. Since the voltage vL s is (n(Vin + Vc )Vo 1 ), the current is is given by is (t) =
Fig. 4. Operating Modes.

n (Vin + Vc ) Vo1 (t t3 ) . Ls

(9)

Since the voltage vp is not changed in this mode, (6) is still effective. In this mode, the switch currents iS 2 and iS 3 can be written by iS 2 (t) = iS 3 (t) = im (t3 ) + (4) (Vin + Vc ) n (n (Vin + Vc ) Vo1 ) + Lm Ls (t t3 ) . (10) At the end of this mode, the currents im and is arrive at Im 2 and ID o 1 , respectively. III. DESIGN PARAMETERS A. Clamping Capacitor Voltage Vc Referring to the voltage waveform vp in Fig. 3, the volt-second balance law gives Vin DTs (Vin + Vc )(1 D)Ts = 0. (11)

reverse-recovery problem is signicantly alleviated. Since the voltage vL s is (nVin Vo 2 ) in this mode, the current is are given by nVin Vo2 (t t1 ) . is (t) = Ls

Since the voltage vp is not changed in this mode, (1) is still effective. In this mode, the switch current iS 1 and iS 4 can be written by Vin n (nVin Vo2 ) + (t t1) . Lm Ls (5) At the end of this mode, the currents im and is arrive at their maximum values Im 1 and ID o 2 , respectively. Mode 3 [t2 , t3 ]: Similar to mode 1, the switches S1 and S4 are turned OFF at t2 . The parasitic capacitors C1 and C4 start to be iS 1 (t) = iS 4 (t) = im (t1 ) +

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From (11), the clamping capacitor voltage Vc is obtained by Vc = B. Voltage Gain From (2) and (9), the maximum diode current ID o 1 can be written as follows: nVin + Vo1 d1 T s ID o1 = Ls = n (Vin + Vc ) Vo1 (1 D d2 ) Ts . Ls D d1 (D/1 D)d2 nVin . 1 D + d1 d2 (13) 2D 1 Vin . 1D (12)

From (12) and (13), the voltage Vo 1 is obtained by Vo1 = (14)

Similarly, from (4) and (7), the maximum diode current ID o 2 can be written as follows: nVin Vo2 n (Vin + Vc ) + Vo2 ID o2 = (D d1 ) Ts = d2 T s . Ls Ls (15) From (12) and (15), Vo 2 can be obtained by Vo2 = D d1 (D/1 D)d2 nVin . D d1 + d2 (16)

In Fig. 2, the secondary current is is the sum of the current owing through the output capacitors Co 1 and Co 2 . Therefore, the average value of is should be zero. As a result, the average values of the diode currents iD o 1 and iD o 2 are equal to the output current Io and the following relation can be obtained by Io = (D d1 + d2 ) ID o2 (1 D + d1 d2 ) ID o1 = . (17) 2 2 From (13) through (17), d1 and d2 is obtained by d1 = kD d2 = k (1 D) 1 k= 2 1 8Ls Io 1 nDVin Ts . (18) (19) (20)
Fig. 5. Voltage gain M: (a) according to D and (b) according to k.

be zero under a steady-state condition, the average value of iS 3 is zero. Therefore, the following relation can be obtained from Fig. 3 as follows: Im 1 + Im 2 (1 D) Ts 2 ID o2 d2 Ts ID o1 (1 D d2 ) Ts +n 2 2 Using (17) and (21), the (23) can be rewritten as Im 1 + Im 2 Iin = 0 (24) 2 where Iin ( = Vo Io /Vin ) is the average input current at unity efciency. From (22) and (24), the maximum value Im 1 and the minimum value Im 2 are given by Im 1 = Iin + Im 2 = Iin Vin DTs 2Lm Vin DTs . 2Lm (25) (26)

Using (14), (16), (18), and (19), the voltage gain M of the proposed converter is obtained by M= n (1 2k) D Vo . (21) = Vin (D + (1 2D)k) (1 D (1 2D)k)

= 0. (23)

Fig. 5(a) shows the voltage gain M according to D with k = 0.07 and Fig. 5(b) shows M according to k with n = 3. C. Maximum and Minimum Values of the Magnetizing Current im From (1), the following relation is obtained by Im 1 Im 2 = Vin DTs . Lm (22)

In modes 3 and 4, the switch current iS 3 is owing through the clamping capacitor Cc . Since the average capacitor current must

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D. ZVS Conditions for the Switches S1 Through S4 From Fig. 3, there is no current cancellation between ip (=nis ) and im at t2 . Therefore, for ZVS of S2 and S3 , the total energy stored in Lm and Ls should be larger than the energy stored in C1 through C4 . Namely, the following condition should be satised:
2 2 2 Ls ID o2 (C1 + C2 ) Vin Lm Im 1 + > 2 2 2

it is selected as 0.06 by considering the diode current changing slopes. From (29), it can be seen that the voltage stresses of S3 and S4 depend on D. If they need to be kept below 150 V, D should be smaller than 0.75. Therefore, the maximum duty cycle Dm ax is determined as 0.7. Since the required voltage gain is 8.3, the turn ratio n can be calculated from (21) by using k and Dm ax . B. Selection of Ls From (20), the serial inductor Ls can be determined as follows: nDm ax Vin Ts 1 (1 2k )2 . (30) Ls = 8Io,m ax By using previously selected k and Dm ax , (32) gives Ls = 87.5 H. Then, Ls is selected as 90 H. C. Selection of Lm From (17), ID o 1 is calculated as 2.287 A. By assuming the output capacitances C1 through C4 of the switches as 500 pF, the inequality of (28) gives Lm < 136 H. Then, Lm is selected as 132 H. D. Selection of Cc , Co 1 , and Co 2 The switch current iS 3 ows through Cc . From the current waveform iS 3 in Fig. 3, the resulting ripple in the voltage across Cc depends on the area under the current waveform. The voltage ripple Vc across Cc is approximately given by Vc (1 D) Ts (Im 1 + nID o2 ) . 4Cc (31)

(C3 + C4 ) (Vin + Vc )2 . (27) 2 Since n, Im 1 , and ID o 1 always have positive values and C1 through C4 are quite small, it can be easily seen that the inequality of (27) is satised. On the other hand, there is current cancellation between ip ( = nis ) and im at t0 . Therefore, for ZVS of S1 and S4 , the energy difference between the energies stored in Lm and Ls should be larger than the energy stored in C1 through C4 as follows: +
2 2 2 Ls ID o1 (C1 + C2 ) Vin Lm Im 2 + > 2 2 2

(C3 + C4 ) (Vin + Vc )2 . 2 This condition can be used to determine Lm . + E. Voltage Stresses of Power Switches and Output Diodes

(28)

Maximum values of vS 1 and vS 2 in the rst bridge are conned to the input voltage Vin . The voltage stresses of S3 and S4 are the sum of the input voltage Vin and the clamping capacitor voltage Vc . Since the clamping capacitor voltage depends on the duty cycle, the voltage stresses of S3 and S4 can be changed according to load. Maximum values of vS 3 and vS 4 in the second bridge is given by vS 3,m ax = vS 4,m ax = Vin + Vc = DVin . 1D (29)

From (31), Cc should be larger than 3.49 F to keep Vc below 1 V. The value of Cc is selected as 6.6 F. The secondary current is ows through Co 1 and Co 2 equally. The voltage ripple Vo 1 across Co 1 is given by Vo1 = (D d1 + d2 ) Ts ID o2 . 4Co1 (32)

When the duty cycle D is below 0.5, the maximum values of vS 3 and vS 4 are lower than the input voltage Vin . Due to the voltage doubler structure, the maximum values of the voltages across the output diodes are conned to the output voltage Vo . IV. DESIGN EXAMPLE To validate the characteristic of the proposed converter, design procedure is given in this section with the following specications: 1) Input voltage Vin = 48 V. 2) Output voltage Vo = 400 V. 3) Maximum output power Po, m ax = 150 W. 4) Switching frequency fs = 74 kHz. A. Selection of k , Dm ax , and n As shown in Fig. 5(b), the smaller k is, the higher the voltage gain is. However, to obtain zero-current switching (ZCS) of output diodes, a proper k is needed. Since k is a function of the output current Io , k is dened as k under full load condition and

From (32), Co 1 should be larger than 18.75 F to keep Vo 1 below 0.1 V. The value of Co 1 is selected as 47 F. Similarly, Co 1 is selected as 47 F. V. EXPERIMENTAL RESULTS According to the design guideline presented in the previous section, the prototype was implemented. The control circuit was implemented with a constant-frequency pulsewidth modulation controller KA7552 from Fairchild. The PWM output of KA7552 is fed to MIC4428 which has one inverting plus one noninverting output. They are then fed to IR2110s which generate gate signals for each bridge. For S1 through S4 , n-channel power MOSFETs are used. Fig. 6 shows the gate driving circuit. FQP85N06 is used for S1 and S2 and FQP32N20C is used for S3 and S4 . For the output diodes Do 1 and Do 2 , the ultrafast recovery diode RF2001T4S from Rohm is used. Fig. 7 shows p-spice simulation results based on the specications and the

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Fig. 6.

Gate driving circuit.

Fig. 8.

Measured key waveforms.

Fig. 7.

Simulation Results.

circuit parameters of the prototype. It shows the key waveforms of the proposed converter and the soft-switching waveforms of the power switches S1 through S4 and the output diodes Do 1 and Do 2 . Fig. 8 shows the measured key waveforms of the proposed converter. It shows the currents is and iT , the clamping capacitor voltage Vc , and the switch voltage vS 2 . According to (12), the

clamping capacitor voltage Vc should be 64 V. It agrees with the experimental result. The measured maximum voltage stress of S4 is around 110 V, which agrees with the theoretical analysis. The measured soft-switching waveforms of all switches and diodes are shown in Fig. 9. The ZVS operations of the power switches are shown in Fig. 9(a)(d). The voltages across the switches go to zero before the gate pulses are applied to the switches. Since the switch voltages are clamped as zero before the gate pulses are applied, the ZVS turn-ON of the switches is achieved. Fig. 9(e) shows ZCS of the output diodes. After the diode currents fall to zero, the voltages across the diode rise to the output voltage Vo . Therefore, the ZCS turn-OFF of the output diodes is achieved. It can be seen that the voltages vD o 1 and vD o 2 are conned to Vo . Fig. 10 shows the measured efciency of the proposed converter. The power consumed in the control circuit is ignored. The proposed converter exhibits the efciency of 95.3% at full load. Due to its soft-switching characteristic and alleviated reverse-recovery problem, it shows a higher efciency than the conventional PSFB converter.

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Fig. 9.

Measured soft-switching waveforms of (a) S1 , (b) S2 , (c) S3 , (d) S4 , and (e) Do 1 and Do 2 .

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Fig. 10.

Measured efciency.

VI. CONCLUSION In this paper, an asymmetrical full-bridge converter with highvoltage gain has been presented. The ZVS of all power switches and ZCS of the output diodes are achieved. The proposed converter is able to provide a high efciency and high-voltage gain with relatively low transformer turn ratio. Also, without any auxiliary circuits, the voltages across the switches and the output diodes are effectively clamped. Therefore, the proposed converter is suitable for high-voltage applications. A prototype was built to verify the performance of the proposed converter. The voltage gain is 8.3 with the transformer turn ratio of 3. It provides a high efciency of 95.3% at full load. REFERENCES
[1] R. J. Wai, W. H. Wang, and C. Y. Lin, High-performance stand-alone photovoltaic generation system, IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 240250, Jan. 2008. [2] C. Wang and M. H. Nehrir, Power management of a standalone wind/photovoltaic/fuel cell energy system, IEEE Trans. Energy Convers., vol. 23, no. 3, pp. 957967, Sep. 2008. [3] R. J. Wai and W. H. Wang, Grid-connected photovoltaic generation system, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 3, pp. 953964, Apr. 2008. [4] M. Prudente, L. L. Ptscher, G. Emmendoerfer, E. F. Romaneli, and R. Fules, Voltage multiplier cells applied to non-isolated DC-DC converters, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 871887, Mar. 2008. [5] E. H. Ismail, M. A. Al-Saffar, A. J. Sabzali, and A. A. Fardoun, A family of single-switch PWM converters with high step-up conversion ratio, IEEE Trans. Circuit Syst. I, vol. 55, no. 4, pp. 11591171, May 2008. [6] Z. Liang, R. Guo, J. Li, and A. Q. Huang, A high-efciency PV moduleintegrated DC/DC converter for PV energy harvest in FREEDM systems, IEEE Trans. Power Electron., vol. 26, no. 3, pp. 897909, Mar. 2011. [7] W.-S. Liu, J.-F. Chen, T.-J. Liang, and R.-L. Lin, Multicascoded sources for a high-efciency fuel-cell hybrid power system in high-voltage application, IEEE Trans. Power Electron., vol. 26, no. 3, pp. 931942, Mar. 2011.

[8] L.-S. Yang, T.-J. Liang, and J.-F. Chen, Transformerless DC-DC converters with high step-up voltage gain, IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 31443152, Aug. 2009. [9] Q. Zhao, F. Tao, Y. Hu, and F. C. Lee, Active-clamp DC/DC converter using magnetic switches, in Proc. IEEE Appl. Power Electron. Conf. Expo., 2001, pp. 946952. [10] D. A. Grant, Y. Darroman, and J. Suter, Synthesis of tapped-inductor switched-mode converters, IEEE Trans. Power Electron., vol. 22, no. 5, pp. 19641969, Sep. 2007. [11] L. Zhu, K. Wang, F. C. Lee, and J. S. Lai, New start-up schemes for isolated full-bridge boost converters, IEEE Trans. Power Electron., vol. 18, no. 4, pp. 946951, Jul. 2003. [12] E. Adib and H. Farzanehfard, Zero-voltage transition current-fed fullbridge PWM converter, IEEE Trans. Power Electron., vol. 24, no. 4, pp. 10411047, Apr. 2009. [13] Y. Jang and M. M. Jovanovic, A new family of full-bridge ZVS converters, IEEE Trans. Power Electron., vol. 19, no. 3, pp. 701708, May 2004. [14] M. Borage, S. Tiwari, S. Bhardwaj, and S. Kotaiah, A full-bridge DC-DC converter with zero-voltage-switching over the entire conversion range, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 17431750, Jul. 2008. [15] Y. Jang and M. M. Jovanovic, A new PWM ZVS full-bridge ZVS converter, IEEE Trans. Power Electron., vol. 22, no. 3, pp. 987994, May 2007. [16] M. Ordonez and J. E. Quaicoe, Soft-switching techniques for efciency gains in full-bridge fuel cell power conversion, IEEE Trans. Power Electron., vol. 26, no. 2, pp. 482492, Feb. 2011. [17] W. Chen, X. Ruan, and R. Zhang, A novel zero-voltage-switching PWM full bridge converter, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 793801, Mar. 2008. [18] R. Redl, N. O. Sokal, and L. Balogh, A novel soft-switching full-bridge dc-dc converter: Analysis, design consideration, at 1.5 kW, 100 kHz, IEEE Trans. Power Electron., vol. 6, no. 4, pp. 408418, Jul. 1991. [19] P. Imbertson and N. Mohan, Asymmetrical duty cycle permits zero switching loss in PWM circuits with no conduction loss penalty, IEEE Trans. Ind. Appl., vol. 29, no. 1, pp. 121125, Jan./Feb. 1993. [20] A. Fiedler and H. Grotstollen, Investigation of asymmetrical phaseshifted full bridge, in Proc. IEEE IECON, 1995, pp. 434439. [21] A. J. Zhang, G. Huang, and Y. Gu, Asymmetrical full bridge DC-to-DC converter, U.S. Patent 6 466 458, Oct. 15, 2002.

Hyun-Lark Do received the B.S. degree from Hanyang University, Seoul, Korea, in 1999, and the M.S. and Ph.D. degrees, both in electronic and electrical engineering, from the Pohang University of Science and Technology, Pohang, Korea, in 2002 and 2005, respectively. From 2005 to 2008, he was a Senior Research Engineer with the PDP Research Laboratory, LG Electronics Inc., Gumi, Korea. Since 2008, he has been with the Department of Electronic and Information Engineering, Seoul National University of Science and Technology, Seoul, where he is currently a Professor. His research interests include the modeling, design, and control of power converters, soft-switching power converters, resonant converters, power factor correction circuits, and driving circuits for plasma display panels.