Towards High Performance and Low Power ADC

Introduction to Microelectronics

Abhishek Minni 4033310 Supervisor: Dr. Ir. W.A. Serdijn

1. INTRODUCTION
The realm of electrical engineering disciplines prevalent around us has paved the way for structuring a society that is hassle free, making life much simpler. This conjunct effort has a significant contribution indebted to the digital integrated circuits which have developed rapidly in past few decades. With the advancement in integrated-circuit fabrication, starting with medium-scale integration and progressing to large-scale integration and now, very large scale integration of electronic circuits has spurred the development of powerful, smaller, and faster special purpose systems. These systems support a spectrum of signals ranging from telecommunications, medical imaging and sensing, speech and many others. To harvest the benefit from the advancement in technology, it is important to develop high performance and low power analog interface circuitry that can be easily integrated with the modern technology. Today, the high speed CMOS transistors are developed using thin gate oxide which requires use of lower gate voltage. The reduced supply voltage reduces the use of topology like cascode to increase gain and forces the use of cascade stages to obtain loop gain. Use of these stages increases poles inducing signal delay, requiring large capacitors and complicated compensation schemes. Analog circuitry no longer performs better in the scaled technology asserting the need of ADC architectures that do not rely on feedback based signal processing to achieve required resolution. In the recent years, ADC architectures such as SAR, Subranging and Pipelined are gaining attention due to their high performance in scaled technology. One of the major issues in designing architectures today is imposed by signal-to-noise ratio (SNR). As the supply voltage reduces, the performance of high resolution ADCs is limited by the thermal noise. To achieve required dynamic performance, a larger capacitance is needed to keep KT/C noise in check. This increases the transconductance of the opamp requiring larger bias current and larger transistor size to achieve speed. As the technology scales down, the power and area increases due to above mentioned reason. Many circuit techniques are employed to reduce the effect of power maintaining the performance. In the next section brief review of various ADC architectures is presented. Further few power reducing techniques in pipelined ADC and SA-ADC is discussed. 2. ADC

ARCHITECTURES

2.1 Flash ADC The simplest ADC architecture is flash ADC. These ADCs are used for high speed mid resolution systems. Increase in resolution of flash ADC by 1 doubles the comparators and also larger size comparators have to be employed to reduce input referred offset for achieving required INL/DNL specifications. Many techniques such as pre-amplification and offset averaging reduce the required area and input capacitance but still impose constraint on power. Most of the power is consumed is due to large number of preamplifiers and comparators. The static power consumption of reference ladder is also a major power issue. Due to these reasons, flash architectures are used for low resolution ADCs.

2.2 Pipelined ADC The functional block diagram for a pipelined multistage A/D converter is shown below in fig1. The system consists of K stages, each comprising a low resolution n-bit ADC whose digital outputs drive n-bit digital-to-analog converter (DAC) to give quantized analog estimate of the input.

N ni
i 1

(1)

Where N is total resolution and ni is the resolution of the stage i. If equality holds in the equation, there is no redundancy of bits. Each stage contains a sample-and-hold amplifier (SHA), a low resolution analogto-digital converter (ADSC), a low resolution digital-to-analog converter (DAC) and a subtractor. The quantized analog signal in each stage is subtracted from the held input, producing a residue, Ri, that is sent to the next stage for conversion.

Fig1. Block diagram of a multistage pipelined ADC [1] Most of the video applications require a conversion rate of around 20MS/s. This corresponds to conversion period of 50ns which means amplifier settling time must be less than 25ns. Assuming each stage has same stage resolution, the time required depends on optimum stage resolution. Minimum stage resolution is selected in order to achieve high input bandwidth as the interstage gain decreases. Due to advances in technology, a higher stage resolution can also be used as with increasing technology, gainbandwidth product increases. Increase in stage resolution reduces noise contribution by later stages considerably. The accuracy of pipelined ADC depends heavily on the amplification of the residue requiring opamp with high gain. Although this constraint can be relaxed by use of digital calibration circuit. With the use of digital circuitry and pipelining, these ADC architectures can be employed in high resolution systems maintaining speed and performance. The much reduced input capacitance allows us to use higher bandwidth signals. However, the use of high gain opamp or digital calibration circuit increases power significantly.

2.3 SIGMA-DELTA To achieve high resolution (14-20 bits), pipelined ADCs require complicated digital calibration techniques. The over sampling nature of sigma-delta architectures allows it to achieve high resolution reducing anti-alias filter requirement and capacitor sizes. The use of huge digital decimation filter required to shape the noise introduces a delay in the signal. Therefore, this architecture is most suited for high resolution - low speed applications.

2.4 SUCCESIVE APPROXIMATION ADC Successive approximation is very hardware efficient architecture. A digital-to-analog converter (DAC) is used to estimate the value of input signal by successive approximations and comparisons. After few clock cycles the sample value is stored in a register often known as successive approximation register. Use of DAC in feedback eradicates issues related to analog feedback such as gain margin, linearity, and phase margin. The settling of the system can be controlled by the passive switch capacitor network which is faster than opamp based switched capacitor network used in other architectures. The major drawback of SA-ADC is the large size of capacitor network when the number of bit increases as there is huge difference between the capacitance corresponding to MSB and capacitance corresponding to LSB. Due to this reason they are best suited for mid resolution ADCs. 3. POWER REDUCING TECHNIQUES: PIPELINED ADC 3.1 Pseudodifferential Architecture The block diagram of architecture as shown below in the figure clearly shows a pipelined ADC with S/H in front followed by nine stages of 1.5b per stage. Each stage consist a multiply-by-two amplifier, 1.5b sub-ADC, and 1.5b sub-DAC. The resulting 10 bits is obtained by digital correction.

Fig. 2 Block diagram of pseudodifferential pipelined ADC. PD: Pseudodifferential stage D: Differential Stage [2].

This architecture works almost similar to a fully differential architecture but suffers from variations in common mode value. The slight variation in common mode value of signal is amplified by factor of two in each stage leading to high non linearity. Two differential stages are used in between to avoid such an error. Fig. 3 shows the pseudo-differential multiply-by-two stage. In the sampling phase, the input is sampled over capacitor C1, C2, C3 and C4. During the multiply and subtract phase, the bottom plate of C1 and C3 is connected to the output and the bottom plate of C2 and C4 is connected to reference voltage (V r+, Vr,Vc) depending on the comparison done at the end of sampling phase. Drive voltages of switches are boosted using bootstrap circuit [3]. This reduces the signal dependence of the on-resistance and charge injection.

Fig3. a) Pseudodifferential multiply-by-two amplifier b) Comparator and logic [2]

Fig4. Gain Boosting cascode amplifier [2]

A regulated cascode amplifier is used to reduce the power consumption. A low DC bias current is used to bias the amplifier and gain boosted amplifier is used to increase the open loop gain. Gain boosting amplifier increases the gain of the amplifier without affecting the frequency behavior of the amplifier. Fig. 4 shows the circuit implementation of such a amplifier. When the input is connected to output cancelling the offset, the switch S of the amplifier is turned on and M2, M4 are biased such that to achieve maximum output swing. In the amplying phase, the switch S is turned off providing amplifier a regulated cascode structure coupled with a capacitor. Due to stacking of extra transistor, the voltage

swing is affected but this is countered by use of dynamic biasing of the circuit using switch S as mentioned earlier. The regulated structure is biased using a low dc bias current as it does not affect the frequency behavior of the system. Here Io/4 is used to bias the structure with W/L ratio of M5-M7 as quarter of M2 or M4 so as to achieve perfect biasing. A fully differential amplifier consumes much higher bias current for same drive capability. Below in fig.5, folded cascode opamp with gain boosting is shown. For same drive capability, Iss = 2Io and each of A1, A2 consumes Io/2 for biasing. Current through M9 and M10 is also Io. Therefore, for same drive ability a fully differential amplifier consumes about 5Io for biasing.

Fig5. Fully differential cascode amplifier [4] Compared to a fully differential amplifier, a single-ended amplifier consumes only 1.5 Io for biasing. As two single ended amplifiers are used in one stage, the total dc biasing current equals 3Io. Also, in folded cascode amplifier the capacitance corresponding to non-dominant pole is larger compared to single-ended due to contribution of the drain capacitance of the input capacitance of differential stage. Therefore, there is increase of 17% in power consumption. Hence, total power reduction is around 50%. 3.2 Flip around digital to analog converter (FADAC) In pipelined ADC most of the power is consumed by S/H and first stage of the ADC (50%). The following proposed method reduces power consumption by 25%. Fig.6 below describes the operation of sample, compare and hold mode.

Fig. 6 Schematic and operation of FADAC [5]

The flip around architecture consumes less power than charge redistribution architecture because Amplifier does not have to charge the capacitor in hold phase, it just shares the charge between the capacitors. Therefore, it uses less power. The capacitor is connected between input and output node only in hold phase which provides feedback gain equal to 1 whereas in the charge redistribution, input node is in middle providing feedback gain of 0.5. Lower the feedback gain larger is the settling time of the amplifier. Therefore, FADAC has smaller settling time which means less power is needed to drive the amplifier. Figure below shows the charge distribution [5].

4. POWER REDUCING TECHNIQUES: SA-ADC 4.1 Split architecture The major drawback of SA-ADC is larger size of capacitor network. This increases the area as the unit capacitance value is restricted by KT/C noise. To reduce the capacitor size, a split architecture is used as shown in below fig.7. The capacitor network is split using a capacitor (C A). The left part is deployed with unary-weighted capacitances for MSBs and binary weighted for LSBs. The choice of number of bits for both parts depends on power consumed by the binary-to-thermometer decoder. Different supply voltages can be used to reduce the power. As the dynamic power consumption in digital circuits is proportional to square of supply voltage, multiple supply levels can be generated for analog and digital circuits. However, this leads to complex design as it might affect the linearity of the SA-ADC

Fig.7 Split Architecture [6] Use of unary weighted capacitors reduces the power consumption further. For each sample value, capacitors are charged to supply voltage and then discharged depending upon the sample value. For example, when the DAC input code changes from 1000 to 0100, 8 capacitors connected to supply voltage are discharged and 4 capacitors are charged. If a unary weighted array is used than only 4 capacitors are discharged. This approach reduces power consumption by 25%, assuming there is equal probability for the input signal to be above or below half of supply voltage. 4.2 Dual Sampling method Many applications related to bio-medical and wireless networks demands low power ADCs. These applications need high resolution which requires a larger capacitor network. By dual sampling method, the MSB operation can be eliminated which reduces the capacitor network size to half.

Fig.8 Dual sampling architecture [7]

As shown in fig.8, this architecture requires capacitance of 2N-1 C+ CBST. For a typical CDAC, reference voltage is connected to one input of the comparator and other input is connected to output of the CDAC which is connected to 2N C. In dual sampling ADC, the input of the comparator is connected to CBST and other input is connected to 2N-1 C (CDAC). During the sampling mode, the CDAC samples Vinput-Vref and the CBST samples Vinput. Now in the hold mode, the MSB is decided differentially by the comparator which requires zero energy. From the next clock cycle, the process works typically as in successive approximation. Below in the fig.9 and fig.10 difference between two schemes is outlined.

Fig. 9 Switching sequence of split cap [7]

Fig.10 Switching sequence of dual sample [7]

Comparison of Switching Energy of conventional, split cap and dual sampling architecture

Fig.11 Comparision of Switching energy [7] Fig.11 shows that there is reduction of around 68% of switching energy as compared to a conventional architecture. Moreover, the energy is uniformly distributed across the codes which improves the linearity of the system. 5. Conclusion and future directions No research is meaningful unless it meets the demands of the society. There are two main market segments for advanced integrated circuits high performance analog/mixed-signal ICs and high volume consumer ICs. High performance analog/mixed-signal ICs includes high resolution, high speed data converters which are majorly used in professional audio, military and other such applications. These applications often require high power, high voltage systems with less room for innovation, often specific to each system. Mainly sub-ranging or pipelined converters are used for such systems. The high volume consumer ICs segment includes microprocessors, graphics chips, cell phones, chips used in product such as USB, HDD, DVD, pacemaker and other such applications. These applications often require low voltage low power system. This limits the use of many transistor level circuit techniques. It is then required to innovate at architecture level such that the same function can be implemented robustly with low power consumption. Use of architectures like SAR and sigma delta is gaining popularity in this domain as the pipelined and sub-ranging architectures lead to much higher power consumption. As discussed earlier, SAR architectures with low switching energy, consume power in the order of few hundred micro-watt while the piplelined architectures with the use of pseudodifferential amplifiers, consumes power in the order of few milli-watt. The limit on the ADC sampling rate can be estimated using Heisenbergs uncertainty principle. Fig. 12 below illustrates the analysis. For 50 ohm impedance and 1V peak-to-peak input signal, the limit is approximately four orders of magnitude ahead of state-of-art [8]. The analysis is done assuming the aperture jitter as the limiting factor which depends heavily on the technology state.

Fig. 12 Applying Heisenberg uncertainty principle to ADC performance [8] Although there are other technology limitations which affect the sampling rate of ADC but due to scaling in the technology and increase in the fT aperture jitter seems to be the dominant parameter. Along with the architecture techniques mentioned above to reduce power there are many other techniques which can further enhance the system performance and will push to the limit as stated by the Heisenberg principle. Few future explorations: 1) Use of a better technology process will reduce limitation due to the aperture jitter. 2) Use of high sampling frequency and smaller capacitor can be used to over-sample analog signal, such that more signal processing can shift to discrete-time. This will provide high dynamic range and less power consumption. 3) Use of digital feedback instead of analog feedback will help in providing better control and stability. It is the most important reason for the use of SAR and sigma delta architecture. 4) Increased level of digital programmability which may allow trade-off between bandwidth, noise and distortion leading to low power designs.

REFERENCES [1] S. H. Lewis, H. S. Fetterman, G. F. Gross, R. Ramachandran, and T. R. Vishwanathan,A 10-b 20MS/s analog-to-digital convereter, IEEE Journal of Solid-State Circuits, vol. 27, pp 351-358, Mar. 1992. [2] D. Miyazaki, S. Kawahito, M. Furuta, A 10-b 30MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture, IEEE Journal of Solid-State Circuits, pp. 369373, 2003. [3] A. M. Abo and P. R. Gray, A 1.5-V 10-b 14.3 MS/s CMOS pipeline analog-to-digital converter, IEEE Journal of Solid-State Circuits, vol. 34, pp 599-606, May. 1999. [4] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill Edition 2002. [5] Masato Yoshioka, Masahiro Kudo,10-bit, 125 MS/s, 40mW Pipelined ADC in 0.18um CMOS, Fujitsu Sci. Tech. J., 42,2, April 2006. [6] Reza Lotfi, Rabeeh Majidi, Mohammad Maymandi-Nejad, and Wouter A. Serdijn,An UltraLow-Power 10-Bit 100KS/s Successive-Approximation Analog-to-Digital Converter, proc. IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 24 - 27, 2009. [7] B Kim, L Yan, J Yoo, N Cho, HJ Yoo, An energy-efficient dual sampling SAR ADC with reduced capacitive DAC, IEEE International Symposium on Circuits and Systems, 2009. [8] Robert H. Walden, Analog-to-Digital Converter Survey and Analysis, IEEE Journal on Selected Areas in Communications, Vol. 17, No. 4, April 1999.