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In this Chapter, we will discuss the most complicated stage of each design the System design. As an example we will use the design of a rather simple Processor. VHDL code for this design will be discussed in the next chapter. Our system design contains the following steps: 1. Representation of separate sub-behaviors (instructions in our case) with functional ASMs; 2. Combining of these ASMs into one combined functional ASM and its minimization; 3. Synthesis of Data path; 4. Transfer from the combined functional ASM to the structural ASM corresponding to Data path; 5. Control unit design; 6. Composition of Data and Control unit into whole Processor. Practically, all steps of such design are formalized and were automated in EDA tool Abelite designed by the author of this book.
a)
b)
reg_16bit
c)
din dout en
d)
e)
f)
Figure 1. Main processor units One more small memory Block of Register (bor) contains sixteen 16-bit registers (Fig. 1,b). For operation write, there must be some data at the bus din and an address at the bus adr. When enable signal en = 1, data is loaded through the input din at the rising edge of the clock signal. For example, if adr = 0011 and en = 1, then R[3] (register number 3) will get information from input din. In operation read from the bor, the signal en should be set to 0. Arithmetic logic unit (alu) is used for implementation of arithmetic and logic operations (Fig. 1,c). Two 16-bit inputs in1 and in2 serve for operands of alu, 5-bit input ctr serves for instruction codes of alu operations. The result of the operation appears at the output dout. One additional one-bit output z is connected with flag zero. Our alu is a combinational circuit (circuit without memory) so Processor has ralu (the register of alu) to save the results of arithmetic and logic operations.
Program counter (pc) points to the next instruction which should be implemented (Fig. 1,d). It saves the address of such instruction. Input en is used to load 16-bit information from din to the counter when en = 1. When count = 1 the content of the counter increases by one. Instruction register contains the instruction which is being currently implemented. As most of processor registers, it has the structure shown in Fig. 1,e. Such a register has 16 clocked D flipflops with input rst to reset it and input en (enable signal), this signal should be equal to one to write information from input din into the register. We skipped signals clk (clock) and rst (reset) in our pictures. Index arithmetic logic unit (ialu in Fig. 1,f) can implement only one operation - addition. With one operation it doesnt need input ctr. ialu is used in the indexed addressing mode see section Addressing modes below. 7.1.2 Instruction set and instruction formats. The instruction set of Processor is presented in Table 1. It contains four subsets, or subgroups of operations: aosh, load, branch and inout. Assembly names of instructions are in the column Name, their machine codes are in the column Code. Column Description contains short description of each operation. You can use Table 1 as a reference table. We will discuss execution of each instruction in the following sections. Table 1. Set of instructions Code 00001 00010 00011 00100 00101 10000 10001 10010 10100 01000 01011 11000 11001 11010 11011 11100 11101 Name add and sub shl shr lod str inc com bcz bun ski sko inp out ion iof Oper1 Oper1 Oper1 Oper1 Oper1 Oper1 Oper2 Oper1 Oper1 := := := := := := := := := Function Oper1 + Oper2 Oper1 AND Oper2 Oper1 - Oper2 One-bit logical shift to the left of Oper2 One-bit logical shift to the right of Oper2 Oper2 Oper1 Oper1 + 1 not Oper1 Addressing Short Dir Indir Dir + + + i + + + i + + + i + + + i + + + i + + + + + + + + + i + i Mode Long Indir + i + i + i + i + i + i + i
Imm + + + + + +
Branch to Oper2 if zero flag is set to 1 Branch unconditionally to Oper2 Skip next instruction if the Input Flag is set to 1 Skip next instruction if the Output Flag is set to 1 Oper1:= Input Register; reset Input flag Output Register := Oper1; reset Output Flag Turn on the Interrupt Enable Flag Turn off the Interrupt Enable Flag
+ i + i
+ i + i
+ +
+ +
i indexed address Processor has two instruction formats (Fig. 3) short (one word, 16 bits) and long (two words, 32 bits). The first twelve bits have the same mission in both formats. Bit 10 points to the length of instructions short (bit 10 equal to zero) or long (bit 10 equal to one). The next two bits define the addressing mode. We will talk about it later. The short instruction cannot use operands from operand memory m1. To access this memory, the 16 bit address should be in the instruction. So, the short instruction uses only operands from bor bits 7-4 define the address of the first operand in bor and the address of the result, whereas bits 3-0 define the address of the second operand in bor. In the long instruction, we will use the field from bit 3 down to bit 0 as address of index register, the second operand is in the memory m1 and
its 16 bit address is in the second instruction word. Sometimes, we have operand itself in the second word see the immediate addressing mode below. Our Processor uses 16-bit words, so 16-bit Instruction Register cannot save the long instruction. Therefore, Processor has two instruction registers ir1 and ir2, sixteen bits each. In the memory, the short instruction takes one word, the long one two sequential words. Processor fetches the short instruction into ir1 and the long instruction into ir1 and ir2. The first half of the long instruction, containing its code, length, addressing mode and two short addresses is fetched into ir1, the second half into ir2.
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14
11
Second operand (data or address) Figure 2. Instruction formats 7.1.3 Addressing modes. Addressing mode defines how Processor finds operands using their addresses in the instruction. In both formats short and long, the address of the first operand and the address of the result are in bits 7-4 of the first instruction word. So, the different addressing modes will be essential only for the second operand. Now we shortly discuss several addressing modes: Direct addressing mode is the simplest one. In this mode, addresses of operands are written within the instruction. In the short format (Fig. 3,a), addresses of the first and the second operands A1 and A2 are in bits 7-4 and 3-0, operands themselves are in bor. In the long format (Fig. 3,b), address A1 is in the bits 7-4 and the long address A3 of the second operand is in the second word of such instruction. The second operand is in the operand memory m1 in the cell with address A3. In immediate mode, not the address of the operand, but the second operand itself is written in the second word of the instruction (Fig. 3,c). Thus, the immediate mode can be used only in the long instructions. In indirect mode, not the address of the operand, but the address of the address of the operand is written in the instruction. For the short format (Fig. 3,d), A2 in the field 3-0 points to the register in bor, where the memory address A3 of the second operand is saved. For the long format (Fig. 3,e), address A3 in the second word of the instruction points to the cell of the memory m1 which contains address A4 of the second operand. Thus, to reach the second operand in the long instruction, Processor should access the memory twice: first time for its address, second time for the operand itself. In the indexed addressing mode, Processor uses an index register to find the address of the operand. Any bor register except bor[0], can be used as an index register. For the long direct indexed mode (Fig. 3,f) the content A2 of the second address field (bits 3-0) in the first instruction word points to the index register in bor. Processor should add the content of this index register (offset) to the long address A3 (base address) from the second instruction word to find the address of the second operand (A3 + offset). Exactly in the similar way, we can define indirect indexed addressing mode.
Memory M0
...
Memory M0
BoR
Memory M1
...
A1
...
...
a) Short, Direct
Memory M0 BoR A1 Op1
b) Long, Direct
Memory M0 BoR A2 A1 A2 Op1 A3 A3
...
Memory M1
...
...
A1 0000 Op2
...
A1
Op2
c) Long, Immediate
d) Short, Indirect
...
Memory M0 A1 0000 A3 A1
BoR
Memory M1
Op1
A3
...
A4
Op2
e) Long, Indirect
Memory M0
Memory M1
...
...
...
...
A4
A1 A3
...
Op2
Figure 3. Addressing modes We will use three addressing modes in our Processor direct (bits 9 and 8 in Fig. 2 are equal to 00), immediate (01) and indirect (11).
...
...
...
...
...
...
...
...
...
information. ext_rdwr is the signal from outside. When ext_rdwr=1, external system writes information to memory m0 (external signal m should be equal to zero) or to memory m1 (external signal m should be equal to one) from its output ext_out. When ext_rdwr = 0, external system reads information from memory m0 or m1 to its input ext_in.
Signal r in the next conditional vertex tells us about an interrupt. If r = 1, the special mode of Processor Interrupt takes place. We will discuss interrupt later together with instructions from the group inout. When r = 0, there is no interrupt and the instruction is executed in regular mode. At the end of each instruction Processor checks the conditions for interrupt; we will discuss it later as well. So, now we will consider the implementation of instruction lod (long, direct) from r = 0 (from the beginning of block fetch1) until the first condition ien of block checkint. To explain the implementation of this instruction, we will use the sequence of figures beginning with Fig. 5. This figure presents the state of Processor before execution of instruction lod. We can see memory m0 (on the left), memory m1 and buffer register br (on the right) and bor, pc, ir1, ir2, ralu (in the middle). Really, here we have most of Processor units, except alu and ialu, because these units are combinational circuits and, in any case, the result of their operations will appear in registers ralu and rialu.
m0
0 1 2
255 256
320 321
0000
255 256
320 321
540
r[14] r[15]
540
964
ralu
RALU
964
220
1120 1121
pc
320
1120 1121
ir1
ir2
br
Figure 5. Before implementation of instruction lod The only information important prior to instruction implementation is the content of pc, which contains an address of the instruction in memory m0. Therefore, in the first step (Fig. 6 and the first operator vertex in fetch1 in Fig. 4), the output of pc should be connected to the address bus of the memory (m0_adr := pc) and the content of the memory cell with this address will be sent to the first instruction register ir1 (ir1:=m0[m0_adr]). Only when a short instruction, or the first word of the long instruction is in ir1, Processor can analyze the instruction code (ir1(15-11)), length (ir1(10)), addressing mode (ir1(9-8)) etc. In our notation, we use square brackets for addresses (m0[m0_adr]) and parenthesis for the fields of the register. For example, ir1(15-11) means bits 1511 of ir1, ir1(10) the tenth bit of ir1 etc. In the second step (Fig. 7 and the second operator vertex in Fetch1 in Fig. 4), Processor increments pc (pc := pc + 1). It is necessary to get an address of the next instruction in pc if the current instruction is short, or to give pc the address of the second word of the long instruction. So, if the current instruction is short, the fetch is finished and the instruction is in ir1. If the instruction is long, the fetch should continue. In our example, ir1(10) = 1 so we have a long instruction and Processor should access memory m0 again for the second part of this instruction see the check of ir1(10) and the stage fetch2 with two steps in Fig. 4 or Fig. 8 and Fig. 9.
m0
0 1 2
255 256
320 321
0000
255 256
320 321
540
r[14] r[15]
540
964
ralu
RALU
964
220
1120 1121
pc
320
1120 1121
ir1
10000
1 00
0101
0000
ir2
br
Figure 6. First step: m0_adr := pc; ir1 := m0[m0_adr] After Fetch2, the long instruction is in two instruction registers ir1 and ir2. ir1 tells us that it is instruction lod (ir1(15-11) = 10000), long (ir1(10) = 1) with the direct addressing mode (ir1(9-8) = 00), the second operand is in memory m1 in cell 964 (ir2 = 964) and this operand should be loaded into the place of the first operand in bor in register 5 (ir1(8-11) = 0101) through buffer register br:
Note, that it is sufficient to check only bit 8 in ir1 for the immediate addressing mode since we use only three addressing modes direct (00), immediate (01) and indirect (11).
m0
0 1 2
255 256
320 321
0000
255 256
320 321
540
r[14] r[15]
540
964
ralu
RALU
964 320 + 1 = 321 1120 1121
220
1120 1121
pc
ir1
10000
1 00
0101
0000
ir2
br
255 256
320 321
0000
255 256
320 321
540
r[14] r[15]
540
964
ralu
RALU
964
220
1120 1121
pc
321
1120 1121
ir1
10000
1 00
0101
0000
ir2
964
br
m0
0 1 2
255 256
320 321
0000
255 256
320 321
540
r[14] r[15]
540
964
ralu
RALU
964
220
1120 1121
pc
321 + 1 = 322
1120 1121
ir1
10000
1 00
0101
0000
ir2
964
br
255 256
320 321
0000
540 250 . . .
255 256
320 321
540
r[14] r[15]
540
964
ralu
RALU
964 322 1120 1121
220
1120 1121
pc
ir1
10000
1 00
0101
0000
ir2
964
br
220
Figure 10. Fifth step: m1_adr := ir2; br:=m1[m1_adr] Blocks Fetch1, DMACycle, IntCycle and CheckInt will be in ASMs for all instructions. Block Fetch2 will be only in ASMs for instructions with the long format. These blocks (we called them by generalized operators) are drawn separately In Fig. 12. If we replace dotted blocks in Fig. 4 by generalized operators we will get ASM in Fig. 13, which is simpler and clearer than ASM in Fig. 4.
m0
0 1 2
255 256
320 321
0000
255 256
320 321
540
r[14] r[15]
540
964
ralu
RALU
964 322 1120 1121
220
1120 1121
pc
ir1
10000
1 00
0101
0000
ir2
964
br
220
10
11
Figure 13. ASM of instruction lod with generalized operators In the next Sections, we will present ASMs with generalized operators for all instructions. 7.2.2 ASMs from group Aosh. All instructions from this group (see Table 1) are implemented in alu. Processor must send operands and instruction code to alu, save it in ralu and return the result from ralu in place of the first operand with an address in ir1(7-4). We can divide these instructions into two subsets: first, containing instructions add, and and sub; second, containing instructions shr and shl. They use one operand. However, we shouldnt distinguish this two set of instructions. Alu will get an instruction code from processor and will choose operands that it needs. Thus, you can draw only one ASM ao.vsd, make build and the copy three files ao.gsa, ao.mic and ao.txt to add, and, sub, shr, shl (three files for each of these five instructions) and even to inc and com from group Load, which are implemented in alu as well.
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7.2.3 ASMs from group Load. ASM for lod instruction (Fig. 4 and Fig. 13) was discussed in details above. Instruction str is inverse to instruction lod. Its goal is to store the first operand in place of the second operand. In the long direct mode, Processor sends the register from bor with an address in ir1(7-4) to memory m1 with an address in ir2: m1_adr := ir2; bor_adr := ir1(7-4); m1[m1_adr]:=bor[bor_adr]. In the short direct mode, Processor sends the register from bor with an address in ir1(7-4) to another register in bor with an address in ir1(3-0).
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For instruction lod, we discussed the long immediate mode in which Processor sends the second operand from IR2 into M1[Adr1]. Try to answer the following question why is there no sense in using this mode for instruction str? Fig. 17 presents ASM for three other instructions of this group inc, dec and com. Implementation of these instructions is similar to implementation of instructions ao (Fig. 14.
Figure 15. ASM of instruction str 7.2.4 ASMs from group Branch. Instructions from this group change, conditionally or unconditionally, the sequential execution of the program. The ASM for unconditional branch bun is shown in Fig. 16. It has three modes direct, immediate long and indirect. In the short direct mode, Processor sends the address of the new instruction from the register in bor with the second address in ir1(3-0) into program counter pc: bor_adr:=ir1(3-0); pc:=bor[bor_adr]. In the long immediate mode, Processor sends the address of the new instruction from ir2 to pc: pc:=ir2.
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In the long direct or indirect mode, as in the previous instructions, Processor finds the second operand according the generalized operator absadr and uses it as the address of the next instruction. ASM for conditional branch instruction bcz is presented in Fig. 17. In this instruction, the address of the next instruction depends on the values of zero flag (flag zf) which is the result of the previous operations in alu. After fetch, short or long, which depends on ir1(10), Processor checks the value of flag zf. If zf = 1, a jump to the instruction with the new address takes place. If zf = 0, Processor executes the instruction which is immediately after bcz in memory m0.
Figure 16. ASM of instruction bun 7.2.5 ASMs from group Inout. All instructions from group Inout are short and only two of them inp and out (Fig. 19 and Fig. 20) use an address of the first operand written in ir1(7-4). Other instructions are zero-address instructions. To explain ASMs of inp and out let us appeal to Fig. 18. When an input device had prepared new information it sets a special flag of input FGI (FlaG of Input) into 1. The goal of instruction inp is to take this information into inpr, to resend it into bor with an address in ir1(7-4) and to reset FGI. Thus, the implementation of this instruction is reduced to two steps: inpr:=data_in; bor_adr:=ir1(7-4); bor[bor_adr]:=inpr; fgi := 0.
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Ouput device
data_out
fgo_set 15
OutR
FGO
fgo_reset
BoR
fgi_reset
InpR
15
FGI
fgi_set
data_in
Input device
16
Figure 19. ASM of instruction inp ASM for instruction out is presented in Fig. 20. In this instruction Processor sends the word from bor with the address in ir1(7-4) into outr and then outside (into two steps) and resets fgo (FlaG of Ouput): bor_adr:=ir1(7-4); outr:=bor[bor_adr]; fgo:=0; data_out:=outr. The output device can take the contents of outr at any time. At the same time, it sets FGO into 1. To explain instructions ski (skip the next instruction if FGI = 1) and sko (skip the next instruction if FGO = 1) let us look at the small assembly program in Fig. 21. If FGI = 0, there is no new information at the input of the input register and the next instruction is implemented after instruction ski. This instruction is branch unconditional (bun) to address aa (to the label aa). Thus, Processor waits for the new information, doing nothing, being in the small loop.
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Figure 22. ASMs of instructions ski, sko 7.2.6 Interrupt system. Of course, input-output shown in Fig. 19-20 is not efficient, so each processor has an interrupt system. The goal of interrupt in our Processor is very simple to stop an execution of the program, when an input-output device addresses Processor and to jump to the subprogram for processing the input-output request. To explain the interrupt system in our Processor we will use Fig. 23; memory m0 is shown in this figure before and after the interrupt.
m1 m0 Main Program
243 244
m0 Main Program
243 244
200 201
. . .
1120 1120
. . .
I/O subprogram
lod 1 00 0000
I/O subprogram
lod 1 00 0000
xffff 00 0000
. . .
xfffd xfffe xffff xfffd xfffe
. . .
xfffd
. . .
bun 1 01 1120 After interrupt
bun 1
01 1120
xfffe xffff
xffff
Before interrupt
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Memory m0 in Fig. 23 contains the main program and the input-output subprogram for interrupt processing. Let us suppose that new information from the input device appears at the input of inpr (FGI = 1) during implementation of the instruction in the memory cell 243. In this case, the interrupt system should do the following: 1. Save return address 244; 2. Go to the I/O subprogram to process input-output; 3. Return to the instruction in cell 244. Our processor has a special place the last two cells in memory m0 and the last cell in memory m1 to realize the first two actions mentioned above look at Fig. 23. Processor saves the return address in the last cell xffff of m1. In the last two cells of m0, there is instruction bun (long brunch unconditional) to the beginning of the I/O subprogram. At the end of this subprogram, instruction lod saves the content of cell xffff from m1 (return address = 244) in r[0] of bor, and the next instruction bun with the short direct mode jumps to the instruction, the address of which (244) is written in r[0] of bor. In many cases the programmer should disable interrupts, there is such an option in our Processor as well. Processor has flag ien (interrupt enable): when ien = 1, the interrupt is enabled, when ien = 0, interrupt is disabled. Thus, an interrupt takes place (sign of this: r = 1, r is one of the first conditions in each ASM), when there is a reason for the interrupt (FGI = 1 or FGO = 1) and it is enabled (ien = 1). Otherwise, interrupt is disabled. At the end of ASM for each instruction, there is checking interrupt block - checkint (Fig. 12). If interrupt is enabled, the next instruction will execute the interrupt cycle. Our processor has two instructions to enable the interrupt (ion interrupt on) or disable it (iof interrupt off). ASM for ion is shown in Fig. 24,a. To construct an ASM for the iof instruction, we should replace the shadowed operator vertex ien = 1 in Fig. 24,a by the operator vertex in Fig. 24,b.
Figure 24. ASMs of instructions ion and iof To explain implementation of interrupt, look at both Fig. 23 and Fig. 25. Let interrupt take place after the instruction in cell 243 (see three signs !!! in Fig. 23). The program counter PC is equal to
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244 at this time, because it was incremented at the stage fetch of the instruction in cell 243. In the first operator vertex of Fig. 25 Processor writes the content of pc in the cell of memory m1 with address xffff. Thereby, the first step of the interrupt is realized the return address is saved. The next step of interrupt is implemented in the next operator vertex in Fig. 25. The value xfffe is written into pc. Thus, the next instruction that Processor will execute is the instruction in cell xfffe of m0 branch to the beginning of I/O subprogram.
Figure 25. Interrupt cycle The assignment ien := 0 forbids an interrupt during implementation of I/O subprogram we do not have multilevel interrupt in our Processor. Thus, we finished the detailed explanation of instructions and constructed ASMs for all of them. Now we can turn to design of Processor based on our design methodology with the use of VHDL.
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