SABANCI UNIVERSITY Faculty of Engineering And Natural Sciences Microelectronics Engineering EL 202 - Electronic Circuits II Spring-2003

Course Instructor: Assoc. Prof. Yasar Grbz e-mail: yasar@sabanciuniv.edu Office: FENS 1044 Tel: ext. 9533 TAs: hsan icek (ihsanc@su.sabanciuniv.edu), Head TA Mustafa Parlak (mparlak@su.sabanciuniv.edu) Mansoor Naseer (mansoor@su.sabanciuniv.edu) Beril S ifti (beril@su.sabanciuniv.edu) Aylin Ekim (ayline@su.sabanciuniv.edu)

Class Information
Lecture Recitation Labs : Section Office Hours:
Course Instructor: Monday 13:10 - 14:10 (Location: FENS 1044) TAs: Thursday 17:10-16:10 (Location: FENS 1040)

Time Mon. 09:10-10:00 Wed. 11:10-13:00 Fri. 11:10-13:00 Thursday 19:00 22:00

Place FENS L045 FENS L045 FENS G032 FENS 1067

Description:
Characteristics, applications, analysis, and design of circuits using BJTs and field-effect transistors (FET) with small and large-signal behaviors. Classroom concepts are reinforced through laboratory experiments and design exercises. Two in-class exams and one final exam will be prepared. No makeup exams will be given. It is in your best interest to attend all exams on the date of their delivery. Conflicts must be stated before the fact. Failure to attend an exam or to make previous arrangements results in a score of zero. Incompletes are not given out as course grades as a consequence of missing an exam, laboratory, or homework assignment. Examinations are normally closed-book, closed-notes, and closed homeworks. Single sheets of summary notes are, however, permitted.

Textbooks:

Adel S. Sedra, Kenneth C. Smith, Microelectronic Circuits, 4th Edition, Oxford University Press, 1998 (www.sedrasmith.com) SPICE, Gordon Roberts and Adel Sedra, Second Edition, 1996

Reference Books (available for the short-loan at the Information Center):

R. C. Jaeger, Microelectronic Circuit Design. New York: McGraw-Hill, 1997. R. T. Howe and C. G. Sodini, Microelectronics, Prentice Hall D. A. Neamen, Electronic Circuit Analysis and Design, New York: McGraw-Hill, 1996 M. N. Hornstein, Microelectronic circuits and devices

Homework:
Homework will consist of problems given out on a weekly basis, nominally on Wednesdays. You are encouraged to work together on the problems, but please insure that the final work handed in is your own. Homework is due at the end of class one week from the day it was handed out. Late homework is not accepted under any circumstances, since solutions to the homework will be posted on the class website immediately after the homework is handed in. Homework should be in order, stapled, and on one side of the page only for full credit. The grading of homework (as well as the exams) will emphasize the method used to arrive at the answer rather than the numerical result itself. Hence, it is most important that your work be legible, organized, and understandable. In addition, computer output, e.g. from SPICE, must be properly annotated to explain and label its key features.

Lectures:
Lecture attendance is not required, but strongly recommended since you are responsible for any material covered in class and any handouts distributed during this time.

Calculators:
An electronic hand calculator is necessary for both the exams and homeworks in this class. A programmable calculator or one that offers an equation solver function is not required, but strongly recommended. Students are responsible for knowing how to use their own calculators.

Computers and Software:

HP-VEE software will be used in the lab experiments and available on the PCs in the lab. This class will also involve computer simulation of circuits using PSPICE. This program will be available on the course web-site for downloading or you obtain the same PSPICE student version software from the OrCAD website: http://www.orcad.com. Be sure to use PSpice 9.1 student edition. This includes Pspice A/D, Capture, Schematics, and PSpice Optimizer. Only PSpice A/D and Capture will be used in this course.

Grading: Midterms: Homework: Lab: Final:

40% (2 x 20%) 10% 20% 30%

EL 202 - Circuits II Course Outline

Chapter 4 Bipolar Junction Transistors (BJTs) (2.5 weeks) Introduction 4.1 Physical Structure and Modes of Operation 4.2 Operation of the npn Transistor in the Active Mode 4.3 The pnp Transistor 4.4 Circuit Symbols and Conventions 4.5 Graphical Representation of Transistor Characteristics 4.6 Analysis of Transistor Circuits at DC 4.7 The Transistor as and Amplifier 4.8 Small-Signal Equivalent Circuit Models 4.9 Graphical Analysis 4.10 Biasing the BJT for Discrete Circuit Design 4.11 Basic Single-Stage BJT Amplifier Configurations 4.12 The Transistor as a Switch-Cutoff and Saturation 4.13 A General Large-Signal Model for the BJT: The Ebers-Moll (EM) Model 4.14 The Basic BJT Logic Inverter 4.15 Complete Static Characteristics, Internal Capacitances, and Second-Order Effects 4.16 The SPICE BJT Model and Simulation Example

Chapter 5 Field-Effect Transistors (FETs) Introduction 5.1 Structure and Physical Operation of the Enhancement-Type MOSFET 5.2 Current-Voltage Characteristics of the Enhancement MOSFET 5.3 The Deletion-Type MOSFET 5.4 MOSFET Circuits at DC 5.5 The MOSFET as an Amplifier 5.6 Biasing in MOS Amplifiers 5.7 Basic Configurations of Single-Stage IC MOS Amplifiers 5.8 The CMOS Digital Logic Inverter 5.9 The MOSFET as an Analog Switch 5.10 Internal Capacitances of the MOSFET 5.11 The Junction Field-Effect Transistor (JFET) 5.12 Gallium Arsenide (GaAs) Devices-The MESFET 5.13 The SPICE MOSFET Model and Simulation Examples

(4 weeks)

Midterm I
Chapter 6 Differential and Multistage Amplifiers Introduction 6.1 The BJT Differential Pair 6.2 Small-Signal Operation of the BJT Differential Amplifier 6.3 Other Nonideal Characteristics of the Differential Amplifier 6.4 Biasing in BJT Integrated Circuits 6.5 The BJT Differential Amplifier with Active Load 6.6 MOS Differential Amplifiers 6.7 BiCMOS Amplifiers (3 weeks)

6.8 GaAs Amplifiers 6.9 Multistage Amplifiers 6.10 SPICE Simulation Examples

Chapter 7 Frequency Response (2 weeks) Introduction 7.1 s-Domain Analysis: Poles, Zeros and Bode Plots 7.2 The Amplifier Transistor Function 7.3 Low-Frequency Response of the Common-Source Amplifiers and Common-Emitter 7.4 High- Frequency Response of the Common-Source Amplifiers and Common-Emitter 7.5 The Common-Base, Common-Gate, and Cascade Configurations 7.6 Frequency Response of the Emitter and Source Followers 7.7 The Common-Collector Common-Emitter Cascade 7.8 Frequency Response of the Differential Amplifier 7.9 SPICE Simulation Examples

Midterm II
Chapter 8 Feedback Introduction 8.1 The General Feedback Structure 8.2 Some Properties of Negative Feedback 8.3 The Four Basic Feedback Topologies 8.4 The Series-Shunt Feedback Amplifier 8.5 The Series-Series Feedback Amplifier 8.6 The Shunt-Shunt and Shunt-Series Feedback Amplifiers 8.7 Determining the Loop Gain 8.8 The Stability Problem 8.9 Effect of Feedback on the Amplifier Poles 8.10 Stability Study Using Bode Plats 8.11 Frequency Compensation 8.12 SPICE Simulation Examples (2 weeks)

Chapter 9 Output Stages and Power Amplifiers Introduction 9.1 Classification and Output Stages 9.2 Class A Output Stage 9.3 Class B Output Stage 9.4 Class AB Output Stage 9.5 Biasing the Class AB Circuit 9.6 Power BJTs 9.7 Variations on the Class AB Configuration 9.8 IC Power Amplifiers 9.9 MOS Power Transistors 9.10 SPICE Simulation Examples ------------------------- end ------------------------------------------

(. weeks)