Description The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads.

In previous MIG designs (ie - Virtex-5 DDR2), the DQS strobe was used to capture data. Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as DQS does. The MIG Vitrex-6 design uses two clocks in the data capture of a DQS byte:

Capture Clock Resynchronization Clock.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information. Solution Usage: An MMCM uses the input system clock to generate the capture clock(s) and resynchronization clock(s) using the CLKPERF output. This CLKPERF output is a low jitter clock source that goes directly from the MMCM to the I/O without using a buffer. This MMCM is located in the infrastructure.v/.vhd module in the output 'rtl/ip_top' directory. The MMCM CLKPERF output is routed to OSERDES/IODELAY elements. These IODELAY elements drive BUFIO (capture logic) and BUFR (resynchronization logic) local clock buffers to create the CPT and RSYNC clocks. The IODELAYs allow each of these clocks to be adjusted individually to provide for reliable capture of the read data eye from the memory. The RSYNC clock is used for final stage data capture in the DQ ISERDES and to transfer read data into fabric. For a view of this capture/rsync logic, see the PHY Clocking Architecture figure (Figure 1-47) in The Virtex-6 FPGA Memory Interface Solutions User Guide. For more information on this logic, see the DDR2 and DDR3 Memory Interface Solution > Core Architecture > PHY section in The Virtex-6 FPGA Memory Interface Solutions User Guide. Placement:

One resynchronization clock is used per interface per I/O column containing Data Groups. Meaning if an interface contains Data Group placement in 2 I/O columns, 2 RSYNC clocks are required. Each RSYNC clock requires an OSERDES/IODELAY and BUFR. In order to use these IODELAY and BUFR elements, a Clock Capable-P (P_SRCC or P_MRCC) site must be prohibited and logic within the prohibited site locked for capture logic usage

Constraints: The MIG output locks the required number of CCIO pins and associated IODELAY and OSERDES sites for the interface generated. These LOCs are contained in the output User Constraints File (design.ucf). Here is an example rsync logic placement: CONFIG PROHIBIT = A20; INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X1Y143"; INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X1Y143"; INST "u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X1Y7"; By default, MIG uses Single Region Clock Capable I/O (P_SRCC) sites because all of the related logic data group logic exists within the same bank. Multi-Region P_CCIO sites may also be used. If it is desired to move the Capture Logic prohibits and site LOCs, users should modify the sites within the output UCF and run the updated UCF through the Verify UCF and Update UCF and Design tool. For more information, see(Xilinx Answer 34386). Related Information: While the design does not capture data using DQS, it does monitor the phase of DQS during reads to account for any phase shift due to voltage/temperature changes. If the phase varies, the capture clock phase is adjusted using the MMCM Phase Shift.

(Xilinx Answer 35123) MIG Virtex-6 DDR2/DDR3 - Phase Detector

Because DQS is not used to capture data, it only needs to be placed on ap/n I/O pair rather then a Clock Capable I/O (CCIO) pair.

(Xilinx Answer 34543) MIG Virtex-6 DDR2/DDR3 - DQS placement rules

For more information on the capture logic, please see:

(Xilinx Answer 34477) MIG Virtex-6 DDR2/DDR3 - Capture Logic Usage and Placement

Description The MIG Virtex-6 DDR2/DDR3 design uses an internally generated clock to capture the data on DQ during reads. In previous MIG designs (i.e., Virtex-5 DDR2), the DQS strobe was used to capture data. Capturing data with an internally generated clock is beneficial because it is a true free-running clock and has no pre-/post-amble glitches as DQS does. The MIG Vitrex-6 design uses two clocks in the data capture of a DQS byte- Capture Clock and Resynchronization Clock. NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information. Solution An MMCM uses the input system clock to generate the capture clock(s) and resynchronization clock(s) using the CLKPERF output. This CLKPERF output is a low jitter clock source that goes directly from the MMCM to the I/O without using a buffer. This MMCM is located in the infrastructure.v/.vhd module in the output 'rtl/ip_top' directory. The MMCM CLKPERF output is routed to OSERDES/IODELAY elements.These IODELAY elements drive BUFIO (capture logic) and BUFR (resynchronization logic) local clock buffers to create the CPT and RSYNC clocks. The IODELAYs allow each of these clocks to be adjusted individually to provide for reliable capture of the read data eye from the memory. For a view of this capture/rsync logic, see the PHY Clocking Architecture figure (Figure 1-47) in the Virtex-6 FPGA Memory Interface Solutions User Guide. For more information on this logic, see the DDR2 and DDR3 Memory Interface Solution > Core Architecture > PHY section in the Virtex-6 FPGA Memory Interface Solutions User Guide. Placement: (Xilinx Answer 34477) - Capture Logic Placement (Xilinx Answer 34540) - RSYNC Logic Placement Description The Virtex-6 DDR2/DDR3 MIG design has two clock inputs, the reference clock and the system clock input. The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks (used in the user interface, controller and the PHY layers). NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information. Solution Reference Clock (clk_ref): The IDELAYCTRL reference clock is routed directly to the IODELAY_CTRL primitive instantiated in the top level module. The clk_ref input should be driven by either a 200 MHz or 300 MHz input clock. The reference clock speed affects the tap size and impacts the effective window over which a signal can be shifted with the IODELAY. It is important to be able to shift a signal over an entire clock period. See the (Xilinx Answer 35252) for more details and when the MIG design uses a 200MHz reference clock versus a 300MHz reference clock. System Clock (sys_clk): MIG assumes that the input system clock is the same as the interface frequency. That is, if you specify a 400 MHz memory interface, the design is setup for a 400 MHz input clock. The 400 MHz system clock is fed into an MMCM (located in the infrastructure.v/.vhd module) to create the required MIG clocks:

0.5x (1/2 rate) BUFG clock used to drive User Interface, Controller, and PHY CLB logic 1x BUFG clock used to drive I/O Logic for the DRAM Clocks, Controller, Address, DM, and DQ/DQS 1x Performance Path Clock (CLKPERF) used to create the capture and resynchronization clocks in the read path

For a picture of the clocking scheme, see the PHY Clocking Architecture figure located in the DDR2/DDR3 SDRAM Memory Interface Solutions > Core Architecture > PHY section of UG406. The Virtex-6 DDR2/DDR3 MIG design is a half rate controller, meaning the controller runs at half the rate of memory interface. This makes it easier to meet timing internally for high speed memory interfaces, and makes the data bus 4 times the DQ width to account for rising and falling data. Using a different input clock rate: MIG assumes the main system clock input is the same rate as the DRAM interface. If you want to use a different input clock rate, you must make changes to the source code to modify the MMCM settings in the MIG design. The MMCM multiply and divide parameters are set in the top level wrapper file (example_top.v/vhd for the example design folder or design_name.v/vhd for the user design folder): parameter CLKFBOUT_MULT_F = 8, parameter DIVCLK_DIVIDE = 4, parameter CLKOUT_DIVIDE = 2,

These are set to create the above MMCM output clocks based on the MMCM input clock. MIG assigns the memory clock frequency to the top-level tCK parameter. This tCK parameter is used to create the input clock (CLKIN1_PERIOD) frequency of the MMCM. It is also used to create counters within the controller design (for example, the refresh counter). Because this parameter is used to create the counters, it cannot be modified to the new input clock period. A new parameter must be created to assign the input clock period to. Once the new parameter is created, it should be used to drive the input clock (CLKIN1_PERIOD) of the MMCM. The MMCM is instantiated in the MIG provided infrastructure.v/.vhd module. The top-level of both the user_design and the example_design instantiate the infrastructure. The Virtex-6 Clocking Wizard can be used to determine the appropriate MMCM M and D values based on the input frequency and required MIG MMCM output clocks (see above). NOTE: To minimize jitter, MIG requires the M (CLKFBOUT_MULT_F) not exceed 8 while keeping the VCO Frequency at or above 1 GHZ. Calculating Proper VCO Frequency: VCO frequency = 1/((DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK)) Additional information: (Xilinx Answer 35113) - Usage of DQS (Xilinx Answer 35112) - Internally generated capture clock