RESUME K Chandran Email: chandran.vlsi@gmail.

com Phone: +91-7204157666 Summary To pursue a challenging and exciting career in the field of VLSI, thereby acquiring knowledge and work towards organizational and personal growth. Enthusiastic about learning and developing Professional Skills in a growth oriented environment. Excellent Communication and documentation skill is an added plus. Academics Pursued doctoral program in Ocean system engineering in Jeju national University South Koera (2010-2011). Degree Master of Engineering in VLSI Design Certificate course on VLSI Layout Design Bachelor of Engineering in Electronics and Communication Skill set Programming Languages Knowledge Hardware Description Languages Operating System Simulation tools used CAD Tools : C, ,Matlab : Device Drivers : Verilog, System Verilog. : Windows, Linux : Modelsim, Xilinx ISE : Cadence Design Suite SOC Encounter XL Virtuoso XL Layout Editor Assura DRC/LVS/RCX Celtic X-talk analysis School Anna University, Coimbatore, India University of California Extension, Santa Cruz SSM College of Engineering, India Duration 2008-2010 2006-2007 2001-2005 Percentage 82% 78% 61%

Experience Maven Silicon Doctoral program Master of engineering Good Will Systems TIIT Bangalore Suthernland : Duration (Nov 11 to July 12) : Duration (March11 to Sept 11) : Duration (Sept08 to Nov 11) : Duration (Aug 07 to Sept 08) : Duration ( July 06 to Aug 07) : Duration (Aug 05 to July 06 )

Projects Title Language used Tools : SPI Controller Core - RTL Design : Verilog : Modelsim 5.7, Xilinx 9.2

Description: The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock. This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register. The SPI Core RTL is technology independent and fully synthesizable. Architected the class based verification environment using system Verilog. Verified the RTL module using System Verilog. Generated functional and code coverage for the RTL verification sign-off.

Title ( Phd) Tool Role

: Footstep Classification of the Person Movement using Seismic Sensor : Matlab : Proposed an algorithm to find the footstep classification of person movement using seismic sensor

Title Language used Tools Role

: Low Power Delay Buffer Using DET FF and C-element Gated Driver Tree Technique : Verilog : Modelsim 5.7, Xilinx 9.2 : Design and implement low power delay buffer using DET and Celement

Title Language used Tools Role

: Low Power Receiver for OFDM-Based WLAN Systems : VHDL : Modelsim 5.7, Xilinx 9.2 : Design and Implementation of Synchronizer and Channel Estimator in WLAN System

Title Technology Gate Count Macros No. of Clocks Role

: PCI Express (Full Chip) : 130nm, : 128K Gates : 12 : 4 : Floor/Power planning using First Encounter, P&R Using Nanoroute Ultra and Timing Analysis using CTE.

Title Description

: Interactive Voice Response System : This project is to develop a Telephone based IVRS (Interactive Voice Response System) using Embedded Technology.

Personal Memorandum Name Date of Birth Marital Status Sex Nationality Language Known Fathers Name Chandran K. 12.09.83 Single Male Indian Tamil, English Sadayan Kanagarajan C-27/37 Mohan Nagar Salem Steel Plant Permanent Address Salem-636030 Tamil Nadu, INDIA e-mail Address Contact Details chandran.vlsi@gmail.com +91-7204157666

Declaration I here by declare that the above mentioned information is true to the best of my knowledge and belief. Kanagarajan Chandran