SIP Substrates Drive Continued Miniaturization

The emergence of SIPs (System-inPackage) is being hailed as the longawaited renaissance of multichip module (MCM) technology. The growth of SIP technology is being made possible by the availability of low-cost, high-quality substrates. This article reviews substrate selection and use.

By Dr. Mohammed S. Sabuktagin, John Hunt and Dr. Pramod C. Karulkar, University of Alaska, Fairbanks, [uaf.edu]

he increasingly attractive features of portable electronic gadgetssold at ever decreasing prices and weightshave made them an irresistable part of our daily life (Figure 1). These trends in portable electronics are made possible by the advances in electronic miniaturization on two fronts, ICs and IC packaging technologies. Continued advances in miniaturization are necessary to meet the cost, weight, size, performance and reliability

Figure 2. This 8-level memory stack was fabricated at the Office of Electronic Miniaturization, University of Alaska, Fairbanks.

requirements of future generation electronics in diverse consumer, commercial, industrial as well as defense and aerospace applications. While in principle, extreme miniaturization can be accomplished through single chip ASICs, this technology is prohibitively expensive, time consum-

ing, and difficult. Optimization for the desired functionality (e.g., RF and digital on the same chip) is not a trivial task.

Affordable
SIP design iterations are very affordable compared to ASIC iterations. They also offer the best compromise by allowing the integration of a number of components that are in a packaged or known good die (KGD) form in the densest possible way without missing the market window or risking a fortune. Numerous innovative design and fabrication approaches have been used to realize SIPs.1, 2, 3 For example, one of the enabling technologies in Cingulars latest 2.5 oz tri-band world phone (Pantech C300) is an RF SIP.4 Figure 2 shows the image of an 8-level memory stack fabricated at the Office of Electronic Miniaturization, University of Alaska, Fairbanks (OEM-UAF).5

Extendible Technology
Figure 1. Key trends in portable electronics are demonstrated by the growing use of SIPs in cellular phones (Nokia).

Currently we are working on a 32-level memory stack that would be only about
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Figure 3. This is a cross-section of a representative SIP substrate. Drawing is not to scale.

1.2cm high. This technology can be extended to combine analog, RF, logic and optoelectronics functions into single 3D stacks. A SIP, which is basically an MCM and can be defined as: a single package substrate with two or more chips mounted to it and encapsulated with mold compound, a high-density ceramic, organic or other rigid material with multiple chips mounted on it constituting a multichip processor and memory system, a small circuit board assembled with many chips and discrete components that becomes the system board for an end product.

Gold may be used in special applications, such as space systems, and in the final layer for forming the external connections. The versatility of microvia technology enables interconnection between any two or more layers through blind, stacked and buried vias (diameter < 150 m) leaving more space for signal routing. The need for high-density signal routing in a SIP system is met by a combination of fine lines and microvias in the build-up layers. Power and signal integrity demands are supplied by introducing entire layers that form power and ground planes. Increasingly, passive components are being integrated into SIP substrates.

Figure 4. Fabrication of SiP substrate by sequential build-up: a. Lamination/coating of a build-up layer onto the core, b. Via formation c. Metallization and circuitization

Substrate Development
An approach to assembling two or more chips (KGD) on a single interconnect substrate known as an MCM has been used for more than two decades. At the time, MCM technology was expensive due to the high costs of complex fabrication steps and ceramic substrates. Many people expected that costs would drop with an increase of demand which never happened. On the other hand, to meet the needs of increasing complexity of electronic systems cost effectively, novel fineline and microvia processes were introduced in traditional PWB fabrication methods. Surface Laminar Circuit (SLC) packaging was developed at IBM Yasu, Japan, during the late 80s7 with a photoimageable solder resist from CibaGeigy used as the build-up layer material. SLCs containing multiple chips came to be known as MCM-Ls for laminated MCMs. SLCs were also used for packaging high pincount ICs. Another well known high-density substrate ALIVH (Any Layer Interstitial Via Hole) was developed by Matsushita during the early 90s. In this approach, a CO2 laser was used to form vias (200m diameter) in Aramid.
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SIP Substrates
The key component of a SIP is the lowcost, high-density substrate. Figure 3 shows a schematic of the cross-section of a representative substrate. The layers at the center are called the core layers, which can be traditional FR4 laminates. The thinner top layers are microvia materials such as Polyimide or BCB, which are sequentially laminated to, or coated on the core. Hence these layers are called the build-up layers and a SIP substrate is known as a build-up substrate. The substrate in Figure 3 is referred to as a 3/2/3 substrate because it has 3 build-up interconnect layers on each side of a 2-interconnect layer core. Copper (5 to 20m thick, 12 to 50m wide) with a thin adhesion layer (Cr, Ti etc.) is used for the interconnect lines.

The latest version of this substrate, ALIVH-FB8, employs thin polyimide films (12.5m) as the build-up layer material. Features of ALIVH-FB include 25/25 m line/space, 50m-diameter laser-drilled vias and up to 8 build-up layers. ALIVH substrates have been used for CSPs and MCM-Ls. A SIP substrate is structurally similar to a high-end MCM-L or IC substrate. However. it is more than an IC substrate in the way that it ensures interconnection between all the chips of the SIP. It is more than a MCM-L substrate, as well, because it fully incorporates a complex functionality.

Material Properties
The desirable material properties of SIP substrates include low dielectric constant and loss, ease of forming uniform thin films, CTE matching to Si, good adhesion, good thermal conduction, ease of multilayer and microvia formation, compatibility with fabrication processes. A number of properties that determine reliability, such as moisture absorption, stability and immunity to the applications environment are also important.
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Table 1. SIP Substrate Materials

Vendor and Website Brand Dow [dow.com] Cyclotene Material BCB Polyimide BT Polyimide Minimum Thickness (m) Spincoatable 12.5 38 25 50 7.5 Dielectric Constant 2.65 (10GHz) 4 (1KHz) 2.65 (40GHz) 3 (1MHz) 3.8 (1GHz) 3.5 (?) Dielectric Loss 0.002 (10GHz) 0.005 (1KHz) 0.004 (40GHz) 0.02 (1MHz) 0.014 (1GHz) 0.0013 (?)

Dupont Kapton [dupont.com] Gore [gore.com]

Figure 5. Fabrication of SiP substrate by single lamination. a. Via formation b. Metallization and circuitization c. Lamination

Microlam

Nippon Espanex [nscc.co.jp]

Park N5000 BT Electrochemical [parkelectro.com] UBE Upilex [northamerica.ube.com] Polyimide

Table 1 lists the key properties of commonly used SIP substrate materials, as well as their vendors. SIP substrates based on thin (<25 m) polyimide films are widely used due to their ease of processing, availability, and the existence of a large technical data base. The recent introduction of adhesives in sheet form have made the formation of multilayer structuresincluding the build-up layerseasy and less expensive than in the past. Liquid crystal polymer films have been considered because of their very low dissipation factor and moisture resistance. Thinner versions of traditional PWB materials are also available.

Fabrication Processes
Build-Up Layer Coating/Lamination The fabrication process (shown in Figure 4), for a build-up substrate begins with a core which acts as the base of the substrate. Build-up dielectric layers are laminated or spin-coated to the core one layer at a time, as shown in Figure 4a. Microvia Formation The method of microvia formation depends on the nature of the build-up layer, shown in Figure 4b. With photoimageable build-up layers (such as Cyclotene, SU-8 or Probimer), all vias are formed simultaneously by photolithography. One needs SIP-specific photomasks, exposure and develop equipment and a photo darkroom.

Some materials (polyimide and Aramid) are suitable for plasma etching, which is also a simultaneous process, but requires more equipment. Laser ablation is the most popular method of microvia formation due to its simplicity, minimum equipment need and its applicability to most organic dielectrics. CO2 (9.2-9.6m) and UV (355nm, Nd:YAG lasers, for example) are commonly used for laser ablation.9 A desmear step is necessary to clean residues from the bottom of the via hole after CO2 laser ablation. These residues result from the vertical standing wave interference patterns of the laser in the via Such residues are rarely seen in UV laser ablation, because the interference effects are mitigated by the shorter wavelength of the laser. Vias as small as 25-30m in diameter can be drilled using a UV laser, which is not possible with CO2 lasers due to their longer wavelength and shorter depth of focus. Average power, hence throughput is higher for CO2 lasers. The disadvantage of via drilling by laser ablation is its serial nature.

thick seed layer of Cu on the surface of the build-up dielectric and the sidewalls of the microvias, as shown in Figure 4c. This deposition is followed by the definition of circuit features using a process called patterned plating. In this process, a thick layer of Cu is deposited by electroplating only in the circuit pattern defined by photolithography. Circuit patterns are finalized by photoresist stripping and a shallow Cu etch to remove the thin-seed Cu layer from the areas that were under photoresist protection. Subtractive Process If a thick Cu foil has already been laminated to the build-up layer insulator, circuit features have to be defined by subtraction, as in the case of traditional PWB processing. Since the features of a SIP substrate are finer than a traditional PWB, however, repeated photolithography and Cu etching steps are necessary to avoid sidewall etching during fineline formation. The availability of low-cost and reliable thin Cu foils would make it easier to form fineline interconnects by subtractive processes. Currently, Cu foils thinner than 5m are available.

Metallization/Circuitization
Additive Process Electroless or direct plating is used to deposit a few hundred nanometersI

Single Lamination
The disadvantage of the SBU process described above is the yield loss due to
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Table 2. Commercial SIP Substrates

Vendor and Website 3M [3m.com] Core Polyimide, Cu Build Up Polyimide, Microlam BT ABF, GX Polyimide Thickness (m) 190 (4 layers) 330 (4 layers) 300 (4 layers) 220 (6 layers) Line/ Space (m) 62/62 50/50 15/15 20/20 Via/ Land (m) 50/? 125/270 50/? 50/90

Daisho-Denshi BT [daisho-denshi.co.jp] Kyocera FR4 [kyocera-slc.co.jp]

Figure 6. Cross-sectional SEM image of a 1/2/1 SIP substrate. (Compass Technology)

Toppan [3m.com]

Polyimide

compounding of defects in successive process steps. This process limits the total number of build-up layers to about 6.10 The alternative approach is to circuitize each layer individually, and laminate them in one step, as shown in Figure 5. The availability of low-cost thin dielectric materials and sheet adhesives is making this approach increasingly attractive. There are, however, a number of limitations to this process such as difficulty in handling very thin films, layer-tolayer alignment and subsequent limits on the minimum feature size.

Generally, to learn substrate costs requires a SIP designer to send the design to a vendor for detailed assessment, which can be time consuming.

8. D. Andoh, Y. Tomita, T. Nakamura and F. Echigo, The Progress of the ALIVH Substrate, Proc. ECTC 2002, pp. 1419-1424. 9. Y. Sun, C. Dunsky, H. Matsumoto and G. Simenson, Microvia Formation with Lasers, Proc. SPIE 2002, pp. 241- 252. 10. Blackshear, et al., op cit.

Conclusion
As miniaturization and performance enhancements through single-chip solutions become increasingly difficult, the heat is now on the packaging sector to meet future miniaturization needs costeffectively. With innovative materials and fabrication processes, commercial substrate technologies are poised to take on the challenges. i

References Commercial Substrates

Table 2 lists the main features of some of the most advanced commercially available SIP substrates demonstrating that a substrates core and build-up layer materials can chosen from a number of options. Very thin flexible substrates based on polyimide films are available from a number of vendors. Figure 6 shows the cross-sectional SEM image of a 1/2/1 polyimide substrate from Compass Technology. Commonly available SIP technologies are not the finest in terms of line/space and via dimensions, as well as in layer thicknesses. Aggressive technologies are under development by a number of vendors, but information about them has to be obtained on a case-by-case basis.
1. M. Karnezos, F. Carson and R. Pendse, 3D Packaging Promises Performance, Reliability Gains with Small Footprints and Lower Profiles, Chip Scale Review, January-February 2005, p. 29. 2. D. Mathews and M. Gaynor, RF System-inPackage: Tradeoffs Govern the Cost, Size and Performance Equation, Chip Scale Review, July 2003, p. 55. 3. http://www.tessera.com, http://www.irvine-sensors.com/ 4. http://www.skyworksinc.com/ 5. http://www.silicontundra.org/ 6. K. Brown, The Rebirth of SIP, Proc. IEEE 2004 Custom Integrated Circuits Conference, 2004, pp. 681-686. 7. E. Blackshear, M. Cases, et al., The Evolution of Build-Up Package Technology and Its Design Challenges, IBM Journal of Res. & Dev., V. 49, July/September 2005, pp. 641-661.

Mr. Sabuktagin is a research associate in the Universitys Office of Electronic Miniaturization (OEM). He earned his doctorate in electrical engineering from Virginia Commonwealth University. [ffmss1@uaf.edu] Mr. Hunt is a senior microelectronics packaging engineer at the OEM. He holds a degree in applied science from the DeVry Institute of Technology. [fnjmh@uaf.edu] Dr. Karulkar is director and Presidents Professor, OEM. Prior to joining UAF, Dr. Karulkar headed (1993 to 2004) the Microelectronics Division of the University Research Foundation, Greenbelt, Maryland. He received his doctorate in materials science and engineering from the University of Wisconsin, Madison. [p.karulkar@uaf.edu]

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