An Investigation of Voltage Balancing Circuit for DC Capacitors in Diode-Clamped Multilevel Inverters to Realize High Output Power Density Converters

Takumi Ito1
Student Member

Masamu Kamaga1
Student Member

Yukihiko Sato1
Member Chiba University 1-33 Yayoi-cho, Inage-ku, Chiba, 263-8522, Japan tito@graduate.chiba-u.jp mkamaga@gmail.com ysato@faculty.chiba-u.jp
Abstract -- Output power density of power converters has been increasing. At the same time, the power converters with lower harmonics and lower electromagnetic interference are required in many applications. To satisfy these requirements, the volume of filters and heat sinks should be reduced. As a solution to realize higher output power density and lower harmonics, diode-clamped multilevel inverters are investigated. In this case, the voltage balancing circuit must be connected to the DC capacitors because the DC voltages tend to unbalance when the number of the output level exceeds three. Therefore, the total volume of the converters including the voltage balancing circuit should be investigated. In this paper, resonant switched capacitor converter is treated as a promising solution to realize the voltage balancing circuit with smaller volume. The operating characteristics and estimated volume are clarified analytically. Finally, the applicability of the voltage balancing circuit is confirmed by the experimental results. Index Terms--power converter, output power density, diodeclamped multilevel inverter, voltage balancing circuit, resonant switched capacitor converter
1 2

Hiromichi Ohashi2
Member National Institute of Advanced Industrial Science and Technology 1-1-1 Umezono, Tsukuba, 305-8568, Japan h.oohashi@aist.go.jp

I.

INTRODUCTION

Output power density of power converters has been one of the important criteria [1]. At the same time, the reduction of harmonics and electromagnetic interference (EMI) caused by the power converters are strongly required in many applications. Especially, in some applications such as photovoltaic inverters, fuel cell inverters, and uninterruptible power supplies, high-quality output voltage waveforms are required from the viewpoint of power quality [2] [3]. In addition, in motor drive applications, high-quality output waveforms are required to reduce motor loss, voltage surges, and bearing leakage currents [4] [5]. To satisfy these requirements, bulky LC filters and EMI filters are usually connected. The volume of the LC filter can be reduced by increasing switching frequency of the converters. However,

the higher switching frequency may cause the larger switching loss and severer EMI. The increase of the switching loss enlarges the required volume of the heat sinks. In this context, the volume of the filters and the heat sinks is a critical barrier to realize high output power density converters [1]. As another approach to reduce the harmonics and EMI, several types of multilevel converters are investigated actively; a diode-clamped converter, a flying capacitor converter, a cascaded converter, and so on [6]. In this case, the harmonics can be reduced because the change of each switching voltage is reduced. The switching loss can be also reduced because the voltage applied to each switching device is reduced. Therefore, the volume of the filters and heat sinks can be reduced. It has been shown that higher efficiency and higher output power density can be realized by the integration of a multilevel converter [7]. Above all, according to [8], it has been also shown that the total volume of the converters can be reduced by introducing diode-clamped multilevel inverters. In this topology, the input DC voltage is divided by series-connected DC capacitors to obtain multilevel DC voltage sources. So far, 3-level diode-clamped inverters have already been put into practical use in medium voltage applications [9]. For the extreme reduction in the volume of the converters, the multilevel converters with a larger number of levels are required. In the case of the diode-clamped inverters with more than 4-level, the voltage balance of each DC capacitor cannot be maintained without additional balancing control, because the charge flowing from the individual capacitors are not equal in each cycle [10]. Because the voltage deviation causes larger harmonics in the output voltage and over-voltage across the switching devices, voltage balancing circuits are indispensable for the DC capacitors in the diode-clamped

978-1-4244-5287-3/10/$26.00 2010 IEEE

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multilevel inverters. Several methods for the voltage balance of the DC capacitors are proposed and investigated; a backto-back converter [11], a buck-boost converter [12], a multilevel boost converter [13], and so on. However, these methods may increase the volume of the converter and have a disadvantage in realization of converters with higher output power density. To solve these problems, a method based on a resonant switched capacitors (RSCC) [14] has been proposed and its applicability has been confirmed as a promising topology [15]. However, the voltage balancing circuit based on RSCC with a feed back control has been investigated only for the 5-level diode-clamped inverter. As the number of level increases, it is concerned that the system of the voltage balancing circuit may become more complex and bulky. Thus, the authors proposed the voltage balancing circuit based on RSCC operated by an open-loop control for diode-clamped multilevel inverters [16] [17]. This paper shows the applicability of the voltage balancing circuit based on the RSCC for the diode-clamped multilevel inverters with a larger number of level by the investigations of the operating characteristics and the volume. Furthermore, the applicability of the voltage balancing circuit is confirmed by some experiments employing a prototype 9-level diodeclamped inverter. II. A. VOLTAGE BALANCING CIRCUIT BASED ON RSCC

ir Lr V vr Cr

S C1 Sp S C2 Sp VC2 ip VC1

Fig.1. Circuit configuration of RSCC State I State II S Sp ir ip vr t Fig.2. Switching pattern and waveforms ON OFF OFF ON ON OFF OFF ON

Operating Principle of RSCC Fig.1 shows the circuit configuration of a unit of the RSCC. The unit of RSCC consists of four switching devices, a resonant inductor Lr, and a resonant capacitor Cr. Each switching device is operated at a 50% duty factor and the resonant frequency determined by Lr and Cr as shown in Fig.2. Under the condition of (VC1>VC2), Cr is charged by C1 when two switches denoted by S are in the on-state (State I). Then, C2 is charged by Cr when switches Sp are in the onstate (State II). Thus, the voltages of the DC capacitors can be balanced by repeating this switching operation. VC1 and VC2 can balance without any feedback control by changing the amplitude and direction of ir automatically. However, the voltage deviation of the DC capacitors remains because of the resistances of the switching devices, Lr, and Cr. On the other hand, the switching loss cannot be a problem because RSCC is operated under zero current switching. Thus, the volume of Lr and Cr can be reduced by introducing a higher switching frequency operation without the increase of the switching loss. B. Application of RSCC to Diode-Clamped Multilevel Inverter The RSCC can be adopted as the voltage balancing circuit for the series-connected DC capacitors of the diode-clamped multilevel inverters as shown in Fig.3 for generalized case [18]. Even when the number of level increases, the DC voltages can be balanced by the switching pattern as shown in Fig.2. As mentioned in the previous section, each voltage

S ir1 Lr vr1 V irj-1 Lr vrj-1 Cr Neutral Point irj Lr vrj V ir2j-2 Lr vr2j-2 Cr Cr Sp S Sp S Cr Sp S Sp

C1

VC1

C2

VC2

Diode-Clamped Multilevel Inverter

Cj

VCj

Cj+1 Sp Cj+2 Sp

VCj+1

VCj+2

Sp S Sp C2j VC2j

Fig.3. Voltage balancing circuit based on RSCC

deviation between two adjacent DC capacitors remains. As a result, the significant voltage deviation between VC1 and VCj remains. The voltage deviation may cause larger harmonics

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in the output voltage and over voltage across the switching devices. On the other hand, because the increase of the number of level increases the number of the components of the RSCC such as Lr and Cr, consequently the volume of the RSCC may become large. Therefore, the voltage deviation of the DC capacitors and their volume should be investigated in the practical applications of the voltage balancing circuit based on RSCC. III. ANALYSIS OF OPERATION OF RSCC CONNECTED TO DIODE-CLAMPED MULTILEVEL INVERTER Analysis Method of RSCC Fig.4(a) and (b) show the current loops of the voltage balancing circuit in State I and State II of Fig.2, respectively. Based on the circuit equations derived from Fig.4, the behavior of the circuit can be analyzed by the approximate analytical method. In Fig.4, Rr is the total resistance of Lr and Cr. Ron is on-resistance of the switching devices. n is the number of level of the diode-clamped multilevel inverter. Capacitances of DC capacitors C1~C2j are assumed to be sufficiently larger than Cr. Initial currents of ir1~ir2j-2 are zero in the beginning of State I and State II in each switching period. Initial voltages of vr1~vr2j-2 in State I and State II are equal in each half cycle. The value j is equal to (n-1)/2. The currents flowing from each node between two DC capacitors are pulsed waveforms in diode-clamped multilevel inverter. For simplified investigation, these currents are regarded as the average values. Then, each average current is given by 3 2 I d m(n 1) 1 2k 2(k 1) sin 1 Ik = sin 4 m(n 1) m(n 1) A.

2k 2(k + 1) 2(k + 1) m , = 1. n 1 n 1 m(n 1) 2(k + 1) , I k is applied directly. If m n 1 In (1), average current flowing from each node between the DC capacitors is affected by the modulation index m. Then, the voltage deviation of DC capacitors, the maximum value of each resonant currents and voltages are investigated corresponding to the value of the modulation index m because the operating characteristics depend on the modulation index m. These values are important parameters in the design of the RSCC. As for the estimation of the volume of the balancing circuit, the maximum stored energy of the resonant inductors and capacitors is investigated, because the volume of an inductor and a capacitor is mostly proportional to the maximum stored energy. Here, the voltage deviation of the DC capacitors is defined as (VC1-VCj). In this investigation, a 3.0kVA diode-clamped multilevel inverter is treated. The load of the inverters is assumed as a 1.5kW induction motor. And, the power factor is assumed 0.8. The on-resistance Ron of each switching device is assumed as Ron=Ron2/(n-1) because it can be assumed to be proportional to the voltage rating and inversely proportional to the number of level of the multilevel converters. Ron2 is the on-resistance in a 2-level converter. Table 1 summarizes the parameters for the analysis. If
Ron ir1 Rr vr1 Lr Cr Ron VC1 vr1 ir1 Rr Lr Cr Ron VC2 Ron

2k 2(k 1) k2 k 1 + 1 1 2 m(n 1) 2 m(n 1)

2

m(n 1) 1 2(k + 1) 2k sin 1 sin 4 m(n 1) m(n 1)

Ron irj-1 Rr Lr Cr Ron VCj-1 vrj-1 irj-1 Rr

Ron

2k 2(k + 1) k +1 k +3 1 1 (1) + 2 2 m(n 1) m(n 1) where, Id is an rms value of the active load current in the inverter, m is a modulation index, and k is k-th node in the upper or lower half leg from the neutral point. From (1), the following results can be obtained. 2(k 1) , I k is equal to zero. If m n 1 2(k 1) 2k If m , the 4th, 5th and 6th terms in the n 1 n 1 2k =1. square bracket of (1) are equal to zero, and m(n 1)
2 2

vrj-1

Lr Cr Ron

VCj

(a) State I (b) State II Fig.4. Current loops of voltage balancing circuit based on RSCC Table 1. Parameters of for the analysis 300V Supply voltage 2V Rated load current Il 7A On-resistance Ron2 0.07 Series resistance Rr 0.1

Voltage Deviation of DC Capacitors Fig.5 shows the analytical results of the voltage deviation of the DC capacitors. As the number of level increases, the voltage deviation increases. In this case, the change in the resonant frequency did not affect the voltage deviation

B.

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Maximum value of Resonant voltage (V)

significantly. In addition, the voltage deviation can be reduced by increasing the value of Lr/Cr. However, as the value of Lr/Cr increases, the value of Lr/Cr does not affect the voltage deviation significantly. The rated voltage of each switching device should be determined based on the consideration of the voltage deviation in the voltage balancing circuit based on RSCC.
25 Voltage deviation (V) 20 15 10 5 9 13 11 15 Number of level Fig.5. Analytical results of the voltage deviation 5 7 15 Maximum value of resonant current (A) 0 Lr/Cr =0.01 Lr/Cr =0.1 Lr/Cr =1

100 80 60 40 20 0 10
-2

vr1 10-1 Lr/Cr (a) 5-level 100

60 Maximum value of Resonant voltage (V) 50 40 30 20 10 0 10-2 vr1 vr2 vr3 100

10-1 Lr/Cr (b) 9-level

10 Maximum value of resonant voltage (V)

60 50 40 30 20 10 0 10-2 vr1 vr4 vr2 vr5 vr3

5 ir1 0 10-2 10-1 Lr/Cr (a) 5-level 100

25 Maximum value of resonant current (A) 20 15 10 5 0 10-2 ir1 ir2 ir3 100

10-1 100 Lr/Cr (c) 13-level Fig.7. Maximum value of each resonant voltage

10-1 Lr/Cr (b) 9-level

40 Maximum value of resonant current (A) 30 20 10 0 ir1 ir4 10-2 ir2 ir5 ir3

10-1 100 Lr/Cr (c) 13-level Fig.6. Maximum value of each resonant current

Effect of Parameters of Inductors and Capacitors Fig.6 shows the analytical results of the maximum resonant currents. As the number of level increases, the maximum value of the resonant currents increases, and the current capacity of the voltage balancing circuit increases significantly. In addition, as the value of Lr/Cr increases, the maximum value of each resonant current decreases. However, the rated currents of the balancing circuit need to be larger than that of the main circuit of the inverter. Fig.7 shows the analytical results of the maximum resonant voltages. As the number of level increases, the maximum value of the resonant voltages decreases. Thus, the rated voltage of each resonant capacitor is reduced by increasing the number of level. In addition, the resonant voltages can be reduced by decreasing the value of Lr/Cr. Volume of Voltage Balancing Circuit The volume of the voltage balancing circuit can be estimated from the maximum stored energy of the resonant D.

C.

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inductors and capacitors as shown in Fig.8. fr is the resonant frequency of the voltage balancing circuit. The volume of them is estimated based on the ratio of volume per stored energy as follows; Lr: 15cc/mJ and Cr: 0.02cc/mJ. These values are obtained statistically from technical datasheets of choke coils and laminated ceramic capacitors [19] [20]. In Fig.8, as the number of level increases, the volume of the voltage balancing circuit increases. However, the volume of the voltage balancing circuit can be reduced by higher resonant frequency and the decrease of the value of Lr/Cr as mentioned before.
103 Volume (cc) 102 101 100

MOSFETs and diodes are excluded.

Multilevel inverter DC V AC Fig.9. Circuit configuration of LC filter 400 Volume (cc) 300 200 100 0 2-level vin LC filter L C R vout

Lr/Cr=0.01 Lr/Cr=0.1 Lr/Cr=1 5 7 9 11 Number of level (a) fr=15kHz 13 15

7 9 11 Number of level

13

15

Fig.10. Volume of the LC filter

A.

103 Volume (cc) 102 101 100

Lr/Cr=0.01 Lr/Cr=0.1 Lr/Cr=1

9 11 Number of level (b) fr=45kHz

13

15

103 Volume (cc) 102 101

0

Lr/Cr=0.01 Lr/Cr=0.1 Lr/Cr=1

LC Filter Fig.9 shows the circuit configuration of the LC filter. The inductance and capacitance in the circuit are determined to satisfy 5% THD in vout. vin is the multilevel voltage, the fundamental frequency is 50Hz, and the switching frequency is 10kHz. The input DC voltage V is 300V, and the load resistance R is 15. These values are determined by simulation software PSIM. The volume of the voltage balancing circuit can be estimated from the maximum stored energy of the resonant inductors and capacitors. The volume of them is estimated with the ratio of volume per stored energy from technical datasheets of toroidal coils and laminated ceramic capacitors [20] [21] as follows; Lr: 2.3cc/mJ and Cr: 0.02cc/mJ. Fig.10 shows the volume of the LC filter. As the number of level increases, the volume of LC filter can be reduced because of the decrease in the dominant harmonic voltages by increasing the number of level. Heat Sink The losses of the switching devices in the voltage balancing circuit and the main circuit of the inverter are calculated, and the volume of the heat sink is estimated. The losses mainly include switching loss, conduction loss of MOSFETs and clamping-diodes, and turn-off loss of antiparallel diodes. Fig.11 shows the calculated loss of the main circuit of the inverter under the condition that the DClink voltage is 300V, and the rated load current is 7A. As the number of level increases, the losses can be reduced in the inverter. Only conduction loss of MOSFETs is investigated in the voltage balancing circuit because the RSCC is operated ideally under zero current switching condition. In addition, the losses of the resonant inductors and capacitors are B.

10

9 11 Number of level (c) fr=100kHz

13

15

Fig.8. Volume of the voltage balancing circuit

IV. ESTIMATION OF TOTAL VOLUME IN POWER CONVERTERS The components such as the LC filter and the heat sink may determine the volume of a power converter. Thus, the volume of each component is investigated quantitatively for the diode-clamped multilevel inverters. In addition, the total volume of the inverters with the voltage balancing circuit is also investigated. In the following investigation, the volume of gate drive circuits and switching devices such as

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excluded. Fig.12 shows the losses of the voltage balancing circuit. The losses of the voltage balancing circuit are smaller than those of the main circuit, and the number of level does not affect the losses in the voltage balancing circuit significantly.
50 40 Loss (W) 30 20 10 0 3 5 7 9 11 Number of level 13 15 2-level

resistance of the required heat sink SA is given by T j Ta SA = jc + cs (2) PD where, Tj is the allowable temperature of the junction, Ta is the temperature of ambient air, PD is the maximum total loss of the switching devices, jc is the thermal resistance between the junction and the case, and cs is the thermal resistance between the case and the heat sink. The volume of the heat sink Vh is fitted by a technical datasheet [22] of a commercial series of heat sinks as following equation.

Fig.11. Loss of MOSFETs and diodes in the inverter 2 1.5 Loss (W) 1 0.5 0 Lr/Cr=0.01 Lr/Cr=0.1 Lr/Cr=1 5 7 9 11 Number of level 13 15

Vh = 690.8 SA [cc] (3) The volume of heat sink is estimated by (2) and (3). Then, (Tj Ta) is equal to 75K, and (jc + cs) is equal to 0.6K/W. Fig.14 shows calculated results of the volume of the heat sink. As the number of level increases, the volume of heat sink can be reduced. And, the volume of the heat sink in over 5-level can be less than half that of 2-level. Total Volume Fig.15 shows the total volume of the LC filter, the heat sink, and the voltage balancing circuit. In this case, the resonant frequency is 45kHz, and the value Lr/Cr is 0.1. The volume of the voltage balancing circuit is sufficiently smaller than that of the heat sink and the LC filter. As the number of level increases, the calculated total volume can be reduced and significantly smaller than that of the 2-level inverter. And, the total volume of the 11-level inverter is the minimum under this operating condition. In addition, the voltage balancing circuit can become smaller with higher resonant frequency and the smaller value of Lr/Cr.
1000 Total volume (cc) 800 600 400 200 5 7 9 11 13 15 Number of level Fig.15. Total volume of the LC filter, the heat sink and the voltage balancing circuit 2 3 0 RSCC Heat sink LC filter

1.36

C.

Fig.12. Loss of the voltage balancing circuit 50 40 Loss (W) 30 20 10 0 3 5 7 9 11 Number of level 13 15 2-level

Fig.13. Total loss of the voltage balancing circuit and the inverter 600 500 Volume (cc) 400 300 200 100 0 3 5 7 9 11 Number of level 13 15 2-level

Fig.14. Volume of the heat sink

Fig.13 shows the total loss of the voltage balancing circuit and the main circuit of the inverter. The volume of the heat sink is estimated by the calculated results. The thermal

EXPERIMENTAL INVESTIGATION OF 9-LEVEL DIODECLAMPED INVERTER WITH RSCC The validity of the analytical results is confirmed by some experiments employing a 150W mini-model prototype of 9level diode-clamped inverter. The experimental results are compared to the analytical results under the same condition. Fig.16 shows the system configuration of the experimental 9level diode-clamped inverter with the voltage balancing circuit. Table 2 summarizes the circuit parameters. Fig.17 shows the experimental waveforms at various points in the V.

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prototype. Fig.17(a) shows the 9-level output voltage and output current. Fig.17(b) shows the balanced voltages of the DC capacitors. Fig.17(c), (d), and (e) show the resonant currents ir1, ir2, and ir3, respectively. The amplitudes of these waveforms are fluctuating during the output fundamental period. Because the currents flowing from the connecting points of the DC capacitors fluctuate in accordance with the output phase angle, the amplitude of the resonant current that compensates the charge flowing out from the DC capacitors fluctuates during the output fundamental period. Fig.17(f), (g), and (h) show the resonant voltages vr1, vr2, and vr3, respectively. The amplitudes of these waveforms are also fluctuating corresponding to the fluctuation of the amplitude of the resonant currents. The voltage deviation of the DC capacitors and the maximum stored energy of the resonant inductors and the resonant capacitors can be calculated from the experimental results. Table 3 shows the comparison between the analytical and experimental results under the same conditions. The experimental results coincide with the analytical results as for the voltage deviation and the maximum stored energy of the resonant capacitors. However, the maximum stored energy of the resonant inductors in the experiment was different from that of the analysis because the fluctuation of the amplitude of the resonant currents was not considered in the analysis. In the RSCC, when the voltage deviation between two adjacent DC capacitors occurs, the resonant current proportional to the voltage deviation flows. In addition, the fluctuation of the DC voltages becomes large when the capacitance of the DC capacitors is not sufficiently large. Therefore, the amplitude of the resonant currents also fluctuated. Thus, the DC capacitors should be designed considering the fluctuation of the resonant currents.
Table 2. Parameters of the experimental circuit 100V Supply voltage V Load resister Rl 20 Load inductor Ll 3.6mH DC capacitor C1~C8 4.7mF Fundamental frequency 50Hz Carrier frequency in the inverter 2kHz Modulation index 0.96 Switching frequency of RSCC 45kHz Resonant inductor Lr 1H Resonant capacitor Cr 11F Table 3. Comparison between analysis and experiment Analysis Experiment Voltage deviation of DC 1.3V 1.0V capacitors Maximum stored energy 0.018mJ 0.032mJ of resonant inductors Maximum stored energy 5.7mJ 6.2mJ of resonant capacitors

VI. CONCLUSIONS This paper revealed the operating characteristics and the volume of the voltage balancing circuit based on RSCC in diode-clamped multilevel inverters. The volume of the voltage balancing circuit can be reduced by introducing a higher resonant frequency and a lower value of Lr/Cr. In addition, some analytical calculations revealed the total volume of LC filter, heat sink and the voltage balancing circuit can be reduced by increasing the number of level. Above all, the volume of an inverter over 5-level can be less than half of that of a 2-level inverter. Therefore, diodeclamped multilevel inverters with the voltage balancing circuit based on RSCC can be promising candidate to realize higher output power density converters. The experimental results confirmed the fundamental proper operation of a 9level experimental diode-clamped inverter with the voltage balancing circuit. REFERENCES
[1] [2] [3] J. W. Kolar, U. Drofenik, J. Biela, M. L. Heldwein, H. Ertl, T. Friedli, and S. D. Round, PWM Converter Power Density Barriers, Proceedings of the 4th Power Conversion Conference, 2007, pp. 9-29. L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M. A. M. Prats, The Age of Multilevel Converters Arrives, IEEE Industrial Electronics Magazine, 2008, Vol. 2, No. 2, pp. 28-39. Investigating R&D Committee of Current Statuses and Trends of General Purpose Inverter, General Purpose Inverter: Current Status of Energy Saving Effect, Performance Improvement, and Environmental Harmonization, IEEJ Technical Report, No. 807, (in Japanese). A. H. Bonnett, Available Insulation Systems for PWM Inverter-Fed Motors, IEEE Industry Applications Magazines, 1998, Vol. 4, No. 1, pp. 14-26. Investigating R&D Committee of Performance Improvement of Induction Machines, Performance Improvement of Induction Machines, IEEJ Technical Report, N0. 997, (in Japanese). J. Rodriguez, J. S. Lai, and F. Z. Peng, Multilevel Inverters: A Survey of Topologies, Controls, and Applications, IEEE Transactions on Industry Electronics, Vol. 49, No. 4, pp. 724-738. M. Kamaga, K. M. Sung, Y. Hayashi, Y. Sato, and H. Ohashi, An Investigation of Gate Drive Circuits and Losses in Power Devices of Multilevel Converters for Circuit Integration to Realize High Output Power Density, Proceedings of the 5th International Conference on Integration of Power Electronics Systems, 2008, pp. 139-142. T. Kinjo, Y. Hayashi, Y. Sato, and H. Ohashi, Study on High Power Density Integration of Multilevel Converters, Proceedings of the 4th International Conference on Integration of Power Systems, 2006, pp. 223-226. A. Nabae, I. Takahashi, and H. Akagi, A New Neutral-Point Clamped PWM Inverter, IEEE Transactions on Industry Applications, Vol. IA17, No. 5, pp. 518-523. J. S. Lai, and F. Z. Peng, Multilevel Converters-a New Breed of Power Converters, IEEE Transactions on Industry Applications, Vol. 32, No. 3, pp. 509-517. L. M. Grzesiak, and J. G. Tomasik, A Novel DC Link Balancing Scheme in Generic n-level Back-to-Back Converter System, Proceedings of the 7th International Conference on Power Electronics, 2007, pp. 1044-1049. N. S. Choi, J. G. Cho, and G. H. Cho, A General Circuit Topology of Multilevel Inverter, Proceedings of the 22nd Annual IEEE Power Electronics Specialists Conference, 1991, pp. 96-103. J. C. Rosas-Caro, J. M. Ramirez, and A. Valderrabano, Voltage Balancing in DC/DC Multilevel Boost Converters, Proceedings of the 40th North American Power Symposium, 2008, pp. 1-7.

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[14] M. Shoyama, T. Naka, and T. Ninomiya, Resonant Switched Capacitor Converter with High Efficiency, Proceedings of the 35th Annual IEEE Power Electronics Specialists Conference, 2004, Vol. 5, pp. 3780-3786. [15] K. Sano, and H. Fujita, Voltage-Balancing Circuit Based on a Resonant Switched-Capacitor Converter for Multilevel Inverters, IEEE Transactions on Industry Applications, Vol. 44, No. 6, pp. 17681776. [16] T. Ito, M. Kamaga, and Y. Sato, Operating Characteristics of OpenLoop RSCC Connected to Diode-Clamped Multilevel Inverter, Proceedings of IEEJ Annual Meeting, 2009, 4-043, (in Japanese). [17] T. Ito, M. Kamaga, and Y. Sato, An Investigation of DC Capacitors Voltage Balancing Circuit in Diode-Clamped Multilevel Inverter to

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Realize High Power Density Converters, Proceedings of IEEJ Annual meeting, 2010, 4-051, (in Japanese). K. Sano, and H. Fujita, A Resonant Switched-Capacitor Converter for Voltage Balancing of Series-Connected Capacitors, Proceedings of the International Conference on Power Electronics and Drive Systems, 2009, pp. 683-688. TDK: http://www.tdk.co.jp/ KEMET: http://www.kemet.com/ Kowa Denshi: http://www.kowa-denshi.com/ Ryosan: http://www.ryosan.co.jp/

ir1 vr1 ir2 vr2 ir3 vr3

C1 C2 C3 C4

VC1 VC2 VC3 Ll VC4 VC5 VC6 va VC7 VC8 ia Rl

V ir4 vr4 ir5 vr5 ir6 vr6 C8 C5 C6 C7

Fig.16. Experimental system configuration of 9-level diode-clamped inverter connected to the voltage balancing circuit

ia

VC1+VC2+VC3+VC4 VC2+VC3+VC4 VC3+VC4 va 2A,20V,4ms/div (a) Output current ia and output voltage va VC4 10V,4ms/div (b) DC voltages 2A,4ms/div (c) Resonant current ir1 2A,4ms/div (d) Resonant current ir2

2A,4ms/div (e) Resonant current ir3

5V,4ms/div (f) Resonant voltage vr1

5V,4ms/div (g) Resonant voltage vr2

5V,4ms/div (h) Resonant voltage vr3

Fig.17. Experimental waveforms

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