VIT University School of Electronics Engineering ECE301 VLSI System Design FALL 2012-13

Faculty : Jagannadha Naidu K Slot :B1+TB1

Due Date: 3rd November 2012 Batch No Reg Num 10BEC397 10BEC515 10BEC411 09BEC411 10BEC146 10BEC360 10BEC502 10BEC501 10BEC484 10BEC007 10BEC015 10BEC355 10BEC365 10BEC381 10BEC204 10BEC187 10BEC354 10BEC426 10BEC349 10BEC407 10BEC259 10BEC421 10BEC021 10BEC201 10BEC183 10BEC231 10BEC044 10BEC409 10BEC350 10BEC048 10BEC274 10BEC308 Title of the Assignment Arbiter

Modified Booth Multiplier(8Bit)

Electronic Dice Game

Maximum_number

Elevator_Controller

Asynchronous FIFO

6 7

Design and Implementation of a Digital Lock

The Waveform Delay Generator

Washing machine controller

SDRAM Controller

10

Digital Circuit Design

11

12

10BEC400 10BEC004 10BEC181 10BEC387 10BEC249 10BEC041 10BEC105 10BEC452 10BEC323 10BEC064 10BEC065 10BEC0453 10BEC271 10BEC147 10BEC230

Matrix Multiply Min Max Avg controller

13 14

Shared_Memory

Simple_Processor

15

Pattren Detection

16

Motion based light controller

17

1. Arbiter Specifications:

Need to design an arbiter which arbitrates 8 client requests for access to a common resource.

The Arbitration scheme can be either Fixed-Priority or Round-Robin, depending on the selection of the input signal cfg_arb_scheme. If (cfg_arb_scheme = 0), Fixed-Priority scheme is selected and if (cfg_arb_scheme = 1) then Round-Robin scheme is selected.

Let us elaborate on both the schemes:

Fixed-Priority scheme:

In case the Fixed-Priority scheme is selected, the client for which highest priority is accorded is indicated by the input signal cfg_arb_fixed_port.

The next port that can be granted is chosen in ascending/increasing order with reference to cfg_arb_fixed_port. Every time the arbiter gets a port request through port_req[7:0]it starts checking whether the highest priority port denoted by cfg_arb_fixed_port is high. If yes, then the arbiter generates the grant for the cfg_arb_fixed_port.

If cfg_arb_fixed_port is low in port_req[7:0], then the arbiter considers the next port as the highest priority port and so on.

The grant is indicated by an output signal gnt_valid and the port for which the grant is given is indicated by gnt_port[2:0], is also an output signal.

Consider that cfg_arb_fixed_port do not change during run time.

Round-Robin scheme:

In Round Robin Scheme the highest priority port is denoted by one port higher to the port which was the last port to send the arbiter an acknowledge through the ack_port[2:0].

Thus, if the last port which sent acknowledge to the arbiter is port X then the highest priority port in the next iteration will be X+1.

When the next port request port_req[7:0] comes the arbiter checks whether the highest priority port X+1 is high just like the fixed port scheme. If it finds it low it considers the next port X+2 to be the highest priority port and so on.

Last served port after reset can be taken as Port 0.

Block Diagram of Arbiter with I/O interfaces:

port_req[7:0]

Gnt_port[2:0]

Gnt_valid Cfg_arb_scheme Cfg_arb_fixed_port[2: 0] clk reset 8-Port Configurable Arbiter Ack_port[2:0] Gnt_ack

Client 0

Diagram 1: Arbiter interfacing with a single client. (Scope of the design is only arbiter; client is not to be designed)

Inputs and Outputs of Arbiter

Following are the input ports of the Arbiter:

Clk Reset Port_req[7:0] Cfg_arb_scheme

-> System Clock -> Asynchronous and active high System Reset -> 8 Client request -> Select signal for Fixed-Priority or Round-Robin scheme

Cfg_arb_fixed_port[2:0] -> Highest priority port for Fixed Priority scheme

Ack_port[2:0] Gnt_ack

-> last Granted port -> One clock duration valid signal for ack_port[2:0] signal

Following are the output ports of the Arbiter:

Gnt_port[2:0] Gnt_valid

-> Granted port -> Valid signal for granted port

Diagram 2: Timing Diagram of Fixed-Priority Scheme

Clk

port_req[7:0]

00

80

80

80

00

00

41

41

41

41

2 1 3

gnt_valid

gnt_port[2:0]

XX

XX

XX

XX

gnt_ack

XX

Cfg_arb_fixed_port

Note: XX means dont care i.e. it can be any value. When gnt_valid is high, gnt_port is valid else it is dont care.

Diagram 3: Timing Diagram of Round Robin Scheme

Clk

00 port_req[7:0]

10

10

10

00

00

81

81

81

81

gnt_valid

gnt_port[2:0]

XX

XX

XX

XX

gnt_ack

Ack_port[2:0]

XX

XX

XX

XX

XX

XX

XX

XX

XX

3. Electronic Dice Game

Task: Design an electronic dice game. Two counters are used to simulate the roll of the dice. Each counter counts in teh sequence 1, 2, 3, 4, 5, 6, 1, 2, ... . Thus, after the "roll" of the dice, the sum of the values in the two counters will be in the range 2 through 12. The rules of the game are as follows:

After the first roll of the dice, the player wins if the sum is 7 or 11. The player loses if the sum is 2, 3, or 12. Otherwise, the sum the player obtained on the first roll is referred to as a point, and he or she must roll the dice again. On the second or subsequent roll of the dice, the player wins if the sum equals the point, and he or she loses if the sum is 7. Otherwise, the player must roll again until he or she finally wins or loses.

Two push buttons as inputs to the dice game:

' Reset ' ---- to initiate a new game ' Rb (roll button)'

a). When the roll button is pushed, the dice counters count at a high speed, so the values cannot be read on the display. b). When the roll button is released, the values in the two counters are displayed, and the game can proceed. c). If the Win light or Lose light is not on, the player must push the roll button again. Below is the block diagram for the game.

4. Maximum Number
Problem Draw a block diagram of the execution unit of a circuit capable of storing a set of 32 8-bit unsigned integers in an internal memory, and then computing the largest and the second largest number in this set and their respective positions within the set.

5. Elevator_Controller

Elevator has four buttons. Two external buttons and two internal buttons (in the elevator car). In addition, there are two floor level sensors. When the elevator is on the ground floor, the ground sensor is ON. If the elevator moves up, the ground sensor is OFF, and the first level sensor will be switched ON when the elevator arrives on the first floor. The engine and direction are elevator inputs. Inputs: engine: ON and OFF direction: move up (ON), move down (OFF) Outputs: FirstSensor: ON if the elevator is on first floor, otherwise OFF GroundSensor: ON if the elevator is on ground, otherwise OFF out_up and out_down: External buttons. Switch ON if pressed, and stay on until the elevator arrives in correct floor. up and out: Internal buttons. Switch ON if pressed, and stay on until the elevator arrives in correct floor.
6 Asynchronous FIFO

Asynchronous FIFO

Task: Design asynchronous FIFO

The first data word written to the FIFO is the first word that flows out the end, the second word written is the second that is read out, etc. The writing and reading are controlled by ' WRITE ' and ' READ ' control signals from the sender and receiver of data, respectively. ' WRITE ' signal is asserted whenever data is being written into the FIFO ' READ ' has an analogous meaning. In addition, two status lines are provided indicating that the FIFO is ' FULL' or ' EMPTY '.

As soon as data is being taken out of the full FIFO, ' FULL ' signal gets deasserted; at this point the sender can begin loading up the FIFO with new data. When new data has been written into an empty FIFIO, ' EMPTY ' signal gets deasserted, and new data can be read out by the receiver.

Project description: You are to design a 4X2 (four words deep by 2 bits wide) FIFO, like the one shown in the following figure.

Assumptions:

The sender never writes to the FIFO if it is FULL. The receiver never reads from the FIFO if it is EMPTY. If the sender has several words to write consecutively into the FIFO, it proceeds as follows: a). The sender first ensures that FULL is not asserted. b). It then writes the first word into the FIFO. c). The sender then checks to see if FULL is asserted, and if it isn't, writes the next word into the FIFO. If FULL is asserted, the sender waits for it to be deasserted before writing the next word. This process continues until all words have been written into the FIFO.

The receiver reads multiple words from the FIFO as follows:

a). When EMPTY is deasserted, it reads the first word from the FIFO. The receiver then checks to see if EMPTY is asserted, and if it isn't, reads the next word from the FIFO. This process is repeated until all desired words have been read or EMPTY gets asserted. b). If the receiver is idle, and there is nothing in the FIFO, it checks EMPTY every cycle, waiting for it to be deasserted.

On initialization, the circuit should be in the EMPTY condition(EMPTY asserted, FULL deasserted, and the circuit ready to accept write data).

7. Design and Implementation of a Digital Lock

8. The Waveform Delay Generator The waveform delay generator has a 4-bit programmable delay, takes an input, A, and outputs B after the predefined delay expires. The two waveforms, A and B, should look identical, except B is delayed. For simplicity of the design, A cannot be asserted again until B is cleared, i.e. the interval between two pulses on A cannot be less than the delay; the length of the pulse on A cannot equal to the delay; and the length of the pulse on A is 15 clock cycles. There are two possible scenarios that can happen : i) the length of the pulse on A is longer than delay; ii) the length of the pulse on A is shorter than delay. The scenarios are illustrated in Figure Care should be taken when implementing the controller so both cases are covered.

The top level of the sorter consists of a reset, a system clock, a pulse input, A, a 4-bit programmable input delay in, and an output pulse, B. The top-level block diagram is illustrated in Figure 2

9. Washing machine controller 10. SDRAM Controller 11. Digital Circuit Design Problem Function The circuit accepts samples from two A/D converters, provided at the inputs A and B, respectively, as wbit signed numbers in the twos complement representation. The samples are generated by each A/D converters in the groups of four, separated by 10 ns within each group, as shown in the figure below. Two consecutive groups of samples are separated by 100 ns. The circuit should compute an average value of four samples within each group, and then compare an average for a group entered using input A with an average for a group entered using input B. A special counter, initialized to zero using reset at the beginning of processing, should be incremented each time an A average is greater than the B average, and decremented in the opposite case. If both averages are the same, the counter should remain unchanged. When the counter reaches a threshold of +10, it does not increment any longer, and it generates an active value at the output overflow, each time A average is greater than the B average. Similarly, when the counter reaches value -10, it does not decrement any longer, and it generates an active value at the output underflow, each time A average is smaller than the B average. Values of the counter, and the signals overflow and underflow should remain unchanged in the period between two consecutive comparisons. A new value of the counter should be indicated with the output control signal new_count, which should be set to high for two clock cycles after the computation of the new value of the counter, and set to zero otherwise.

12. Matrix Multiply

12 clock cycles or less and to operate at a clock frequency of not less than 25 Mhz. There are no resource limitations; use as many multipliers, adders, registers, RAMs etc as you want. The device must be the EPF10K20RC240-4 (Flex 10K, note the speed grade!!!!) The interface to the design has been altered to define two modes of operation: continuous mode and normal mode. The new interface for mmult is defined as follows:

Inputs

clk, reset - clock and asynchronous reset din[8..0] - data bus for both 9-bit matrix coefficients and 8-bit coordinates cf_load - used to load the 16 matrix coefficients start - used to input the 4 coordinate values and start a computation

Outputs

dout[7..0] - output bus for transformed coordinates busy - asserted when either coefficient values are being loaded or a matrix operation is being performed output_rdy - asserted when either coeffs or dout contains valid data input_rdy - asserted when ready for new coordinate data

Clock Cycle Constraint

The clock cycle constraint of 12 clocks is measured between falling edges of the input_rdy output while in continuous mode (this number of clocks defines the initiation rate of the design). The smallest possible number of clocks is 4; this represents a continuous stream of X,Y,Z,W values on the DIN bus.

Extra Points
You can earn extra points in two ways:
1. For every Mhz above 25 Mhz, you earn 1 extra point. There is no maximum to this bonus. 2. For every clock cycle below 12 for the initiation rate, you earn 2 extra points. You earn a 10 point bonus for an initiation rate = 4, for a maximum bonus of 20 points.

The bonus points are added directly to the point total of your tests. IF you earn the MAXIMUM bonus for #2, you have the option of keeping all of the bonus points or dropping one test grade (the final exam does not count as a test grade).

Extra points will ONLY be awarded if you meet all functionality specs and timing specs (i.e, a design that fails functionality tests, but fails them fast at 100 Mhz, still gets 0 extra points)

Hints
1. There are 16 multiply-add operations. You must have at least 2 multiply-add blocks in order to perform the multiply in 12 clock cycles or less. 2. The more resources you use, the less complex your finite state machine will be. 3. An alternate way to do the computation is in column order. Once you have X, you can perform the X*T00, X*T04, X*T08, X*T11 calculations in parallel instead of waiting for Y, W, Z and doing the X*T00, Y*T01, etc. calculations. 4. I doubt that you can get 25 Mhz operation without putting a register between your multiplier and saturating adder; you may even have to pipeline your multiplier. 13.Min Max Avg controller Specification of the MIN_MAX_AVR circuit

Function

Design a circuit capable of calculating the minimum, maximum, and average of 32 n-bit numbers.

Optimization

Optimize your circuit for the minimum total execution time. When choosing between two circuits with the same or very similar execution time, give preference to the circuit with the smaller area.

Interface

Assume the following interface to your circuit:

clk reset in_data in_addr write START n 5 MIN_MAX_AVR n out_data 2 out_addr DONE

Port clk reset in_data in_addr write START DONE out_data out_addr

Width 1 1 n 5 1 1 1 n 2

Meaning System clock System reset clears internal registers Input data bus Address of the internal memory where input data is stored Synchronous write control signal Starts the computations Asserted when all results are ready Output data bus used to read results 01 reading minimum 10 reading maximum 11 reading average

14. Shared_Memory

Problem Draw the State Transition Diagrams for the controllers below. Controller 1 is the data producer; it streams a sequence of values to the shared, single word buffer. Concretely, it reads the value from the memory location pointed to by the memory pointer, places it in the next value register, and sets the valid bit to inform the consumer that the shared buffer is full. It increments the memory pointer before reading the next word. Controller 2 is the data consumer; it takes the value from the next value register when valid, clears the valid bit, accumulates the value and places it in the accumulated value register. The true controllers operate independently and run and potentially different rates. The producer cannot overwrite the buffer until it has been emptied, and the consumer cannot read it until it is full. Be careful to design the FSMs such that memory locations are not added in multiple times in a row and that values are not lost. Note that this problem is a little bit open ended. You will need to specify the inputs and outputs of your two cooperating state machines, as well as determining the symbolic states and the functional behavior.

15. Pattren Detection Problem Function Design and describe using RTL capable of processing a stream of up to 2m data bytes in search of a specific data pattern, of the size of k bytes. The circuit should detect the pattern, and output the position of the given pattern each time it appears in the input data stream. Interface Assume the following interface to your circuit:

17. Motion based light controller

Problem In this problem you will design a (now familiar) motion-based light controller shown in the diagram below. The wall switch is normally left in the ON position, supplying power to the controller and the light. The normal behavior of this controller is to turn the light ON for 30 seconds after motion is detected, but only if it is dark out. In addition, there is an override mode where if the switch is turned OFF and back ON within 2 seconds it turns the light on for 5 minutes, regardless of daylight or motion. Override can occur while the light is ON, either due to motion or test. Your controller has two digital inputs based on the photocell and passive infrared sensors: daylight and motion. In addition, it has a circuit that detects when the switch is turned off and provides the input Switch_off. (The controller has a backup capacitor so it can run for a while with the switch off.) It has an output AC_on that controls a relay to actually turn the light on and off. It has three preset timers, each with a start control point and a fired signal. The start signal for a timer should be asserted for one cycle to start the timer. Each time it is pulsed it will reset the timer.