Modeling of Pocket Implanted MOSFETs for Anomalous Analog Behavior

Kanyu Mark Cao, Weidong Liu, Xiaodong Jin, Karthik Vasanth*, Keith Green*, John Krick*, Tom Vrotsos*, and Chenming Hu
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, C A 94720, USA Tel: 510-643-2639 Fax: 5 10-643-2636 Email: kcao@cory.eecs.berkeley.edu *Spice Modeling Laboratory, Texas Instruments, Dallas, T X 75266, USA

Abstract Pocket implant is widely used in deep-sub-micron CMOS technologies to combat short channel effects. It, however, brings anomalously large drain-induced threshold voltage shift and low output resistance to long channel devices. This creates a serious problem for high-performance analog circuits. In this paper, the first physical model of these effects are proposed and verified against data from a 0.18pm technology. This model is suitable for SPICE modeling. Introduction Pocket implant is widely used in deep sub-micron CMOS technologies to reduce VTroll-off and punch-through [ 11. This technique, however, produces large drain-induced VT shift and low R,,, in long channel devices [2], greatly affecting analog circuit design and performance. Physical compact model for these effects, however, is not available. In this work, we report the first physical model of these effects suitable for compact MOSFET modeling. The proposed model is verified against both simulation and experimental data from a 0.18pm CMOS technology. Drain-induced threshold voltage shift (DITS) Fig. 1 illustrates the enhanced DITS effect in long channel devices with pocket implants compared with uniformly doped devices using 2-D simulation. Fig. 2 is an illustration of the structure used in the device simulation. DITS increases by 2 to 3 times for long channel devices. Fig. 3 shows the simulated q ~ \vs. x for two V,, biases for a pocket implanted device. Clearly, q\ is independent of x in the center segment of the channel and the drain barrier peak decreases with increasing V,, thus leading to DITS. Starting with the drift-diffusion equation, we derived a drain current expression by considering the source-end, center, and drain-end sections of the channel separately and applying a DIBL model [3] to the drainside barrier only: 15,Tu I, y W w D 6 - e+* ) = AW C,L + (1 + e-clv* ) (1) ~ o ~ e - ~ ~ ~ , - ~ P &w~r ~-(~ v ~ 2 ~ n ) ~ , ~ ~ y I

where S is the sub-threshold swing and can be calculated or extracted [4]. Modeling the output resistance Pocket implants also lower the output resistance, R,,,. Figure 4 shows that at low V,,, R,,, can be 10 to 100 times smaller because of the pocket implant. Pocket implants affect output resistance in two ways. Firstly, DITS causes Z h to increase with increasing V,. The early voltage due to this mechanism can be derived from (1):

Since parameters CI and C2 in (1) are used to model Zd, in subthreshold-threshold region, we introduce parameters CoC, C, and C2, to accurately capture this effect in strong inver,, sion region:

where p=&g, p, is the surface potential, and CI and C2 as cI -- e-P(c"s*-c"m,"l)@qN p xdep-&"x(vTo - v F B - ~ ~ ) / I ; , I / & , l(2) ~ ~ I x~

The second effect of the pocket implant on R,,, is that the output resistance due to all mechanisms (CLM, DIBL, etc.) is reduced by a factor that varies with V,, and L. Let us compare a pocket-implanted device with a MOSFET uniformly doped to the pocket concentration, N,,. In Figure 5 , both devices are partitioned into two parts. The device on top has a length L,,, the length of the pocket. The lower part is the rest of the channel with length L-L,,. This partition is useful because in the saturation region, is mainly determined by the effects in a small region close to the drain, and the rest of the channel, i.e. the lower device may be considered simply a source resistance. For the cascode circuit in Fig. 5(a), the output resistance in saturation is well known: R,,, = (g,,,,r,, + 1). rC,, (LI L p ) .r,,l = (5) where rol is the output resistance of the device on top. In a similar way, % of the pocket device, i.e. the circuit in Fig. , 5(b) can be derived as:

C, = p

(,LP'ZP

+&-LP'lP)

doping and since Early voltage VAis insensitive to Vg,r, i and M the gate voltage at which Id,=Icnr=IT.WIL, where IT is the MI, should have the same VA. threshold current chosen experimentally. Then the threshold voltage shift can be derived as:

are model parameters.

1, =

Jm'. to be If V , is defined

where hv, = v , ( N , ) - v , ( N , , , ~ ) .Since M I and Mi, have the same

c.1 ['.a. I

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equations (5), (6) and (7) model of the degradation factor is compared with the ratio of the output resistance of the pocket-implanted device can be output resistance measured on devices with and without pocket implants. The devices are otherwise identically fabrirewritten as: (8) cated using a 0.18 pm process. The agreement is excellent. Routp = F . R O U , The proposed model not only provides the first physical where R,,, is the output resistance of the uniformly doped analysis for the anomalous analog behaviors but is also suitdevice, which can be modeled by conventional models such as able for use in compact modeling of analog devices. It was implemented into the BSIM3 model and model parameters BSIM3v3 [4]. F is a degradation factor were extracted for a 0.18pm technology. Fig. 13 shows that the output resistance fitting is excellent and the fitting in long region has been significantly improved. channel, low V,,T-V~ where PF S , I L should be considered a fitting paV Both the threshold voltage model and the output resistance ,, model are reduced to the original model when I K , , C and rameter decided by the characteristics of pocket implant. SVT approach zero. In that case, AVFO in (3), VA,Dms=co in Results andDiscussion Eq. (3) can be added to a conventional VT model as a new (4a), and F=l in (9) respectively.,Also from the expression, term. Fig.6 shows the agreement between the model and the we can see that to minimize the degradation of the output remeasured VT of a W b S p m / l O p m device. Fig. 7 shows that sistance, pocket implant with lower peak concentration and the BSIM3 VT model [3] does not model the Vll,Tdependence wider lateral length is desired. These are also the conditions to of VT at long gate lengths. Fig. 8 shows that the new model minimize the long channel DITS effect. This agrees with the significantly improves the fitting using parameters extracted fact that output resistance degradation and long channel DITS from Fig. 6. The new threshold shift model can give rise to are highly correlated [2]. Although the models are developed DITS at long channel lengths where the conventional DIBL for pocket implanted devices, it can also improve the model theory predicts none. This can be explained by the fact that at accuracy of devices without pocket implant if it has reverse Vg-VT and small Id,,, there is little voltage drop in most of the short channel effect (RSCE) due to defect-enhanced diffusion. Acknowledgements channel region. Therefore, even in a long channel device, nearly all the Vd,Tis available to reduce the drain-side barrier The authors want to thank Joe Watts and Peiqi Xuan for disheight as shown in Fig. 3 and the drain barrier height can sig- cussions and BTA for providing model development tool. The work is supported by SRC under contract 98-SJ-417, Compact nificantly affect IdT. To verify the model of (9), 2-D simulations and meas- Modeling Council, and Texas Instruments under the MICRO urements are performed for identical devices with and without program. References pocket implant. Fig. 9 shows that the degradation factor is indeed a constant, independent of Vds in the saturation region [I]M.Rodder et al., A 0.10pn Gate Length CMOS Technology with 30A Gate Dielectric for I.0V-1.5V Applications, IEDM Tech. Digest, p 223, which is in agreement with (9). Our derivation is general and 1997. does not depend on what mechanisms determine the kUt. A. Chatterjee et al., Transistor Design Issues in Integrating Analog [2] From the model, at high V,, and long L, if F is plotted versus Functions with High Performance Digital CMOS, Proc. V U 1 Sypm., cv,, - v r ) l f i ,all data should fall on a universal curve. This is pp.147, 1999.Jiu et al., Threshold Voltage Model for Deep-Submicrometer Considering

sv, << (v,- vT), using

[3] Zhi-Hong

verified in Fig. 10. F vs. V,, for different L also agrees with MOSFETs, IEEE TED Vol. 40,No. 1, pp. 86, Jan. 1993. the 2-D device simulation data in Fig. 11. In Fig. 12, this [4]Weidong Liu et al., BSIM3v3.2 MOSFET Model Users Manual (1998).
pp. 3-10. http://www-device.eecs.berkeley.edu/-bsim3/.

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Fig. 1. Comparison of (Vnin-V~st)vs. L between two devices with and without pocket implant by 2-D simulation. The threshold voltage shift is 2-3 times larger for the pocket implanted device at long gate lengths.

Fig. 2. Device structure used in 2-D device simulations. Pocket doping profile shown simulates that of a 0.18pm technology.

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Fig. 3. Simulated channel surface potential. Only the drain barrier is significantly affected by Vd,. The integration in F.q. I is carried out in regions TI, Tz, and T1. Fig. 4. Simulated , of the device with pocket implant is more than 10 R times smaller at long channel length. One device has a pocket doping of NP=8E17cm,and pocket length I,,=O.OIpm. The devices are otherwise identical.

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Fig. 5. Equivalent circuits usedin the derivation of the output resistance model. A uniformly doped device is shown in (a) and a pocket implanted device in (b).

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Fig. 8. Fitting of experimental data with the new model added to the BSIM model used in Fig. 7. The number of fitting parameters is the same as in Fig. 7 because parameters extracted in Fig. 6 are used in the new model.

Fig. 7. Best-effort fitting of experimental data with the BSIM3 model. The model shows negligible DIBL effect (V, dependence) at long gate lengths.

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Fig. 11. Agreement of V, dependence of the degradation factor F be, tween model and simulation for different gate lengths.

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Fig. 13. On the left, the equivalent circuit of the implementation of proposed model. On the right is the fitting of measured Rou,of 0.18pm technology using the model implemented. 12 devices with gate lengths from 0.15pm to 10pm are fitted using a single set of parameters without binning. The maximum error is 17.0% and the RMS error is 4.9%. A new V,, model and CLM R,, model were also implemented for the fitting.

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