555 Timer and its Applications Since the development of this chip, called the 555 timer, in 1972

by Signetics, it has become so versatile that the electronic-circuit designers are developing new applications where it can be effectively used. The most important feature of this chip is that we can develop oscillating or non-oscillating circuits with very few external components. The main elements of this chip that help us understand its operation, as shown in Figure-1, are (a) (b) (c) (d) (e) Three resistors, about 5-k, forming a voltage divider circuit. Two comparators An RS flip-flop An open-collector npn transistor A reset

The reset terminal (pin-4) controls the operation of the 555 timer. The output voltage at pin-3 is low as long as the reset pin is connected to low. The timer begins its operation only when the reset pin is connected to the applied voltage. Pin-1 is usually the ground and pin-8 is the dc supply terminal. For the proper operation, pin-8 and pin-4 are usually connected together.

Figure 1: Simplified version of a 555 timer

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

The voltage divider comprising of three 5-k resistors biases the noninverting terminal of comparator C1 at VCC / 3 and the inverting terminal of comparator C2 at 2 VCC / 3 . It is recommended by almost all the manufacturers of the 555 timers that the control terminal (pin-5), when not in use, should be connected to ground via a 0.01 F capacitor.
The capacitor will filter the power supply noise, which may otherwise interfere with the operation of the two comparators. The output at Q (pin-3) of the flip-flop is either high (almost equal to VCC ) or low (nearly equal to zero). The output is controlled by the set (S) and reset (R) input to the flip-flop within the 555 timer. When Q is high, the output at Q is low, which in turn forces the npn transistor Q1 to

operate in its cut-off mode. On the other hand, when Q is low, Q is high, and Q1 operates in the saturation region with a very small voltage between its collector and emitter terminals. For all practical purposes, Q1 can be modeled as a switch. When the output of comparator C1 goes high, it sets the flip-flop and the voltage at Q goes high and that at Q goes low. The output of comparator C1 is high only when the trigger input at pin-2 tends to go below VCC / 3 . The output will stay high as long as the voltage at reset (R) of the flip-flop remains low. The voltage at R of the flip-flop goes high only when the output of comparator C2 is high. This happens when the threshold voltage at the noninverting terminal of C2 (pin-6) tends to go above 2 VCC / 3 . Let us now summarize the operation of the 555 timer: 1. The reset terminal (pin-4) should be connected to the dc voltage source for the proper operation of the 555 timer. As long as the reset terminal voltage is low, the output voltage at pin-3 is low. 2. When a voltage lower than VCC / 3 is applied at pin-2 (trigger voltage or input voltage), the output voltage at pin-3 goes high. 3. The output voltage at pin-3 goes low only when the input at pin-6 (threshold) is higher than 2 VCC / 3 .

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

The voltage levels for the two comparators may be changed by applying a dc voltage other than 2 VCC / 3 at the control terminal (pin 5) of the 555 timer. For example, we can set the voltage level at the inverting terminal of C2 to 9 V by applying a 9-V source to pin-5. If we do so, the voltage level at the noninverting terminal of C1 is now set to 4.5 V. The voltage level at C1 and C2 may also be changed by connecting a resistor between pin-5 and the ground.

Figure 2: Astable multivibrator

We now explain how we can use the 555 timer to operate in its oscillatory mode as an

astable multivibrator. Let us begin with the understanding that the circuit in Figure 2
has been operating for a long time and it has attained its stead state as an oscillator. The voltage across the capacitor at t = 0 is just below VCC / 3 and the output of C1 is high, which in turn forces the output voltage to go high as shown in Figure-2. Since Q is high, Q is low. The transistor Q1 is off and the capacitor C begins its charging cycle toward VCC through R 1 and R 2 according to the following differential equation.

(R 1 + R 2 )C dv c ( t ) + v c ( t ) = VCC
dt The general solution of the above first-order differential equation is v c ( t ) = VCC + A e t / c where
c = (R 1 + R 2 )C

(1)

(2) (3)

is the charging time constant and A is the constant of integration.

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

Applying the initial condition that v c (0) = VCC / 3 at t = 0, we obtain 2 A = VCC 3 Consequently, the voltage across the capacitor during the charging cycle is v c ( t ) = VCC 2 VCC e t / c 3 (5) (4)

The capacitor continues to charge toward VCC until it attains a voltage of 2 VCC / 3 at t = TC , where TC is the charging time. This condition enables us to obtain an expression for the charging time from (5) as 2 2 VCC = VCC VCC e TC / c 3 3 This equation yields the charging time as TC = c ln(2) = (R 1 + R 2 )C ln(2) (6)

As soon as the voltage across the capacitor tends to go above 2 VCC / 3 , the output of comparator C2 goes high, which resets the flip-flop and the output voltage at pin-3 goes to zero. Since the voltage at Q is low, the voltage at Q is high. The transistor Q1 turns on and operates in the saturation region. The voltage at the discharge terminal (pin-7) is nothing but the collector-to-emitter saturation voltage of Q1, which may be about 0.2 V or so. Therefore, the discharge terminal provides a path for the capacitor to discharge through R 2 toward the saturation voltage of Q1. Assuming that the collector-to-emitter saturation voltage of Q1 is zero, we can write the following differential equation for the voltage across the capacitor during the discharging cycle for 0 t TD as R 2C dv c ( t ) + v c ( t) = 0 dt (7)

Its general solution is v c ( t ) = B e t / d where

d = R 2C

(8)

(9)

is the discharging time constant.

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

Applying the initial condition that v c (0) = 2VCC / 3 at t = 0, we obtain B= 2 VCC 3 (10)

Consequently, the voltage across the capacitor during the discharging cycle is v c (t) = 2 VCC e t / d 3 (11)

The capacitor continues to discharge toward zero until its voltage tends to go below VCC / 3 at t = TD . The output of comparator C1 goes high, which sets the flip-flop and the output voltage at pin-3 goes high as well. Since Q is now high, Q is low, the transistor Q1 shuts off and the capacitor begins its charging cycle allover again. The discharging time can be obtained from (11) as 1 2 VCC = VCC e TD / d 3 3 Hence, the discharging time is TD = d ln(2) = R 2 C ln(2) The time period and the duty cycle are T = TC + TD = (R 1 + 2 R 2 )C ln(2) (13) (12)

D=

TC R + R2 = 1 T R 1 + 2R 2

(14)

Comparing the equations (6) and (12) for the charging and discharging times, we find that the charging time is greater than the discharging time. This simple arrangement results in a duty cycle that is more than 50% as is evident from (14).

Example 1: _________________________________________________________
Design a 555-timer circuit with a duty cycle of 75% and the oscillation frequency of 1000 Hz. Use a 0.1-F capacitor for this application: Solution: For the oscillating frequency of 1000 Hz, the time period is T= 1 1 = = 1 ms f 1000

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

For a duty cycle of 75%, the charging and discharging time periods are TC = DT = 0.75 1 10 3 = 0.75 ms

TOF = (1 D ) T = (1 0 .75 )1 10 3 = 0 .25 ms

From (12), we obtain the unknown resistor R 2 needed during the discharging time as R2 = TD 0.25 10 3 = = 3.608 k C ln(2) 0.1 10 6 0.693

From (6), we obtain the unknown resistor R 1 , which is a parting of the charging time, as TC 0.75 10 3 R1 = R2 = 3.608 10 3 = 7.214 k 6 C ln(2) 0.1 10 0.693 Select the closest standard values for R 1 and R 2 .

Improved circuit to obtain any desired duty cycle between 0 and 1.

Figure 3: Circuit for independent charging and discharging times

The circuit we have just analyzed is good to obtain a duty cycle of more than 50%. To obtain a duty cycle below 50%, we can include a diode D in the circuit as shown in Figure 3. In this case, under the assumption that D is an ideal diode, the charging and discharging times from (6) and (12) are TC = R 1C ln(2) and (15) (16)

TD = R 2 C ln(2)
T = TC + TD = (R 1 + R 2 )C ln(2)

The corresponding time period and duty cycle are (17)

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

D=

TC R1 = T R1 + R 2

(18)

Example 2: ____________________________________________________________
Design a 555-timer circuit with a duty cycle of 25% and the oscillation frequency of 1000 Hz. Use a 0.1-F capacitor for this application: Solution: We use the circuit of Figure 3 to obtain a duty cycle of 25%. For the oscillating frequency of 1000 Hz, the time period is T= 1 1 = = 1 ms f 1000

For a duty cycle of 25%, the charging and discharging time periods are TC = DT = 0.25 1 10 3 = 0.25 ms TD = (1 D)T = (1 0.25)1 10 3 = 0.55 ms The two unknown resistors may now be computed from (15) and (16) as R1 = TC 0.25 10 3 = = 3.608 k C ln(2) 0.1 10 6 0.693

TD 0.75 10 3 R2 = = = 10.824 k C ln(2) 0.1 10 6 0.693 Once again, we should select as few standard components as possible to obtain the desired values of the two resistors.

Improved circuit to obtain a constant time-period regardless of the pulse width:

Although the circuit in Figure-3 enables us to obtain a desired duty cycle, it has one major drawback for pulse-width modulation application. As the values of the two resistors are changed to reflect the change in the duty cycle, the time period and thereby the frequency change as well. The change in the frequency is not an acceptable feature for a circuit used for pulse-width modulation. This minor setback can be overcome if we just look at (17) and (18). The time period depends upon the sum of the two resistors. The time period can be held the same as long as the sum of the two resistors remains the same. In other words, a decrease in the value of one resistor can be offset by an increase

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

in the value of the other. This basic understanding led to the development of the circuit given in Figure-4 using a potentiometer.

Figure 4: Constant time-period circuit

The charging and discharging times for the circuit in Figure-4 are TC = (R 1 + R )C ln(2) (19) (20)

TD = R 2 C ln(2)
The time period and duty cycle are

T = (R 1 + R 2 + R )C ln( 2)
D= TC R + R1 = T R + R1 + R 2

(21) (22)

The time constant depends upon the sum of R 1 and R 2 , which is the total resistance of the potentiometer and is constant. Thus, the time period is independent of the duty cycle. Keep in mind that this is not the only circuit that results in a constant time period. There are many other circuits based upon the 555 timer that will meet the constant time-period requirement. This circuit can be used to control the speed of a dc motor, the power-dissipation capability of a heater, the dimming of the lights, etc. If the current requirement of the load exceeds that supplied by the 555 timer, we can always use a power transistor as shown in the figure 5, where the freewheeling diode is also included to bypass the current

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

of the inductive load when the transistor is off. Note that VDC can be a separate dc supply and it does not have to be the same as VCC .

Figure 5: Pulse-Width Modulation circuit for various applications

Example 3: _________________________________________________________
Design the circuit given in Figure-4 so that the duty cycle is 40% and the time period is 1 ms. To keep the power dissipation low, select all resistors in kilo-ohm range. Solution: This is a design example with many possible answers. Since the capacitor selection is often limited, let us select 0.01 F capacitor for this application. For a time-period of 1-ms, we use (21) to obtain R + R1 + R 2 = T 1 10 3 = = 144.3 k C ln(2) 0.01 10 6 0.693

Let us use a 100-k potentiometer such that R 1 + R 2 = 100 k . Then, the resistor R is 44.3 k. Since 44.3-k is not a standard value of a resistor, we can us two 22-k standard resistors in series. Equation (22) helps us determine R 1 and R 2 for a duty cycle of 0.2 as 44 + R 1 = 0 .4 144 where all the resistors are in kilo-ohms.

Guru/PEDC2DC/ February 19, 2006

555 Timer and its Applications

From the above equation, we get R 1 = 13.6 k and R 2 = 100 13.6 = 86.4 k The charging time and the discharging time, from (19) and (20), respectively, are TC = (R 1 + R )C ln(2) = (13.6 + 44) 103 0.01 10 6 0.693 = 0.399 ms TD = R 2 C ln(2) = 86.4 103 0.01 10 6 0.693 = 0.599 ms Hence, the time period and the duty cycle are T = 0.399 + 0.599 = 0.998 ms D= 0.399 = 0.3998 0.998

The design is complete as the required constraints for the time period and duty cycle are met.

Problems: ______________________________________________________________
1. Design the circuit given in Figure-2 so that the duty cycle is 60% and the time period is 1 ms. If the 555-timer is operating from a 15-V dc supply, sketch the output and the capacitor voltages. 2. Design the circuit given in Figure-3 so that the duty cycle is 40% and the time period is 1 ms. If the 555-timer is operating from a 12-V dc supply, sketch the output and the capacitor voltages. 3. Redesign the 555 timer so that its sets and resets at 0.25VCC and 0.75VCC , respectively. Write appropriate differential equation to obtain expressions for the charging and discharging time periods. 4. Repeat Problem-1 using the redesigned 555 timer of Problem-3. 5. Repeat Problem-2 using the redesigned 555 timer of Problem-3. 6. Design the circuit given in Figure-4 using the redesigned 555 timer of Problem-3 so that the duty cycle is 25% and the time period is 2 ms. 7. Determine the minimum duty cycle that can be obtained using the components selected in Design Example above.

Guru/PEDC2DC/ February 19, 2006

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555 Timer and its Applications