650LabHandout Fall 2012

EEEE 650 Design of Digital Systems with VHDL Lab #1: Introduction to VHDL
Labs are due at the beginning of next lab 10% off for each day late. Once past 50% off, you get a 0. Weekend time does not count. Suppose your lab section is on Wednesday [or Friday] at 2pm. Demo: Wednesday [Friday] before 2pm get 100%, Thursday [Monday] before 2pm get 90%, Friday [Tuesday] before 2pm get 80%, Monday [Wednesday] before 2pm get 70%, Tuesday [Thursday] before 2pm get 60%, Wednesday [Friday] before 2pm get 50%, after second Wednesday [Friday] 2pm you get 0; Work alone. Each student will receive their own board. Advice: In your work load for the week, finish labs first then homework as you dont know how long it will take to get the labs working. Dont wait until the last minute!! Use office hours.
Troubleshooting with Altera: Google is your friend. Search for error codes, messages, and sample code. There is a lot of help on Google! Appendix A of the book has good sample code. Use RTL Viewer under Compile Design / Analysis & Synthesis / Netlist Viewers, in order to look at how it is interpreting your code and what circuit it is implementing. When you have errors, search in the console tab for more details on the errors. Errors are meaningful!
Things to know about VHDL: VHDL is not case sensitive. VHDL is not a programming language! It is a hardware description language. Therefore behavior is inherently parallel. VDHL is heavily type oriented. Variables must be assigned with values of exactly the same type! VHDL uses processes for internal component description. Processes require a sensitivity list (list of inputs to component). If the list is incomplete, the design will simulate but not necessarily work in hardware.
Adapted by Carlos Barrios Page 1 of 2 from EE347 and EE650 labs by Dorin Patru Technical Assistants Office: 09-3248 9/11/2012 Technical Assistants Phone: x5-7092
Design of Digital Systems - EEEE 650 Rochester Institute of Technology Url: http://www.rit.edu/~labeee
Must specify a value for all outputs for every case or state. If an output is not specified, a latch warning will occur which will create hardware issues. Code outside a process is combinational (i.e. parallel). Code inside a process is sequential (i.e. like a software program). Two different processes can not modify/update the same variable. Multisource error will occur.
Sample Code, adapted from Figure A.35 in Appendix A of the course textbook [1].
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY reg4 IS PORT( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Resetn,Clock : IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END reg4; ARCHITECTURE Behavior OF reg4 IS SIGNAL sD : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN sD <= D; PROCESS (Resetn, Clock) BEGIN IF Resetn = 0 THEN Q <= 0000; -- This is a comment. For hex notation use: x --For example: Q <= x12; ELSIF ClockEVENT AND Clock = 1 THEN Q <= sD; END IF; END PROCESS; END Behavior;
References
[1] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, Third Edition, McGraw Hill, 2005.
EEEE 650 Design of Digital Systems with VHDL Lab #2: Introduction to QuartusII
Objective The purpose of this laboratory exercise is to introduce the Altera Quatus II software. A simple decoder and a full adder will be designed and tested using VHDL. The students knowledge of emulation will also be refreshed by downloading the designs to the Altera UP1/UP2 boards. Lab Part 1 - Decoder In this section you will design a 2-to-4 decoder with enable in VHDL. The decode truth table is shown in Table 1.1. The design will be entered and synthesized, implemented to the FLEX10K FPGA architecture and verified first in simulations then in hardware. An exhaustive test bench will be created to test the design at the functional and timing levels of analysis.
Inputs Data1 X 0 0 1 1 Outputs Eq2 Eq1 0 0 0 0 0 1 1 0 0 0
enable 0 1 1 1 1
Data0 X 0 1 0 1
Eq3 0 0 0 0 1
Eq0 0 1 0 0 0
Table 1.1: Logic Table for Decoder
Writing & Compiling VHDL Source Files Create a new directory to store the files for this course. It is important to retain backup copies of your files on a network location or portable USB device. However, synthesizing and implementing projects from a non-local directory to the workstation will result in significantly longer processing delays. Open the Quartus II Software and go to File New Project Wizard. Click NEXT in the dialog that comes up. In the second dialog box that appears (Figure 1.1), choose a working directory for your project. It is suggested that you create a folder named FML_eee650 (where F = First Name initial, M = Middle Name initial (use X if no middle name) and L = Last Name initial), and use a folder within that for your working directory (for example, Lab2). This will make it easier to keep track of separate projects. This is the folder in which you should store all your files/work for the remainder of this quarter. The project name as well as the top-level design entity can be named my_decoder. If the directory does not already exist, the Quartus II new project wizard will create it for you. Click YES when this option is presented.
Design of Digital Systems - EEEE 650 Rochester Institute of Technology Url: http://www.rit.edu/~labeee Adapted by Carlos Barrios Page 1 of 22 from EE347 and EE650 labs by Dorin Patru Technical Assistants Office: 09-3248 9/11/2012 Technical Assistants Phone: x5-7092
Figure 1.1 New Project Dialog Box (Page 1)
Another dialog box (Figure 1.2) pops up providing you the option of adding files (if any) to your project. There are no files to add at this point so click NEXT.
Figure 1.2 New Project Dialog Box (Page 2)
You can now select the target device for compilation. Choose the FLEX10K family and ensure all the filters are set to Any. Then select the EPF10K70RC240-4 device as shown in Figure 1.3. Click NEXT.
Figure 1.3 Device selection dialog Box
In step 4 of the new project wizard sequence, third party (EDA) tools can be specified. For these labs, Quartus II will be enough so leave the boxes unchecked. Click NEXT, to finally display all the chosen settings. Click FINISH to complete the project creation process. Your project e.g. my_decoder should now be the main project displayed in the left hand column and the title bar. To build your decoder you will need to open a new VHDL file. Select File New and choose the VHDL File item under the Design Files heading as shown in Figure 1.4. Click OK.
Figure 1.4 New Dialog box
A blank .vhd file window should appear. You are expected to complete the VHDL module by adding the code to describe the behavior of the decoder at this time! The next step assumes you have completed this. When the module has been completed, save the file as my_decoder.vhd in the folder you chose earlier. Make sure you check the box Add File to Current Project. Shown in Figure 1.5.
Figure 1.5 Design saving procedure
Go to the Processing menu and click on Compiler Tool, and select Start. If there are any errors locate and fix them. Carefully examine all warnings! Some warnings may be expected. A compilation free of errors and an understanding of all warnings must occur to continue.
Figure 1.6 Compiler Tool
Behavioral simulation using a test bench and the Altera Simulator Test Bench Notes After the design of any circuit, it is imperative that the circuit be tested for proper operation; this is done using a test bench. For any non-trivial circuit, test benches can test large numbers of input and output combinations; it would be a tedious task to manually test each input/output pair. Using the Quartus Simulator, a test bench can be developed to test and report any failures. Develop a test bench using structural VHDL that instantiates the decoder component as the unit under test. The test bench will have a process to test all input combinations and asserts that the output matches the expectation. For example, an exhaustive test bench for a two out of five bit detector (output of circuit is high when exactly 2 bits out of 5 are set) is shown on the next page.
-- Author: Matthew Hosking -- Created: 09/08/08 -- VHDL'93 -- Description: Test Bench for a two out of five (2/5) detector library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; -- required for CONV_* functions use ieee.std_logic_unsigned.all; -- Entity Declaration (This is empty for test benches!) entity detect_2_5_TB is end detect_2_5_TB; architecture beh_TB of detect_2_5_TB is component detect_2_5 is port( a,b,c,d,e : in std_logic; end component detect_2_5;
: out std_logic );
signal sInputs : std_logic_vector(4 downto 0); signal sOutput : std_logic; constant delay : time := 50 nS; begin uut : detect_2_5 port map( a => sInputs(0), b => sInputs(1), c => sInputs(2), d => sInputs(3), e => sInputs(4), y => sOutput ); test_verify : process variable temp : std_logic_vector(4 downto 0); begin -- 'i' emulates the 5 bit input signal for i in 0 to 31 loop sInputs <= CONV_STD_LOGIC_VECTOR(i,5); wait for delay; temp := (CONV_STD_LOGIC_VECTOR(i,5)); -- Mathematical algorithm to verify uut if (CONV_INTEGER(sOutput) = 1) or (i = 0) then assert (CONV_INTEGER(sOutput)*2 = CONV_INTEGER(temp(0))+ CONV_INTEGER(temp(1))+CONV_INTEGER(temp(2))+ CONV_INTEGER(temp(3))+CONV_INTEGER(temp(4))) report "Output not as expected at i=" & integerimage(i) severity FAILURE; else assert (CONV_INTEGER(sOutput)*2 /= CONV_INTEGER(temp(0))+ CONV_INTEGER(temp(1))+CONV_INTEGER(temp(2))+ CONV_INTEGER(temp(3))+CONV_INTEGER(temp(4))) report "Output not as expected at i=" & integerimage(i) severity FAILURE; end if; end loop; report "Test bench completed!"; wait; -- Wait forever to end simulation end process test_verify; end beh_TB;
Assert statements A test bench can use assert statements to compare expected results to actual results. If there is a discrepancy, the assert statement prints a message and can optionally halt the simulation. There are different priority levels for assert statements that control the simulation in different ways. Assert statements provide a way to declare the expected value of a signal. In general, with an assert statement, you make a claim about a condition that should be true if everything is
working. If it turns out that your claim is false, the assert statement will cause the simulator to print a message stating that your assertion has been violated (or has failed). Depending on the severity, the simulation may also stop at that point. An assert statement can be thought of as a reverse IF-THEN statement. When using an IF-THEN statement, the code inserted in the THEN portion is implemented when the IF portion is true. When using assert statements, the message is output to the screen (the REPORT message and SEVERITY are implemented) when the claim is false. This means that the value that you want to include in the assert statement is the expected value for that particular signal. Here is the format for assert statements:
ASSERT ( claim ) REPORT " message " -- ( If claim is violated ) SEVERITY ( FAILURE / ERROR / WARNING / NOTE );
Typically, a severity of FAILURE or ERROR will cause the simulation to halt after printing the REPORT message. A severity of WARNING or NOTE will print the report but continue the simulation. To write your test bench you will need to open a new VHDL file. Select File New and choose the VHDL File item under the Design Files heading as shown in Figure 1.7. Click OK.
Figure 1.7 New Dialog box
A blank .vhd file window should appear. You are expected to complete the VHDL test bench module at this time by adding the code to create the test bench! The next step assumes you have completed this. When the module has been completed, save the file as my_decoder_TB.vhd in the folder you chose earlier. To keep things clean, note that the name should match the entity declaration name you used in the test bench. Make sure you check the box Add File to Current Project. Now it must be specified as a test bench file. Make sure the test bench file is currently selected, and go to File File Properties and choose the VHDL Test Bench File item under Type. Before simulating, you must configure the NativeLink settings. Note that this is done ONCE PER PROJECT and the information is stored with the project information. Select
Assignments Settings. The Settings dialog box appears. In the Category list, select EDA Tool Settings Simulation. The Simulation page appears. In the Tool name list, select ModelSim-Altera. Format for output netlist should be set to VHDL, and the output directory to simulation/modelsim. Under the NativeLink settings, select Compile test bench, and click on the Test Benches button. A screen appears where you can specify the settings for each test bench. Click on New Choose a name for the test bench. Then fill the top level module in test bench field with the entity name you used in your test bench, which should be my_decoder_TB. Also fill the Design instance name in test bench with the name used in the test bench, which should be uut. Select the simulation period to be 500ns. This run time might need to be different depending on the timing values used in your test bench. Under the Test Bench Files, browse for the test bench you wrote, and click on Add. Then click OK.
Figure 1.8 New Test Bench Settings
Figure 1.9 EDA Simulation Tool Settings
Now, we need to tell Quartus where the EDA Tools executable path is. This will only need to be done once, BUT since lab computers are re-imaged often, its good to check and make sure the path is still correct. Go to Tools Options General EDA Tool Options and under ModelSim-Altera, you can specify the path. On lab computers the path should be: C:\altera\81\modelsim_ae\sin32aloem\modelsim.exe. Click OK. Make sure that the task flow is set to Compilation. Compile the circuit for a functional simulation by selecting Processing Start Compilation. After a full compilation is successful, launch the ModelSim-Altera simulator by selecting Tools Run EDA Simulation Tool EDA RTL Simulation. ModelSim-Altera will display a splash screen. ModelSimAltera will load libraries and compile the project. The transcript pane at the bottom of the screen indicates the scripts that have been run (or are running). If everything has been set up correctly and nothing fails, the simulation should start and finish to completion. Under the workspace pane, in the library tab, your work library will contain two VHDL files; your circuit and your test bench. Select both and right click to compile both.
Figure 1.10 ModelSim-Altera Workspace Pane
Select Simulate Start Simulation to put ModelSim-Altera in simulator mode. The Start Simulation Window appears. The Start Simulation window contains many tabs. The Design tab lists the designs available for simulation; most are system libraries. At the top of list will be work (default name for the library containing your program), expand work by selecting the '+'.
Figure 1.11 ModelSim-Altera Start Simulation Window
All components in your design will be listed, select the component that is the testbench and select OK. This will bring up other panes. The left hand side of the screen should now contain a sim tab that displays the design units in your circuit and the supporting libraries. When a design unit is selected in the sim tab, the corresponding signals are shown in the objects window on the right hand side of the screen. Signals that are preceded with a plus (+) sign indicate a bus (a group of wires with common function). For each signal that you want to add to the simulation, right click on the signal name in the Objects window and select Add To Wave Selected Signals. Typically, you would want to add all inputs and outputs. A waveform window will appear in the work area.
Figure 1.12 ModelSim-Altera Objects Pane
Alternatively, you can add a range of signals at once by selecting the 1st signal and then, while holding down the shift key, select the last signal in the range. Then right click in the selected signal region and select Add To Wave Selected Signals. When all signals are selected, expand the Wave window. You can undock the Wave window by using the middle button on the top right side of the Wave pane. This will allow you to expand the Wave window so it is easier to see. Expand the detached window. Select the run time by selecting Simulate Run Time Options and selecting the default run time to be 500ns. This run time might need to be different depending on the timing values used in your test bench. Run the simulation by selecting Simulate Run Run -All You should see the inputs that you entered and the outputs from your system on the waveform. The period of the run will correspond to the time in the period window. All signals should be green. If any signals are red,
then one or more of the inputs was not specified. Also note that the simulation might stop (depending on the severity chosen) and show a red time marker whenever an assert statement failed.
Figure 1.13 ModelSim-Altera Wave Window
Once finished, show your results to the lab TA. Then close the wave window and close ModelSim-Altera. In Quartus, run the timing analyzer tool by selecting Processing Classic Timing Analyzer Tool Once the Timing Analyzer Tool shows up, click on Start. Once the analyzer finishes, click on Report. The timing analyzer summary shows up. Examine the worst case delays between inputs and outputs. Also click on the tpd tab under the Timing Analyzer compilation report, and examine the delays.
Figure 1.14 Timing Analysis Report (Summary)
Figure 1.15 Timing Analysis Report (tpd)
Gate-Level simulation adds timing delays to the output model so that the simulation can include exact timing analysis for the module and the targeted FPGA device. Launch the ModelSimAltera simulator by selecting Tools Run EDA Simulation Tool EDA Gate Level Simulation. ModelSim-Altera will again display a splash screen. If everything has been set up correctly and nothing fails, the simulation should start and finish to completion. For each signal that you want to add to the simulation, right click on the signal name in the Objects window and select Add To Wave Selected Signals. Typically, you would want to add all inputs and outputs. Expanding the decoder test bench block (should be named uut) to see sub-modules will display many entries. These are exact models of the FPGA hardware the module will be deployed on for in-circuit verification. Notice that you can probe the separate signals going into the cells. A waveform window will appear in the work area. When all signals are selected, expand or undock the Wave window. Now, run the simulation again. The waveform will look similar but notice the outputs no longer change simultaneously with the inputs, you should now see simulation results which contain the gate delays. These gate delays should correspond to the results you obtained from the Classic Timing Analyzer Tool.
Figure 1.16 ModelSim-Altera Wave Window
Once finished, show your results to the lab TA. Then close the wave window and close ModelSim-Altera. Configuring the design on an FPGA Plug in the Altera UP1/2 development board to the workstation using the parallel cable and plug the power adapter into an available outlet.
Now we will download the design to the Altera UP1/2 boards. For the decoder, the following pin assignments will be carried out: I/O Pin Enable Data1 Data0 EQ3 EQ2 EQ1 EQ0 Switch FLEX_PUSH_BUTTON2 FLEX_SWITCH-2 FLEX_SWITCH-1 Right digit, segment d Right digit, segment c Right digit, segment b Right digit, segment a Flex 10K Pin 29 40 41 20 19 18 17
Table 1.2 Decoder Pin Assignments
Note that the outputs of the decoder will be connected to the LEDs on the UP1/2 board and the LEDs on the boards are active-low, meaning they need a low signal (0V) to turn on. The Push Buttons on the UP1/2 are also active-low. Select Assignments Pins. All known pin names should display in the bottom window pane (called All Pins) when filtered with Pins: all. You may need to expand this pane to make it visible. In the Location column (Figure 1.17) simply double-click on a box next to any of the signals and type the desired pin number, e.g., type PIN_41 for Data[0]. Choose the pin from the menu. Repeat this procedure for all the pins using Table 1.2 as a reference. The resultant table should look like Figure 1.17.
Figure 1.17 Pin Assignment Window
Compile the circuit and then go to the Tools Programmer. Figure 1.18 should appear (the text next to Hardware Setup will possibly indicate No Hardware). Click on the Hardware Setup button and ensure that the ByteBlasterII[LPT1] hardware is selected then click CLOSE. The Hardware configuration should now be updated with the ByteBlasterII[LPT1]; next check the box under Program/Configure. (If the hardware configuration says ByteBlasterMV, this is fine also.)
Figure 1.18 Programmer Dialog box
Make sure the jumpers on the UP1/2 board are set in the correct position to download to the FLEX10K.
Figure 1.19 Correct Jumper Setting for Downloading to the FLEK10K
Click the Start button and if everything goes correctly, the board will program. Set switch 1 and 2 to all the different positions to generate the binary sequences from Table 1.1, and verify the correct output by pressing the ENABLE button (PB2) and observing the LED outputs. Remember that the LEDs are active low: LED off equates to a 1 signal and LED on
equates to a 0 signal. Only one LED should be off at a time with the decoder module configured on the FPGA in this manner. This is the final in-circuit verification step for the decoder. Verify correct functionality to the TA before proceeding. Save and close the my_decoder project.
Lab Part 2 - Full Adder Create a new project in QuartusII that implements a full adder with the truth table in Table 1.3. After fixing any compilation errors, create a test bench to test the full adder exhaustively. Follow the same design flow as the decoder: enter and synthesize VHDL module, create a test bench, simulate behavioral model, add pin assignments and generate post place and route model, simulate Post-place and route model, verify module with in-circuit test.
Inputs B 0 0 1 1 0 0 1 1 Outputs Cout Sum 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1
A 0 0 0 0 1 1 1 1
Cin 0 1 0 1 0 1 0 1
Table 1.3: Logic Table for the Full-Adder
Use the 2 dot segments of the 7-segment-displays to display SUM and CARRY-OUT. Use 3 consecutive switches, for example FLEX_SWITCH [6 7 8], to be inputs for A, B, and Carry-In. Show the TA your working system before leaving. Follow the instructions in the lab policy to complete and document your assignment. To archive your project and upload it in the corresponding dropbox on mycourses, Go to Project > Archive Project, use default settings, and create the archive file *.qar. References
EEEE 650 Design of Digital Systems with VHDL Lab #3: Parallel Array Multiplier
Objective In this lab, you will implement a four-by-four, parallel array multiplier, using structural VHDL code. An extra credit opportunity exists to create a scalable design and demonstrate functionality of a 16x16 parallel array multiplier. Background This lab will be based on structural VHDL. A structural architecture consists of an interconnection of components. It is essentially a textual version of a schematic for the architecture. Refer to section 5.5.2 in the course textbook [1] for the various styles of coding in VHDL. This section illustrates various ways to define a four-bit adder in VHDL. The versions of the adder in Figure 5.23 (page 284) through Figure 5.26 (page 288) represent structural VHDL. They define a ripple carry adder as an interconnection of full-adders. A scalable design using generic and generate statements is presented in Figure A.15 on page 801. The design for the full adder itself is given in Figure 5.22 on page 283. Lab Refer to section 5.6 in the course textbook [1]. Study the given design for a multiplier. Using this method create a parallel array multiplier. Create the blocks from figures 5.32b and 5.32c using functional or behavioral design. Once these blocks are created use them in a top level design that structurally connects them. Refer to Fig. 5.32 on page 294. The entity declaration of the multiplier must be exactly as follows, including for the names of the inputs and outputs of the module (you need generics if you do the extra credit):
ENTITY multiplier IS port( Q : in std_logic_vector(3 downto 0); M : in std_logic_vector(3 downto 0); P : out std_logic_vector(7 downto 0)); end ENTITY;
Create a test bench: the test bench should test the 4x4 multiplier exhaustively using assert statements. Simulation will be completed at the behavioral and timing levels, meaning the post place and route models must be used in the simulations. Also, make note of the minimum delay at which the circuit can run without triggering test bench assert statements. After simulation is completed, download the appropriate (4x4 bit or extra credit) Built In Self Test (BIST) files from myCourses. Add your multiplier design (all .vhd files except for the Test Bench) to
the BIST (Built In Self Test) project. Make sure your entity matches the expected component naming. Generate a programming file and demonstrate the in-circuit functionality of the BIST. Segment A from Digit 1 of the 7-segment-display should light up to show the circuit is ON (signal name: test_led_0). Press the push button PB1 (signal name: reset) and verify that both Segments G and D are ON. Segment G should indicate the test is running (signal name: BistDone); Segment D should indicate PASS (LED lit up) or FAIL (LED off) (signal name: BistFail).
Extra Credit Use generic and generate statements to make the multiplier scalable. The width of each factor should be separately controllable. That is, the design easily creates an QSIZE by MSIZE multiplier with a product result of (QSIZE+MSIZE) bits. The textbook [1] contains examples and descriptions of both generics and generate statements in Section A.7.5 and A.8, in figures A.14 and A.15 (pages 799-801). Notes on Generics and Generate Statements Generics act like named constants within an architecture. Generics are declared with an entity, along with a default value for each. A component instantiation can override any of the default values using a generic map. Thus, generics can be used to make parameters in VHDL code. The general format for an entity declaration including both generic declarations and port declarations is shown here.
ENTITY ( <entity_name> ) GENERIC( <generic1_name> <generic2_name> <genericN_name> ); PORT( <port_1_name> : <port_2_name> : <port_N_name> : ); END <entity_name>;
: <generic_1_type> := <default_value_1>; : <generic_2_type> := <default_value_2>; : <generic_N_type> := <default_value_N>
<port_1_mode> <port_1_type>; <port_2_mode> <port_2_type>; <port_N_mode> <port_N_type>
An example of a generic statement is in section A.8 on page 801 (Figure A.15). It is the VHDL source code for a simple shift register. This register can load in parallel data as well as shift in a given bit into the LSB of the register. It outputs the register data in parallel. In this example, the generic width specifies the size of the register in bits. Its default value is four bits but this can be changed when the component is instantiated. The body of a higher-level architecture might use both an eight-bit and a sixteen-bit version of the shift register as follows:
X: shift_reg_n GENERIC MAP ( width =>8 ) PORT MAP ( loadX, shiftX, serial_in_X, D_X, Q_X ); Y: shift_reg_n GENERIC MAP ( width =>16 ) PORT MAP ( loadY, shiftY, serial_in_Y, D_Y, Q_Y );
References
[1] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, Third Edition, McGraw Hill, 2005. [2] J. Hamblen and M. Furman. Rapid Prototyping of Digital Systems - Second Edition. Kluwer Academic Publishers, August 2001.
----------------------- Shift Register ---------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.all; ---------------------------- Entity Declaration --------------------------ENTITY shift_reg_n IS GENERIC ( width :integer := 4 ); -- size of shift register in bits PORT ( parallel_loadh : IN STD_LOGIC; -- enable parallel load shift_enh : IN STD_LOGIC; -- enable shift shift_in_value : IN STD_LOGIC; -- serial data input reg_in : IN STD_LOGIC_VECTOR((width-1) DOWNTO 0); -- parallel data reg_out :OUT STD_LOGIC_VECTOR ((width-1) DOWNTO 0) -- output ); END shift_reg_n; ---------------------------- Architectural body --------------------------ARCHITECTURE behavior OF shift_reg_n IS signal reg : STD_LOGIC_VECTOR ((width-1) DOWNTO 0); BEGIN reg_out <= reg; PROCESS( parallel_loadh, reg_in, shift_enh, reg ) BEGIN IF ( parallel_loadh = '1' ) THEN reg <= reg_in; ELSIF ( shift_enh = '1' and parallel_loadh = '0' ) THEN reg ((width - 1) downto 1) <= reg((width - 2) downto 0); reg(0) <= shift_in_value; END IF; END PROCESS; END behavior;
EEEE 650 Design of Digital Systems with VHDL Lab #4: VGA Interface
Objective The purpose of this laboratory exercise is to introduce graphics creation using VHDL and an FPGA. This is also a good lesson on how an FPGA can interface with various components using a host board. This lab has three parts. Background Review Chapter 9 of the lab manual [1], which is related to VGA Video Display Generation. In this lab, you will need to use the modules CLOCK_GEN, SVGA_TIMING_GENERATION, and VIDEO_OUT that can be found on the course website. SVGA_DEFINES.v and SVGA_DEFINES_vhdl.vhd are also required as source files in the project. Some of these are Verilog source files but QuartusII supports mixed designs containing both Verilog and VHDL. Chapter 9 in the lab manual reviews similar VGA modules and explains the internal workings of VGA drivers. This lab provides a vertical bouncing ball VHDL example (main_vhdl.vhd and xilinx_ball.vhd and vga_vhdl.ucf) to start designing. Specification Part 1 Create a project and add the source files provided for the vertical bouncing ball example. Synthesize and implement the design in QuartusII. Verify the assignment of the outputs to the correct FPGA pins as listed in Section 9.6 of [1]. Generate a programming file and configure the device. Connect the VGA monitor to the Virtex-II Pro development board. A red square traveling vertically and bouncing off of the top and bottom of the screen should appear on the monitor. Part 2 Rewrite the bouncing ball example so that the ball travels horizontally and bounces off of the left and right sides of the screen. Be aware of signed versus unsigned interpretations of signals.
Part 3 Create a new project design that implements a two-digit seven segment display instead of one bouncing object. The provided source files for driving the VGA output need to be included as source files. The design will represent a two-digit display, each digit composed of seven segments plus an additional decimal point. The system will have two 8-bit inputs, DISPH and DISPL. Each bit of the inputs will control one segment of the display. Test the design by assigning fixed 8-bit numbers to the DISPH and DISPL and verifying the desired numbers are displayed correctly. Next, create a decoder which will convert a given 4-bit binary number to be displayed into the 8-bit code which will toggle the appropriate segments for this number to be displayed appropriately. Test the seven segment display and decoder by attaching them to the output of the previously designed multiplier. Map the switches as follows: The first 4-bit number should be the high-order switches. These should be on the left, and therefore use the FLEX_SWITCH [1 2 3 4]. The second 4-bit number is the low-order set of switches, so these should be on the right. Therefore, use the FLEX_SWITCH [5 6 7 8]. Arrange the switches so that a switch down produces a zero, and a switch up produces a one. Verify that the correct answer is displayed properly on the VGA monitor. Demonstrate the design to the TA. References
[1] J.O. Hamblen and M.D. Furman. Rapid Prototyping of Digital Systems: A Tutorial Approach. Kluwer Academic Publishers, 2001.
EEEE 650 Design of Digital Systems with VHDL Lab #5: State Machines and Keyboard Interfacing
Objective This laboratory exercise introduces the implementation of finite state machines (FSMs) in VHDL. The circuit to be designed monitors input from a PS2 keyboard connected to the Altera UP1/2 development board. This circuit will serve as the input front end of the video game to be designed in the next lab. Finite State Machines in VHDL Chapter 8 of the text book [1] discusses state machines in detail. State machines are embedded within a process block in VHDL. A process is re-evaluated when the sensitivity list is triggered. The finite state machine (FSM) will implement the state it is currently in every time the process is implemented. Each state should include code that the user wishes to implement when the state is triggered as well as code to determine which state to transfer to next. Appendix A is an excerpt from the text book [1] and gives a generic VHDL code sample of a FSM. Specification Design a circuit that monitors the four arrow keys on a PS2 keyboard connected to the Altera UP1/2 board. The output of the circuit should be connected to 4 segments of a 7-segment display (Use segments A, B, G and F of Digit 2). There must be a separate LED for each of the four arrow keys. For each key, the corresponding LED of the display must be illuminated when and only when its key is down. Each key must be tracked independently. For example, if both the left and up arrow keys are currently down, the segments for both of those keys must be illuminated. If this is implemented correctly, the user will get the impression that each arrow key is a push button that is directly connected to its LED. However, Section 3 demonstrates that interfacing with a PS2 keyboard will require a sequential circuit. PS2 Keyboard Interface Chapter 10 of the lab manual [2] discusses interfacing to a PS/2 keyboard and presents a module called keyboard that handles the low-level details of serial-to-parallel conversion. The most important points to understand from that chapter are: 1. More than one key on a keyboard can be down at the same time. Therefore, the PS2 keyboard detects events and sends a code when an event occurs. Each key has its own make code and break code. When the user pushes down on a key K, the keyboard sends the make code for key K. When the user releases key K, the keyboard sends the break code for key K.
2. Each code is a sequence of multiple bytes. Therefore, you must implement a sequential circuit, preferably a finite-state-machine (FSM), to detect when each code has been sent from the keyboard. 3. Each byte is actually sent serially as a sequence of bits. Fortunately, you are provided with a keyboard module that handles the low-level details of the serial-to-parallel conversion to provide you with a byte at a time. Make sure that you understand the interface to this module. References
[1] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, Third Edition, McGraw Hill, 2005. [2] J. Hamblen and M. Furman. Rapid Prototyping of Digital Systems - Second Edition. Kluwer Academic Publishers, August 2001.
A FSM Code Example from [1]

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY simple IS PORT(clock, resetn, w :IN STD_LOGIC; Z :OUT STD_LOGIC); END simple; ARCHITECTURE behavior OF simple IS TYPE State_type IS(A,B,C); SIGNAL y: State_type; BEGIN PROCESS(resetn, clock) BEGIN IF resetn = '0' THEN y <= A; ELSIF(clock'EVENT AND clock = '1')THEN CASE y IS WHEN A => IF w = '0' THEN y <= A; ELSE y <= B; END IF; WHEN B => IF w = '0' THEN y <= A; ELSE y <= C; END IF; WHEN C => IF w = '0' THEN y <= A; ELSE y <= C; END IF; END CASE; END IF; END PROCESS; Z <= '1' WHEN y = C ELSE '0'; END behavior;
EEEE 650 Design of Digital Systems with VHDL Lab #6: Pong
Objective The project will be to create the game Pong. For those of you who do not remember this 1970s game, it is basically a two dimensional version of table tennis. This project is to be coded entirely in VHDL. Schematic entry may be used to interface the keyboard and VGA sync modules previously created, or else this can be done structurally in VHDL. A written report is also required as part of this lab exercise! See the separate handout under Labs/Pong/Written Report/Assignment for specifics. Lab One example of the top level black box entity for the basic design is:
ENTITY pong IS PORT( -- User interface controls SIGNAL PB1, PB2, Clock : IN std_logic; SIGNAL paddle_up, paddle_dn : IN std_logic; -- VGA interface ports SIGNAL pixel_clock : IN std_logic; SIGNAL pixel_count0 : IN std_logic_vector(10 downto 0); SIGNAL line_count0 : IN std_logic_vector(9 downto 0); SIGNAL vga_red_data : OUT std_logic_vector(7 downto 0); SIGNAL vga_green_data : OUT std_logic_vector(7 downto 0); SIGNAL vga_blue_data : OUT std_logic_vector(7 downto 0) ); END pong;
These are all signals to or from the KEYBOARD and VGA modules, except for reset and clock. Use push button RIGHT for the reset. You may declare your own ports and building blocks as you complete a design. Use the keyboard state machine created earlier for an input to the pong circuitry. The up and down keys should control your paddle. You can just instantiate your state machine as a component in this new code, or copy/paste the relevant section of code.
Game Specifications - The player paddle must move in the Y-direction only, and it must stop at the edges of the screen and be controlled by the up and down arrow keys. - The ball must be able to move in two dimensions and differ in color from the paddles. - The ball must bounce off of the paddle and upper/lower walls in a realistic manner.
- The game must stop when the ball goes out of bounds (left or right edges of screen). The ball will remain stationary until the game is reset to play again. Some Game Over indication is also required (such as changing the background color) to distinguish a game over condition from a faulty implementation. - The second player paddle must be controlled by the computer. The AI can be as simple or as complicated as you want. The paddle can just track the balls Y-position if you would like. Having a computer that is beatable would be nice but it is not a requirement. - Reset should reinitialize the game so that you can keep playing.
These are the minimum requirements. Feel free to make this as complicated as you would like. Some possible simple enhancements are: - Keep score and display the score to the user on the VGA monitor. - Make the ball bounce off at different angles and speeds depending on where it hits the paddle. - Improve the computers AI. Much more is possible. Use your imagination! Up to an additional 50% of the demo portion of the pong lab is available as extra credit. This is not a small project, so do not wait until the last minute. Feel free to contact the Teaching Assistant with questions related to the VHDL or game requirements.
EEEE 650 Design of Digital Systems with VHDL Lab #7: Simple Processor
Objective
The purpose of this laboratory exercise is to design a simple processor with 16 instructions. Two simple programs will be programmed on the processor: bitwise operands test and four bit multiplication. A test bench will be written to verify the multiplication program and both circuits will be demonstrated on the Altera UP 1/2 FPGA development board.
Background Processor Architecture This simple processor performs an infinite loop of fetching the next instruction and executing the instruction. The processor maintains an eight bit program counter (PC) containing the address in memory of the next instruction to execute. During the first phase, instruction fetch (IF), the processor simultaneously increments the PC and decides what action to take based on the instruction in memory at the address specified by the old value of the PC. The memory is an array of 256 words. Each word is four bits wide. This is easily modeled as an array of std_logic_vector(3 downto 0) in VHDL. Table 6.1 shows the registers in the processor, each of which can be modeled as a signal in your code. Placing the signal assignment inside a clocked process will create the necessary register.
Diagram
3 2 A 3 2 B 0 C 7 6 5 4 3 PC 3 MA MAH 3 MAL 2 1 IR 0 2 1 0 1 0 1 0
RTN
A<3..0>
Description
Destination and one operand for all ALU operations. The other operand for ALU operations that need two operands. Stores the carry out of the most recent arithmetic operation. Program Counter holds address of next instruction to execute.
B<3..0>
PC<7..0> 2 1 0 MA<7..0> MAH<3..0> := MA<7..4> MAL<3..0> := MA<3..0>
Memory Address register. Holds address for Jump, JumpC, Read, and Write operations. Divided into two four-bit fields, MAH & MAL.
IR<3..0>
Instruction Register. Holds opcode of the currently executing instruction. Holds value displayed (in hexadecimal) on the High-order digit of the 7-segment display. Holds value displayed (in hexadecimal) on the Low-order digit of the 7-segment display.
2 1 0 DISPH 2 1 0 DISPL 2 1 0
DISPH<3..0>
DISPL<3..0>
3 0 1 2 3 252 253 254 255
Memory
M[0..255]<3..0>
Memory (eight-bit address can select from 256 words. Each word is four bits wide).
Table 6.1: Processor Registers
Instruction Set Architecture The instruction set architecture (ISA) defines the required functionality of the processor. Each instruction should be completed exactly as stated. Table 6.2 contains the abstract description of each of the 16 instructions. #
0 1 2 3 4 5 6 7 8
Opcode
0000 0001 0010 0011 0100 0101 0110 0111 1000
Mnemonic
ADD SUB INC DEC NOT AND OR XOR JMPU
RTN Description
C#A ((0#A)+B) C#A ((1#A)-B) C#A ((0#A)+1) C#A ((1#A)-1) A A A A A B B
Comments
Four-bit result gets stored in A. Carry out gets stored in C.
A A B See JMPC below for C= 0 MAH M[PC] : PC PC+1 ; MAL M[PC] : PC PC+1 ; C=0 PC MA A B: B A B A MAH M[PC] : PC PC+1 ; MAL M[PC] : PC PC+1 ; M[MA] A MAH M[PC] : PC PC+1 ; MAL M[PC] : PC PC+1 ; A M[MA] MAH M[PC] : PC PC+1 ; MA<7>=1 A SWH : MA<7>=0 A SWL MAH M[PC] : PC PC+1 ; MA<7>=1 DISPH A MA<7>=0 DISPL A A remains unchanged Write contents of A to memory location Jump Unconditional Jump Conditional 8-bit transfer!!!
9 10 11
1001 1010 1011
JMPC SWAP CPY
12
1100
WR
Read contents of memory location into A
13
1101
RD
Read Input peripheral into A
14
1110
IN
Write contents of A to Output Peripheral
15
1111
OUT
Legend: # concatenate, value transfers to, results in, ; one machine cycle, : simultaneously
Table 6.2 Instruction Set Architecture
Used for: Word 1 Word 2 Word 3
Format 1 ALU ops, COPY, SWAP, PUSH, POP Opcode
Format 2 IN/OUT (D bit specifies left or right) Opcode D
Format 3 Jumps, RD / WR Opcode AddrH AddrL
Table 6.3: Instruction Formats
Table 6.3 illustrates the instruction formats used in our processor. For instructions that use Format 1, the opcode alone is sufficient. The sources, destination, and next address are all implicit. I/O mapped processors implement input and output instructions called IN and OUT to read from the switch inputs and output to the LED display. These instructions use Format 2: the high-order bit of the second word specifies which peripheral to use. If D=0, the peripheral on the right is used. If D=1, the peripheral on the left is used. JMPU, JMPC, RD, and WR use Format 3. For these instructions, MAH contains the high-order four bits of the target address. MAL contains the low-order four bits of the target address. Design Algorithmic State Machine (ASM) Chart Start by drawing an ASM chart for your processor. The only operations that require multiple states for execution are those with multiple sequential operations: RD, WR, JMPU, JMPC, IN, and OUT. Note: If you have worked with this processor before in EE347, you may start from that ASM chart. However, it will be easiest to implement the I/O mapped Von Neumann architecture shown above. Furthermore, for this assignment, you do not need to worry about bus limitations or temporary registers. VHDL Create VHDL for your ASM. We recommend using an approach similar to Section 8.4.1 of the text [1] on page 508. See the code in Figure 8.29 on page 509. Define a symbolic state type just as they do in the figure. You will have a state for Instruction Fetch, and a state for each cycle of execution for each instruction.
Note: You do not need to worry about separating control and data path, or allocating control signals. The VHDL in each state can look just like the concrete RTN for that state of the ASM chart plus something to set the next state. During reset, you initialize the memory, set the program counter to zero, and set the next state to FETCH. During each clock tick you complete the actions required for the current state. During the case for instruction fetch, you need to determine the next state based on the opcode. The opcode is in the memory location pointed to by the program counter. Simulation Assemble the test programs provided in Table 6.4 and Table 6.5. For each program, put the code to initialize the memory into the reset code in the processor itself. Constants can be declared to initialize the memory array as well. Write a test bench that resets the processor, sets example inputs, and checks that the correct outputs are produced. For the multiplier test program (Table 6.4), your test bench must be exhaustive and have assert statements that check the outputs for all 256 possibilities. You can start with your testbench from the combinational multiplier lab and modify it to work with the processor. Note: The processor will only execute one program at a time. The design needs to be resynthesized and implemented for each program! In Circuit Verification For the multiplier source code (Table 6.4): Wrap your processor VHDL code in a top level that connects the DISP outputs from the processor to the binary-to-seven-segment-to-VGA decoders that you created in the VGA lab. Note: DISPH is the high-order digit, so this should be displayed on the left. DISPL is the loworder digit, so this should be displayed on the right. Map the switches and pushbuttons as follows: SWH should be the high-order switches. These should be on the left, and therefore use the FLEX_SWITCH [1 2 3 4]. SWL is the low-order set of switches, so these should be on the right. Therefore, use the FLEX_SWITCH [5 6 7 8]. Arrange the switches so that a switch down produces a zero, and a switch up produces a one. The final arrangement should be such that SWH<3> (msb) is FLEX_SWITCH 1 on the left-most switch, and SWL<0> (lsb) is FLEX_SWITCH 8 on the right. Map the pushbutton FLEX_PB2 to reset. (Make sure that pushing the button leads to an active reset.) Demo the hardware in person to your TA.
For the bitwise code (Table 6.5), map DISPL to the four vertical segments of the right-most 7segment display (Digit 2). Use inverters such that a 1 leads to an LED that is on. The most significant bit, DISPL<3>, should be Segment F. DISP<2> should be Segment E. DISP<1> should be Segment C, and the least significant bit, DISPL<0>, should be Segment B. Use the same switch mappings as for the multiplier program. You do not need the VGA anymore. Recompile your design with the bitwise program from Table 6.5 together with the new LED mappings. When you program the FPGA, set switches to a binary 6 (0110). Now press the button you mapped to reset. You should see the LEDs cycle through the pattern given in the comments of the code in Table 6.5. When you have it working, demonstrate the working processor to your TA. References
I/O mapped Program by Eric Peskin to compute product = X * Y X and Y are four-bit numbers on the input switches The eight-bit product can be displayed in hexadecimal on a seven-segment display. Label Operation Comments Left-hand set of switches. switches_left: .equ F ; switches_right: display_high: display_low: start: .equ .equ .equ IN WR CPY SUB WR CPY RD DEC WR JMPC IN ADD CPY JMPC RD INC WR JMPU SWAP OUT RD OUT JMPU .dw 0 F 0 switches_left count ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
X will be input on these switches. Right-hand set of switches. Y will be input on these switches. High-order digit of display. Low order digit of display. count = X
product_high = product_low = 0 (product_low is in B)
product_high count count done switches_right
loop:
while(count-- > 0) {
product_low = product_low + Y (product_low is in B)
loop product_high product_high loop display_low product_high display_high start 1
if(carry){ product_high = product_high + 1
} (end of iteration)
done:
Display low product (product_low is in B) Display high product
Do it all again Allocate one word of data memory to hold the count of remaining additions to perform. Allocate one word of data memory to hold high-order nibble of product.
count:
product_high:
.dw
Table 6.4: I/O Mapped program for multiplication
I/O mapped Program to test bitwise logic functions Label DISPL: SWL: start: Operation .equ .equ CPY SUB IN INC CPY INC INC INC INC OUT AND INC INC OUT OR OUT XOR OUT NOT OUT JMPU 0 0 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Comments
Lower word of display Lower word of input
SWL
Set switches to x6 A=x7 A=x7, b=x7
DISPL
LEDs = b1011
DISPL DISPL DISPL DISPL start
LEDs = b0101
LEDs = b0111
LEDs = b0000
LEDs = b1111 Do it all again
Table 6.5: I/O program for bitwise logic functions

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EEEE 650 Design of Digital Systems with VHDL Lab #1: Introduction to VHDL

Table 1.1: Logic Table for Decoder

Figure 1.1 New Project Dialog Box (Page 1)

Figure 1.2 New Project Dialog Box (Page 2)

Figure 1.3 Device selection dialog Box

Figure 1.4 New Dialog box

Figure 1.5 Design saving procedure

Figure 1.6 Compiler Tool

Figure 1.7 New Dialog box

Figure 1.8 New Test Bench Settings

Figure 1.9 EDA Simulation Tool Settings

Figure 1.10 ModelSim-Altera Workspace Pane

Figure 1.11 ModelSim-Altera Start Simulation Window

Figure 1.12 ModelSim-Altera Objects Pane

Figure 1.13 ModelSim-Altera Wave Window

Figure 1.14 Timing Analysis Report (Summary)

Figure 1.15 Timing Analysis Report (tpd)

Figure 1.16 ModelSim-Altera Wave Window

Table 1.2 Decoder Pin Assignments

Figure 1.17 Pin Assignment Window

Figure 1.18 Programmer Dialog box

Figure 1.19 Correct Jumper Setting for Downloading to the FLEK10K

Table 1.3: Logic Table for the Full-Adder

: <generic_1_type> := <default_value_1>; : <generic_2_type> := <default_value_2>; : <generic_N_type> := <default_value_N>

<port_1_mode> <port_1_type>; <port_2_mode> <port_2_type>; <port_N_mode> <port_N_type>

A FSM Code Example from [1]

PC<7..0> 2 1 0 MA<7..0> MAH<3..0> := MA<7..4> MAL<3..0> := MA<3..0>

3 0 1 2 3 252 253 254 255

Table 6.1: Processor Registers

1001 1010 1011

JMPC SWAP CPY

Read contents of memory location into A

Read Input peripheral into A

Write contents of A to Output Peripheral

Table 6.2 Instruction Set Architecture

Used for: Word 1 Word 2 Word 3

Format 1 ALU ops, COPY, SWAP, PUSH, POP Opcode

Format 2 IN/OUT (D bit specifies left or right) Opcode D

Format 3 Jumps, RD / WR Opcode AddrH AddrL

Table 6.3: Instruction Formats

product_high = product_low = 0 (product_low is in B)

product_high count count done switches_right

product_low = product_low + Y (product_low is in B)

loop product_high product_high loop display_low product_high display_high start 1

if(carry){ product_high = product_high + 1

Display low product (product_low is in B) Display high product

Table 6.4: I/O Mapped program for multiplication

Set switches to x6 A=x7 A=x7, b=x7

DISPL DISPL DISPL DISPL start

LEDs = b1111 Do it all again

Table 6.5: I/O program for bitwise logic functions

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