Smart Card Reader

UPDATE NOTIFICATION
F8767 0387
Document No.: Document Title:
D2-0198
NCR 56XX/Personas Self-Service Financial Terminals Hardware Module Descriptions
Change No.: Print Date:
21 February 2001
REASON FOR UPDATE: Update Chapters 7-8 and 7-14 to include the new 8-pin motorised smart card reader/writer.
UPDATE INSTRUCTIONS: Replace the front cover with new front cover, dated 0201. Replace the Title Page with new Title Page dated 0201. Remove and discard the Revision Record pages xiii to xx. Insert the new Revision Record pages xiii to xx dated February 2001. Remove and discard Chapter 7.8, pages i through 48. Insert new Chapter 7.8, pages i through 48 dated February 2001. Remove and discard Chapter 7.14, pages i through 56. Insert new Chapter 7.14, pages i through 56 dated February 2001. Replace the back cover with the new back cover dated 0201.
UPDATE INSTRUCTIONS:
NCR 56XX/Personas XX
Self-Service Financial Terminals Hardware Module Descriptions
D2-0198-A 0201
NCR- CONFIDENTIAL AND PROPRIETARY Use Pursuant to Company Instructions
The product described in this book is a licensed product of NCR Corporation. Trademark Information It is the policy of NCR Corporation (NCR) to improve products as new technology, components, software, and firmware become available. NCR, therefore, reserves the right to change specifications without prior notice. All features, functions, and operations described herein may not be marketed by NCR in all parts of the world. In some instances, photographs are of equipment prototypes. Therefore, before using this document, consult with your NCR representative or NCR office for information that is applicable and current. To maintain the quality of our publications, we need your comments on the accuracy, clarity, organization, and value of this book. Address correspondence to: NCR Financial Systems Group Ltd. Information Solutions Dept. Kingsway West Dundee Scotland DD2 3XX Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 By NCR Corporation Dayton, Ohio U.S.A. All Rights Reserved
REVISION RECORD
Contents
Revision Record
Use the following table to check if your manual is up to date. The revision date that appears on each page is given in the last column.
Section Front matter: Front cover Title Page Preface FCC Statement Safety Information Contents Revision Record 1. General Description 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2. PC Core 2.1 2.2 2.3 2.4 2.5 3. Power Supply and Distribution 3.1 3.3 i/ii iii to iv v to vi vii to xii xiii to xx Divider Card 1.1-i to 1.1-12 1.2-i to 1.2-9 1.3-i to 1.3-9 1.4-i to 1.4-8 1.5-i to 1.5-9 1.6-i to 1.6-8 1.7-i to 1.7-12 Divider Card 2.1-i to 2.1-5 FO-1 to FO-4 2.2-i to 2.2-51 2.3-i to 2.3-65 FO-1 to FO-19 2.4-i to 2.4-4 2.5-i to 2.5-1 FO-1 Divider Card 3.1-i to 3.1-12 FO-1 to FO-10 3.3-i 3.3-1 to 3.3-3 FO-1 FO-2 3.4 3.5 3.6 3.4-i to 3.4-6 3.5-i to 3.5-8 FO-1 to FO-2 3.6-i to 3.6-6 1000 March 2000 December 1996 November 1994 October 2000 October 2000 Undated June 1991 April 1991 Undated Undated Undated Undated Undated Undated September 1991 September 1991 Undated May 1996 July 1991 Undated Undated Undated Undated May 1996 December 1991 Undated November 1992 November 1992 Undated November 1992 June 1991 March 1992 October 1991 Chapter Page Number Date
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REVISION RECORD
Section Chapter 3.7 3.8 3.9 3.10 4. High Order Communications 4.1 Page Number 3.7-i to 3.7-10 3.8-i to 3.8-13 FO-1 to FO-6 3.9-i to 3.9-17 FO-1 to FO-3 3.10-i to 3.10-26 Divider Card i to iv 4.1-1 to 4.1-24 4.1-25/26 4.1-27 to 4.1-42 4.1-43/44 4.1.45 to 4.1-54 FO-1 to FO-13 4.1 Appendix A 4.2 4.3 4.6 4.7 5. Audio, Video, & Graphics 5.1 4.1-A-i to 4.1-A-52 4.2-i to 4.2-7 4.3-i to 4.3-74 FO-1 to FO-8 4.6-i to 4.6-10 4.7-i to 4.7-51 FO-1 to FO-7 Divider Card 5.1-i/ii 5.1-1/2 5.1-3 to 5.1-22 FO-1 to FO-3 5.1 Appendix A 5.1-A-i i to vii 1-1 to 1-3 2-1 to 2-3 3-1 to 3-10 4-1 to 4-11 5-1 to 5-14 6-1 to 6-13 7-1 to 7-21 (FO-1) 8-1 to 8-7 (FO-1) 8-9 to 8-11 (FO-2) 8-13 (FO-3) 8-15 to 8-17 (FO-4) 8-19 (FO-5) 8-21 5.1 Appendix B 5.1-B-1 i to vii 1-1 to 1-3 2-1 to 2-4 3-1 to 3-11 4-1 to 4-19 5-1 to 5-22 6-1 to 6-17 7-1 to 7-3 Date December 1993 Undated Undated Undated Undated Undated Undated May 1993 May 1993 April 1995 May 1993 April 1995 May 1993 Undated June 1991 Undated December 1993 December 1993 March 1992 December 1993 December 1993 Undated June 1995 January 1996 June 1995 June 1995 June 1995 Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated June 1995 Undated Undated Undated Undated Undated Undated Undated Undated
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REVISION RECORD
Section Chapter 5.2 5.3 5.4 5.5 Page Number 8-1 to 8-15 5.2-i to 5.2-10 5.3-i to 5.3-27 FO-1 to FO-9 5.4-i to 5.4-6 5.5-i to 5.5-5 FO-1 FO-2 to FO-4 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.6-i to 5.6-10 FO-1 to FO-4 5.7-i to 5.7-7 5.8-i to 5.8-5 5.9-i to 5.9-42 FO-1 to FO-5 5.10-i to 5.10-32 FO-1 to FO-2 5.11-i to 5.11-42 FO-1 to FO-2 5.12-i to 5.12-4 5.13-i to 5.13-2 5.14-i to 5.14-12 FO-1 to FO-3 5.15-i to 5.15-10 i 5.16-1 to 5.16-7 5.17-i to 5.17-2 5.17-3 to 5.17-6 5.17-7 to 5.17-12 5.17-13/14 5.17-15/16 5.17-17 to 5.17-22 5.17-23 to 5.17-35 FO-1 to FO-2 5.18 5.19 5.21 5.22 5.26 5.27 6. Printers 6.1 6.1 Appendix A 5.18-i to 5.18-30 FO-1 to FO-3 5.19-i to 5.19-36 FO-1 to FO-2 5.21-i to 5.21-46 5.22-i to 5.22-38 5.26-i to 5.26-58 5.27-i to 5.27-58 Divider Card 6.1-i to 6.1-11 6.1-A-1 i/ii 1-i to 1-3 2-i to 2-28 3-i to 3-91 4-i to 4-5 (FO-1) 4-6 to 4-10 (FO-2) 4-11 to 4-28 (FO-3) Date Undated November 1996 Undated September 1990 Undated December 1991 Undated December 1991 Undated Undated November 1992 December 1991 April 1991 April 1991 June 1991 June 1991 July 1993 July 1993 January 1994 Undated Undated Undated Undated September 1992 September 1992 November 1992 July 1993 November 1992 July 1993 November 1992 July 1993 November 1992 July 1993 October 1999 February 1994 November 1996 December 1992 October 1999 Undated Undated Undated Undated January 1994 Undated Sep. 1991 Undated Undated Undated Undated Undated Undated
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REVISION RECORD
Section Chapter Page Number 4-29 to 4-41 5-i FO-1 to FO-3 FO-4 to FO-6 FO-7 FO-8 FO-9 FO-10 to FO-12 FO-13 FO-14 FO-15 to FO-18 FO-19 6-i to 6-71 6.2 6.2 Appendix A 6.2-i to 6.2-10 6.2-A-1 i/ii 1-i to 1-3 2-i to 2-19 3-i to 3-90 4-i to 4-28 5-i FO-1 FO-2 FO-3 FO-4 FO-5, FO-6 FO-7 FO-8 FO-9 to FO-11 6-i to 6-46 6.2 Appendix B 6.2 Appendix C 6.3 6.2-B-1 to 6.2-B-7 6.2-C-1 to 6.2-C-6 6.3-i/ii 6.3-iii to 6.3-10 6.3-11 to 6.3-14 6.3-15 to 6.3-31 6.3 Appendix A 6.3-A-1/2 i/ii 1-i to 1-6 2-i to 2-23 3-i to 3-174 4-i to 4-59 5-i FO-1 FO-2 FO-3 FO-4 FO-5 FO-6 to FO-7 FO-8 FO-9 Date Undated Undated Nov. 1988 Dec. 1988 Apr. 1991 Nov. 1990 Apr. 1991 Dec. 1988 May 1992 Jan. 1991 Dec. 1988 May 1992 Undated June 1991 June 1991 May 1990 Undated Undated Undated Undated Undated Apr.1989 July 1989 Mar. 1990 Apr.1989 Feb. 1989 Apr. 1989 Jan. 1989 Apr. 1989 Undated June 1991 June 1991 May 1993 Undated May 1993 Undated Undated Dec. 1994 Undated Undated Undated Undated Undated Oct. 1989 Mar. 1990 Oct. 1989 Jan. 1990 Nov. 1990 Oct. 1989 Nov. 1990 Oct. 1989
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REVISION RECORD
Section Chapter Page Number FO-10 6-i to 6-62 6.3 Appendix B 6.3 Appendix C 6.4 6.5 6.3-B-1 to 6.3-B-7 6.3-C-1 to 6.3-C-7 6.4-i to 6.4-28 FO-1 to FO-6 6.5-i to 6.5-112 6.5-113/114 6.5-115 to 6.5-176 6.5-177 to 6.5-192 6.6 6.6 Appendix A 6.6 Appendix A 6.6 Appendix B 6.6 Appendix B 6.7 6.6-i to 6.6-16 Title page i to 86 Title page i to 96 6.7-i to 6.6-176 FO-1 to FO-2 6.7-A-1 to 6.7-A-26 6.11 6.12 7. Magnetic Card Reader/Writers 7.1 7.2 7.3 7.4 6.11-I to 6.11-2 6.12-i to 6.12-152 Divider Card 7.1-i to 7.1-13 FO-1 to FO-3 7.2-i to 7.2-53 FO-1 to FO-19 7.3-i to 7.3-48 FO-1 to FO-19 7.4-i to 7.4-12 FO-1 to FO-3 FO-4 to FO-6 7.5 7.6 7.5-i to 7.5-8 7.6-i/ii 7.6-1 to 7.6-28 7.6-29 to 7.6-41 FO-1 to FO-6 7.7 7.8 7.7-i to 7.7-61 FO-1 to FO-9 7.8-i to 7.8-42 FO-1 to FO-21 7.8-i to 7.8-48 7.10 7.10-i to 7.10-12 7.10-13/14 7.10-15 to 7.10-18 FO-1 to FO-2 7.12 7.14 8. Encryptors 8.1 8.2 7.12-i to 7.12-16 7.14-i to 7.14-56 7.14-i to 7.14-56 Divider Card 8.1-i to 8.1-19 FO-1 to FO-4 8.2-i to 8.2-18 September 1996 January 1997 June 1995 January 1997 Undated Undated Undated June 1991 June 1991 October 1991 October 1991 October 1991 October 1991 January 1994 November 1992 January 1994 Undated May 1993 Undated May 1993 Undated Undated Undated May 1996 November 1993 February 2001 Undated April 1995 Undated Undated Undated Undated February 2001 Undated June 1991 June 1991 June 1991 December 1996 Date Mar. 1991 Undated Undated Undated Undated Undated June 1999 October 2000 June 1999 October 2000 September 1996
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REVISION RECORD
Section Chapter 8.3 9. Disk Drives 9.1 9.2 9.3 9.4 9.5 10. Input Devices 10.1 10.2 10.3 Page Number FO-1 to FO-4 8.3-i to 8.3-12 Divider Card 9.1-i to 9.1-7 9.2-i to 9.2-2 9.3-i to 9.3-6 9.4-i to 9.4-8 9.5-i to 9.5-7 FO-1 to FO-2 Divider Card 10.1-i to 10.1-7 10.2-i to 10.2-5 10.3-i to 10.3-8 10.3-9 to 10.3-12 10.3-13 to 10.3-16 FO-1 to FO-23 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.12 10.13 11. Miscellaneous Interfaces 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.14 Appendix A 12. Currency Handling 12.1 10.4-i to 10.4-11 FO-1 to FO-12 10.5-i to 10.5-22 10.6-i to 10.6-18 FO-1 to FO-6 10.7-i to 10.7-6 FO-1 10.8-i to 10.8-15 FO-1 to F0-10 10.9-i to 10.9-3 10.10-i to 10.10-8 10.12-i to 10.12-36 10.13-i to 10.13-14 Divider Card 11.1-i to 11.1-22 FO-1 to FO-14 11.2-i to 11.2-3 11.3-i to 11.3-4 11.4-i to 11.4-2 11.5-i to 11.5-3 11.6-i to 11.6-7 11.7-i to 11.7-5 11.8-i to 11.8-6 11.9-i to 11.9-6 FO-1 to FO-2 11.10-i to 11.10-15 FO-1 to FO-4 11.11-i to 11.11-4 11.12-i to 11.12-3 11.13-i to 11.13-11 FO-1 to FO-4 11.14-i to 11.14-77 11.14-A-i to 11.14-A-51 Divider Card 12.1-i to 12.1-130 Date June 1991 Undated Undated May 1996 March 1996 March 1996 October 2000 January 1992 June 1996 Undated May 1993 May 1993 Undated July 1993 Undated Undated June 1991 June 1991 March 2000 March 1996 Undated Undated Undated Undated Undated Undated October 1994 Undated Undated Undated November 1990 Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated Undated
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REVISION RECORD
Section Chapter 12.2 12.3 12.4 12.5 12.6 12.6 Appendix A 12.8 Page Number FO-1 to FO-26 12.2-i to 12.2-36 12.3-i to 12.3-14 12.4-i to 12.4-42 12.5-i to 12.5-135 FO-1 to FO-25 12.6-i to 12.6-xii 12.6-1 to 12.6-282 12.6-A-i to 12.6-A-10 12.8-i to 12.8-172 Divider Card 13.1 13.1-i/ii 13.1-1 to 13.1-30 13.1-31 13.1-34 13.1-35 to 13.1-40 FO-1 to FO-13 13.2 13.3 13.4 14.1 14.1 Appendix A 14.2 14.3 14.4 14.5 14.6 14.7 15. HI3 15.1 15.1 Appendix A 15.2 15.3 15.4 15.4 Appendix A 15.5 15.6 16. Document Processing 16.1 16.2 13.2-i to 13.2-24 13.3-i to 13.3-37 FO-1 to FO-12 13.4-i to 13.4-56 14.1-i to 14.1-58 FO-1 to FO-66 14.1-A-i to 14.1-A-88 14.2-i to 14.2-9 FO-1 to FO-5 14.3-i to 14.3-11 FO-1 to FO-8 14.4-i to 14.4-8 FO-1 14.5- i to 14.5-8 FO-1 to FO-4 14.6-i to 14.6-6 FO-1 to FO-2 14.7-i to 14.7-10 FO-1 to FO-4 Divider Card 15.1-i to 15.1-92 FO-1 to FO-38 15.1.A-1 to 15.1.A-182 15.2-i to 15.2-33 FO-1 to FO-8 15.3-i to 15.3-4 15.4-i to 15.4-136 15.4.A-i to 15.4.A-110 15.5-i to 15.5-24 15.6-i to 15.6-4 Divider Card 16.1-i to 16.1-134 16.2-i to 16.2-10 14. Terminal Control Module (ISA Bus) Divider Card Date Undated August 2000 March 2000 September 1995 Undated Undated March 2000 May 1996 Undated Undated Undated Undated November 1992 May 1993 November 1992 Undated June 1995 Undated Undated October 2000 Undated December 1992 December 1992 December 1992 Undated Undated Undated Undated October 1991 October 1991 March 1996 Undated Undated Undated May 1996 Undated Undated Undated Undated Undated July 1993 July 1993 Undated Undated Undated Undated Undated Undated June 1995 Undated
13. Depository and Envelope Dispensers
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REVISION RECORD
Section Chapter Page Number 16.2-11/12 16.2-13 to 16.2-82 16.3 17. Standard PC Core 17.1 18. NLX PC Core 18.9 Back Matter Readers Comment Form Back Cover 0699 1000 16.3-i to 16.3-52 Divider Card 17.1-i to 17.1-18 Divider Card 18.9-i to 18.9-36 Date January 1996 Undated Undated Undated Undated Undated Undated
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SMART CARD READER/WRITER
Contents
Smart Card Reader/Writer
Chapter 7.8
INTRODUCTION ........................................................................................................ 7.8-1 GENERAL DESCRIPTION ......................................................................................... 7.8-1 FUNCTIONAL DESCRIPTION .................................................................................. 7.8-2 SCRW MODULE ......................................................................................................... 7.8-3 MECHANICAL OPERATION ............................................................................... 7.8-3 SOFTWARE OPERATION ................................................................................... 7.8-4 Modes of Operation............................................................................................. 7.8-4 Card Entry ........................................................................................................... 7.8-4 Normal Sequence ................................................................................................ 7.8-4 ELECTRICAL OPERATION.................................................................................. 7.8-4 Input Signals........................................................................................................ 7.8-4 Output Signals ..................................................................................................... 7.8-5 Contacts (16 Pin) ................................................................................................. 7.8-5 Contacts (8 Pin)................................................................................................... 7.8-5 Power Requirements ........................................................................................... 7.8-6 PRE-EMV SCIF BOARD ............................................................................................ 7.8-7 SCIF CORE ELECTRONICS ................................................................................. 7.8-7 Processor and Support Circuitry ......................................................................... 7.8-7 Memory and Address Decode ............................................................................. 7.8-8 Level 0 Diagnostics............................................................................................. 7.8-9 INTERFACES ......................................................................................................... 7.8-9 Power Interface ................................................................................................. 7.8-10 PIA Interface ..................................................................................................... 7.8-10 SCRW Interface ................................................................................................ 7.8-13 Smart Card Interface ......................................................................................... 7.8-15 Power Fail Interface .......................................................................................... 7.8-18 Test Connectors................................................................................................. 7.8-19 ERROR CODES AND DIAGNOSTICS.................................................................... 7.8-20 LEVEL 0 DIAGNOSTICS .................................................................................... 7.8-20 Switch Settings.................................................................................................. 7.8-20 LEDs.................................................................................................................. 7.8-20
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Test Descriptions SCIF ..................................................................................... 7.8-21 Test 01 - CPU and EPROM .............................................................................. 7.8-21 Test 02 - External Data Memory....................................................................... 7.8-22 Test 03 - External Data Memory Address and Data Lines ............................... 7.8-22 Test 04 - NVRAM Initialize.............................................................................. 7.8-23 Test 06 - Smart Card Contacts and Communication......................................... 7.8-23 Test 10 - Card Vpp Slow Staircase ................................................................... 7.8-24 Test 11 - Card Vpp Fast Sawtooth .................................................................... 7.8-24 Test 12 - Card Vpp = 5.0 Volt........................................................................... 7.8-25 Test 13 - Card Vpp = 21.0 Volt......................................................................... 7.8-25 Test 14 - Card Clock = 1 x 3.579545 MHz....................................................... 7.8-25 Test 15 - Card Clock = 2 x 3.579545 MHz....................................................... 7.8-26 Test 16 - Card Clock = 4 x 3.579545 MHz....................................................... 7.8-26 Test 17 - Card Clock = 1 x 4.9152 MHz........................................................... 7.8-26 Test 18 - Card Clock = 2 x 4.9152 MHz........................................................... 7.8-26 Test 19 - Card Clock = 4 x 4.9152 MHz........................................................... 7.8-27 Test 1A - Card Reset Toggle............................................................................. 7.8-27 Test 1B - Card Input/Output Toggle ................................................................. 7.8-27 Test 1C - Card Vcc Toggle ............................................................................... 7.8-27 Test 1D - Exercise Stopper Pin ......................................................................... 7.8-28 Test 1E - Exercise Contact Unit ........................................................................ 7.8-28 Test Descriptions EMV-SCIF ........................................................................... 7.8-29 Test 01 - CPU and EPROM .............................................................................. 7.8-29 Test 02 - External Memory ............................................................................... 7.8-30 Test 03 - External Data Memory Address and Data Lines ............................... 7.8-30 Test 04 - NVRAM Initialize Disabled .............................................................. 7.8-31 Test 05 - NVRAM Initialize Enabled ............................................................... 7.8-31 Test 06 - Smart Card Communication Test....................................................... 7.8-31 Test 07 - Card Clock - Stop Low ...................................................................... 7.8-32 Test 08 - Card Clock = XTAL/ 2 MHz ............................................................. 7.8-32 Test 09 - Card Clock = XTAL/ 4 MHz ............................................................. 7.8-32 Test 0A - Card Clock = XTAL/ 8 MHz ............................................................ 7.8-32 Test 0B - Card Clock = FINT/ 2 MHz .............................................................. 7.8-33 Test 0C - Card Stop High .................................................................................. 7.8-33 Test 0D - Card Signal Toggle ........................................................................... 7.8-33 Test 0E - Exercise Stopper Pin.......................................................................... 7.8-33 Test 0F - Exercise Contact Unit ........................................................................ 7.8-34 LEVEL 1 DIAGNOSTICS .................................................................................... 7.8-35 SMART CARD STAGE ................................................................................... 7.8-35 SMART CARD RESET.................................................................................... 7.8-35 SMART CARD RELEASE .............................................................................. 7.8-35 SCIF INITIALISE............................................................................................. 7.8-35 SCIF SOLENOID ............................................................................................. 7.8-35 SCIF IDENTIFY ............................................................................................... 7.8-35 RUN-TO-RUN 1 ............................................................................................... 7.8-36 RUN-TO-RUN 2 ............................................................................................... 7.8-36 RUN-TO-RUN 3 ............................................................................................... 7.8-36 M_STATUS ...................................................................................................... 7.8-37 M_DATA .......................................................................................................... 7.8-38 LEVEL 2 DIAGNOSTICS .................................................................................... 7.8-38 LEVEL 3 DIAGNOSTICS (TALLIES) ................................................................ 7.8-38
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7.8-ii
STRAPPING............................................................................................................... 7.8-40 ADJUSTMENTS ........................................................................................................ 7.8-40 CARD VPP ............................................................................................................ 7.8-40 PD7 SENSE ........................................................................................................... 7.8-40 TEST EQUIPMENT................................................................................................... 7.8-41 DIAGNOSTIC TEST CARDS .............................................................................. 7.8-41 PREVENTIVE MAINTENANCE ............................................................................. 7.8-41 INTERCONNECTIONS ............................................................................................ 7.8-41 SOLENOIDS AND PHOTODETECTOR CONNECTORS ................................. 7.8-42 MOTOR AND SHUTTER CONNECTOR ........................................................... 7.8-43 SDC MCRW TO SCIF PIA INTERFACE BOARD ............................................. 7.8-44 SCIF TO MCRW CONTROLLER PIA CONNECTOR ...................................... 7.8-45 POWER CONNECTIONS .................................................................................... 7.8-46 SMART CARD SIGNALS AND POWER .......................................................... 7.8-47 SCHEMATIC AND ASSEMBLY DIAGRAMS ....................................................... 7.8-47
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7.8-iv
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Contents
Chapter 7.8
Smart Card Reader/Writer
INTRODUCTION
This chapter describes the Smart Card Reader/Writer (SCRW) feature used in NCR 56XX Self Service Financial Terminals to read and write to smart cards and ISO magnetic cards. The smart card feature consists of the following major components:
z The MCRW which may be one of the following types: z SDC Magnetic Card Reader/Writer Track 1-2-3 (described in Chapter z SDC Magnetic Card Reader/Writer Track 2 (described in Chapter 7.3) z 3 Track Write MCRW (described in Chapter 7.7).
7.2).
z The Smart Card Reader/Writer (SCRW) Module (described in this Chapz The Smart Card Interface (SCRW) Board (described in this Chapter).
ter).
GENERAL DESCRIPTION
There are two types of (Smart Card Reader/Writer) SCRW:
z The 16-pin version reads and writes to smart cards and ISO magnetic
cards in compliance with EMV 3.1.1, ISO 7816 (parts 1, 2 and 3) and the AFNOR/CP8 I.C. card standards. z The 8-pin version only reads and writes to smart cards and ISO magnetic cards in compliance with EMV 3.1.1, ISO 7816 (parts 1, 2 and 3) card standards. The SCRW feature adds on to the Magnetic Card Reader/Writer (MCRW) or Magnetic Card Reader (MCR) modules for the 56XX/personaSXX range of NCR Self Service Financial Terminals. The additional electronic functions necessary for reading and writing of smart cards are provided by the Smart Card Interface (SCIF) board which is also attached to the MCRW. When an SCRW module and SCIF are configured in the host machine the SCIF interfaces with the same PIA bus (from the SDC MCRW Interface Board) as the MCRW. A smart card command sent by the host is identified by the SCIF, which then disables the PIA interface to the MCRW and takes control of the MCRW. Once the smart card operation is complete, control is passed back to the host/MCRW interface.
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The following figure shows the SCRW feature attached to an MCRW
FUNCTIONAL DESCRIPTION
The functional description of the SCRW Module and SCIF Board is provided in the following sub-sections: z SCRW Module: z Mechanical Operation z Software Operation z Electrical Operation. z SCIF Board: z PIA Interface z SCRW Interface z Smart Card Interface. In addition to the above interfaces, there are circuits associated with handling power failure and providing test connectors.
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SCRW MODULE
MECHANICAL OPERATION
The figure below shows the components of the SCRW Module:
Contact Solenoid Stopper Pin Solenoid Solenoid Sensors PCB
Flexible Printed Cables
Stopper Pin
Card Sensor
Card Entry Mouth Contacts (8-pin or 16-pin version)
The SCRW attaches to the rear of the MCRW/MCR. The rear transport shaft of the MCRW/MCR is modified to have a double belt pulley turned by a pin through the shaft which creates a half-turn clutch. A rubber wheel on the shaft bears down on a lower nylon wheel to drive a card, passing between them, into the SCRW. The card is pushed against a reference surface on the right-hand side of the SCRW by a flat metal spring attached to the left-hand side. The card is detected in the SCRW by an optical sensor (PD7). A solenoid energizes to lower a pin into the path of the card and stop it in position under a set of spring metal contacts. The action of the solenoid is detected by a photodetector (PD5) looking at a flag on the solenoid arm. With the card correctly in position, a second solenoid is energized to lower the spring metal contacts on to the contact area of the card. Another sensor (PD6) detects the movement of this solenoid. An O-belt from the MCRW rear transport pulley drives a shaft at the rear of the SCRW. This shaft carries a rubber wheel which bears down on a lower nylon wheel to drive cards into the card capture bin. In a normal transaction the card will not reach these drive wheels but remain in the grip of the MCRW rear transport wheels which reverse direction to drive the card back to the cardholder.
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SOFTWARE OPERATION
Control of the SCRW is provided by the Smart Card Interface (SCIF) board which has its own on-board firmware. This firmware communicates with the host SSFT via the SDC MCRW Interface Board, to control the card movement and the operation of the smart card stopper pin and contacts. Modes of Operation At initialization the MCRW/SCRW device driver and the SCIF board adopt MCRW mode. The device driver interrogates the hardware to determine if the SCIF is present and functioning correctly. If all is O.K. the device driver will control the SCRW by sending SCIF commands to the SCIF board (see the section Normal Sequence for a list of SCIF commands). All hardware signals, including MCRW signals, are routed through the SCIF board. When a SCIF command is received by the board, it switches to SCRW mode, produces the associated signals to achieve that command and then switches back into the MCRW mode. The SCIF switches into the SCRW mode for the duration of each SCIF command. Card Entry Card entry is identical to MCRW/MCR card entry. Once the card width and card sense requirements are met and under application control, the card is accepted and staged in the transport by the motor in the MCRW/MCR. A SCIF command is then issued to stage the smart card in the SCRW so that it is ready to be read from or written to. Normal Sequence The normal sequence of events for smart card operation is as follows:
z The MCRW/MCR Accept command stages the card z The SCIF command Stage Smart Card moves the card into the SCRW z The SCIF command Power On Card applies to the card and produces a z The SCIF command Smart Card Direct reads/writes to the card. These z The SCIF command Power Off Card removes power from the card z The SCIF command Release Card moves the card back to the MCRW/
MCR stage position. commands are card specific Response To Reset from the card
ELECTRICAL OPERATION
The electrical logic to control the SCRW is wholly located on the SCIF board as described on the section SCIF Board. Connectors on the SCRW carry the power supplies, the signals from the smart card, the sensor status, and the solenoid control signals, to the SCIF board. Refer to the section Interconnections for pinouts of these connectors. Input Signals The input signals are as follows:
z STP - When this signal goes from 24V to ground, the card stage stopper z TUD - When this signal goes from 24V to ground, the connector lowering
mechanism is activated. pin mechanism is activated
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7.8-4
Output Signals The following TTL compatible output signals are generated:
z PD5 - This signal becomes logically high when the card stopper pin is lowz PD6 - This signal becomes logically high when the smart card contacts are z PD7 - This signal becomes logically high when the smart card is correctly
staged in the SCRW. Contacts (16 Pin) Two rows of eight contacts are lowered on to the card. Of the 16 contacts, eight are in the ISO contact group position and eight are in the AFNOR/CP8 contact group position. The contacts provide power, and read or write, to cards of both the ISO and AFNOR/CP8 formats. Contacts (8 Pin) Two rows of four contacts are lowered on to the card. The contacts provide power, and read or write, to cards of ISO formats only. Smart Card Contacts for ISO The positions of the contacts on an ISO standard card are shown in the figure below, with the position of the magnetic strip (on the underside of the card), shown by dotted lines.
Rear of SCRW Magnetic Stripe
ered
lowered on to the card
1 2 3 4
5 6 7 8
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FEBRUARY 2001
Smart Card Contacts for AFNOR/CP8 The positions of the contacts on a AFNOR/CP8 standard card are shown in the figure below, with the position of the magnetic strip (on the underside of the card), shown by dotted lines.
8 7 6 5
4 3 2 1
Function of Contacts The following table lists the functions of the card contacts.
Signal VCC RST CLK RFU GND VPP I/O RFU Contact No. 1 2 3 4 5 6 7 8 Function Card power supply voltage: Min. = 4.75 V, Max = 5.25 V at 230 mA Reset signal Clock signal Reserved for future use Ground Programming/Erase volts Data input/output Reserved for future use
Power Requirements Power for the SCRW is supplied from the SCIF board for stopper pin lowering, lowering of contacts, and sensor operation. The maximum power required for these functions is shown below.
Voltage +VDD 24 Vdc +VDD 5 Vdc Current 800 mA (operating) 50 mA (operating) Regulation 10% 5% 250 mA p-p
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7.8-6
PRE-EMV SCIF BOARD

PIA Interface Smart Card Interface
SCIF Core Electronics
SCRW Interface
In the following text the functions of the SCIF are described with reference to four areas in the block diagram above.
z z z z
SCIF core electronics PIA interface SCRW interface Smart card interface. In addition the following interfaces are also provided:
z Power interface z Power fail interface z Test connectors.

The schematics for the SCIF Board are included at the end of this chapter. Refer to these schematic diagrams while reading the following circuit description. NOTE: Sheets 4 and 5 of the schematics show a possible future expansion to the interface board. This circuit is not described.
SCIF CORE ELECTRONICS

The core of the SCIF is the controlling electronics which is designed around an INTEL 8 bit embedded controller. The controlling electronics is described in the following subsections:
z Processor and support circuitry z Memory and address decode z Level 0 diagnostics.
Processor and Support Circuitry Refer to schematics sheets 6 and 8 when reading the following text. The processor is an INTEL 8032 8 bit embedded controller operating at a frequency of 12 MHz which is provided by a TTL compatible clock oscillator with a 2K pull up resistor. This clock is also used to drive the smart card encryptor timing circuits. Port 0 of the processor operates as a multiplexed address/data bus with the address latched by the ALE signal. The serial port provides the communication interface with the smart card. The power-up/power-down and reset circuits are provided by a dedicated microprocessor supervisory circuit. (Maxim 691) device which supplies a continuous voltage to the RAM, thereby providing an area of non-volatile memory. A 3.6 volt 1 ampere-hour lithium battery supplies the RAM in the event of a power failure.
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FEBRUARY 2001
Two fast reacting Schottky diodes are incorporated in the series path from the battery to the Maxim 691 device to prevent a possible charging current flowing into the battery. This satisfies UL/CSA safety requirements. A one microfarad capacitor is included in the Maxim output circuit to provide smoothing when switching. The Maxim 691 also provides a reset signal which is used with the powerup cycle. This reset signal, which is active high, lasts for approximately 35 to 70 ms (typically 50 ms). A 2K pull-up resistor ensures a strong reset signal. Memory and Address Decode Refer to schematics sheets 6 and 9 when reading the following text. The memory available on the board consists of 64 KB of EPROM and 32 KB of battery backed RAM. Memory-mapped I/O is located from 8000H upwards. This is above the 32K battery backed RAM. The overall memory map is shown in the following figure.
0FFFFH
Code Area
Data Area
0FFFFH
Not Populated
9000H 8FFFH EPROM I/O 8000H 7FFFH NVRAM 7000H 6FFFH
Not Used
2000H 1FFFH SRAM 0000H 0000H
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7.8-8
Owing to the high population density of the board, all decodes for address locations are performed by a 44-pin PLCC EPLD device. This device has a large number of output ports which allow both RD- and WR- qualification on address selection. The RD- and WR- qualification originates from the processor. Two 0.47 microfarad capacitors decouple the noise from the voltage plane as required by the EPLD internal architecture. The positions of the various ports in the memory-mapped I/O portion of the overall memory map are shown in the following table:
RD/WR RDWRRDRDWRWRWRRDWRRDWRMCRW Port A MCRW Port A MCRW Port B SCRW Status Port SCRW Control Port SMART Card Control Port SMART Card DAC Port SCE Data Port SCE Data Port Switch Pack Level 0 LEDs Level 0 8006H 8003H 8004H 8005H 8001H 8002H Port 9000H Address
Level 0 Diagnostics Refer to schematic sheet 10 when reading the following text. The Level 0 diagnostics are performed using an 8-way switch pack and eight LEDs. The 8-way switch pack U4 is used for setting and running the extended level 0 testing. The appropriate switch setting is obtained by reading memory mapped I/O at address 8006H. When the switch is open a logical low is read and, when closed, a logical high. The 8 LEDs display information about the level zero tests that are being run and also the result of the tests. The LEDs are accessed by writing to memory location 8006H. Each LED can be written to individually. A logical low signal turns the LED on, and a logical high turns the LED off. The switch pack and LED signals are brought out to a DUAL 10-way RDI connector along with a reset signal. This allows the board to be tested using a remote level 0 testing device.
INTERFACES
The SCIF provides the following interfaces:
z Power z PIA z Port A z Port B z SCRW interface z Input port z Output port z Solenoid drivers
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FEBRUARY 2001
z Smart card interface z Smart card programming voltage (VPP) z Digital to analogue conversion z Vpp current limiting z Smart card clock generation z Smart card data (ISO and AFNOR/CP8) z Smart card Vcc z Power fail interface z MVF and MCB sense circuit z MCF and MCB control output z Test connectors z Test evaluation connector z Remote diagnostic interface.
Power Interface Refer to the schematic sheet 7 when reading the following text. Dual 4-way connector J11 provides three power lines (+24V, +12V, +5V) and associated return Grounds. To ensure good noise immunity, these lines are connected directly into the inner planes of the PCB. PIA Interface Refer to the schematic sheets 2 and 3 when reading the following text. The SCIF monitors the PIA interface. When a smart card instruction is recognised the SCIF latches the data to the MCRW and assumes control. The SCIF executes the smart card instruction then passes control back to the host. The PIA interface can be divided into the sections, Port A interface and Port B interface. These are shown in the following figure:
PORT A PORT B
SCIF Bus
Host Buffer 1
MCRW
Host Buffer 4
MCRW
PD7 PD_PD4 Buffer 2 Buffer 5
SCIF Bus
Buffer 3
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7.8-10
Port A Interface Port A is an 8-bit wide directional port which interconnects the following status information:
z z z z
SCIF to host Host to SCIF MCRW to host Host to MCRW.
NOTE: SCIF to MCRW and MCRW to SCIF never occur. The format of the signals is divided into sections A select, B select and C select as shown below. For more information on the signal functions refer to Chapters 7.2, 7.3, or 7.7.
Bit 0 1 2 3 4 5 6 7 A Select DW0 DW1 DW2 DW3 DW4 DW5 DW6 Not Used B Select DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 C Select PD1 PD2 PD3 Busy SW2 SW1 PD7 PD5 - PD6
The schematics (sheet 2 and 3) for the interconnections of Port A, show that a communication link is present between the host and the MCRW and between the host and the SCIF. There is no direct communication between the SCIF and the MCRW. Buffer 1 (a 74F623, U44) provides the interface between the host and the MCRW/SCRW. Buffer 2 (a 74F623, U36) enables bit 0 to 5 from the MCRW and PD5, PD6 and PD7 from the SCRW on to the hosts bus. When the SCIF is in the smart card mode buffers 1 and 2 are set to a high impedance. The data is read and written by the SCIF through buffer 3 (a 74LS652, U37) which is mapped at memory location 8000H. SCIF to Host Handshaking Sequence
DTA_s
DTAR
Data
Valid Data
Data is written to the host using a handshaking mechanism that exists between the host and the MCRW and uses signals DATR and DTA. A similar method is used to transfer the data between the host and the SCIF but using signals DTA_s and DATR_s. When a smart card command is identified, the
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FEBRUARY 2001
data is latched into buffer 3 by writing to location 8000H. The host requests data by setting DATR low. The data is then put on the host bus by setting DATR_s low, DTA_s is also set low to indicate that data is present from the SCIF. The host acknowledges receipt of the data by setting DATR high. The handshake sequence is completed by setting DTA_s high. Host to SCIF Handshaking Sequence
DTA_s
DTAR
Data
Valid Data
A similar method of handshaking is used to read data from the host. The SCIF sets DTA_s low to indicate to the host that data is required. The host responds to outputing the data to the bus and setting DATR low. The SCIF reads the data by reading memory location 8000H. DTA_s is reset high by the SCIF after the data is read and accepted. The host then resets the DATR signal high and DATR is checked to ensure that the host to SCIF communication link is functioning correctly. Port B Interface The Port B interface carries the commands from the host to both the MCRW and the SCIF. It is through this interface that the smart card instruction is sent. When the latch clock signal, LC, goes from a high to low transition an interrupt is generated and the SCIF firmware checks for a smart card command. A smart card command is generated when:
z The SELECT signal is low z The SC MODE signal is low z The LC signal is an active low pulse.
The lower five bits of Port B are multiplexed by bit 6 of this port and are referenced as register A and register B. These signals are detailed below.
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7.8-12
NOTE: A hardware reset is generated by toggling PB3, Register A.

Port B Bit PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Register A MCF MCB SHE Reset SC Mode DATR Select LC Register B TS0 TS1 RW0 RW1 DT
Port B is located in memory mapped I/O at address 8001H. The Port B commands from the host to the MCRW are interfaced through buffer 5 (a transparent latch 74LS373, U45). When the SCIF detects a smart card command the SCIF_En signal is set high latching the signal from Port B to the MCRW. SCRW Interface Refer to schematic sheets 11 and 12. The MCRW interface is mapped in memory I/O at location 8002H and consists of an input and an output port. All signals associated with the status, that is, the sensors and control for the solenoids, are connected through this interface. Input Port The input port (a 74LS244, U21) is accessed by reading data from memory location 8002H. The signals associated with each bit are listed below:
Bit 0 1 2 3 4 5 6 7 Signal PD7 PD5 PD6 Low_curr High_curr Not used Not used Not used
A description of each bit follows:
z Bit 0 - PD7 indicates if a card is present in the SCRW. A logical high signal
on this line indicates that a card is present. On power up, when no card is present, this signal is low z Bit 1 - PD5 reflects the status of the SCRW stop pin which is used to position the card for correct contact alignment. The signal is low if the pin is in the lowered position
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FEBRUARY 2001
z Bit 2 - PD6 indicates the position of the smart card contacts. If the conz z z z z
tacts are down and in contact with the card PD6 is a logical low. If the contacts are up and not in contact with the card PD6 is high Bit 3 - When the current drawn by the smart card is less than approximately 2 mA this signal is set low Bit 4 - When the current drawn by the smart card is greater than 230 mA this signal is set low Bit 5 - Not used Bit 6 - Not used Bit 7 - Not used.
Output Port U24 (a 74F259 latch) generates the signals on the SCRW output port. This allows each bit to be individually addressed. A coded byte is written to location 8002H in the memory mapped I/O area. The byte is then decoded by the hardware and the appropriate output bit set. The coded bytes should be written to the output port, and the expected output, are given in the table below:
Data Bit Bit 0 1 2 3 4 5 6 7 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 4 L L L L H H H H 5 L L H H L L H H 6 L H L H L H L H Byte (hex) 00-low 10-low 20-low 30-low 40-low 50-low 60-low 70-low 01-high 11-high 21-high 31-high 41-high 51-high 61-high 71-high O/P Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Signal MCF_s MCB_s STP TUD SCIF_En CLK_Sel Not used Not used
A description of each signal follows:
z MCF_s - This signal controls, in conjunction with the MCB_s signal, the z z z z z
motor direction. When MCF_s is high and MCB_s is low the card moves forward in the MCRW MCB_s - This signal controls, in conjunction with the MCF_s signal, the motor direction. When MCB_s is high and MCF_s is low the card moves backwards in the MCRW STP - This signal operates the card stop solenoid. The solenoid is activated when STP is set high TUD - This signal operates the smart card contact solenoid. When TUD is set high the solenoid activates lowering the contacts on to the smart card SCIF_En - This bit is set high to enable the SCIF and disable/latch the PIA signals to the MCRW CLK_SEL (CLOCK_SELECT) - Not used.
NOTE: The outputs of this buffer are all set low by a system reset.
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7.8-14
Solenoid Drivers The card stop pin and card contact solenoids are controlled by Darlington power transistors. The STP and TUD signals are pulled high to 5 volts through 2K2 resistors. This ensures sufficient base drive to saturate the transistors. Current limiting is obtained by a 470R resistor in the series path of the base. Noise decoupling from the transistor base is obtained by a 0.1 microfarad capacitor. This reduces any ringing effect that may result from high speed switching. Any back emf is decoupled by connecting two Schottky diodes in reverse mode across the solenoid coils. Smart Card Interface Refer to schematic sheets 13 and 14. The figure below is a functional block diagram of the smart card interface.
Vcc
74LS273
Current Sense
SCIF DATA Bus
U19
SCIF Control Bus
Data and Clock
Output to Smart Card
Resettable Latch Vpp
The 74LS273 resettable latch, U19 controls most of the smart card interface functions. On power-up the output signals are reset logically low. Data is written to this port, as an 8-bit byte, by writing to memory location 8003H. The functions associated with each bit are as follows:
Bit 0 1 2 3 4 5 6 7 Function Vcc_en Vpp-EN SC-Reset SC_Clock 1 SC_Clock 2 SC_Clock_Base Active_OP_Dis CLK_EN
A brief description of each bit follows:
z Bit 0 - A logical high enables Vcc z Bit 1 - A logical high enables Vpp z Bit 2 - This signal provides a reset to smart card
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FEBRUARY 2001
z Bits 3, 4 and 5 - These signals are decoded to select the required clock frez Bit 6 - The Active_OP_Dis- signal resets all flip-flops which are used to z Bit 7 - This signal enables the clock output through to the smart card contacts. Smart Card Programming Voltage (Vpp) One of the SCIF functions is to provide a programming voltage for the smart cards. This voltage is in the range 5 V to 21 V, with a circuit to provide current limiting. The voltage levels are generated by a digital to analogue converter (DAC) from an 8-bit byte. A 74F573 latching buffer U26 provides the interface to the DAC. The data is latched in to U26 by writing to memory mapped location 8004H. Data is latched out by setting Vpp-EN (Bit 1 of the SCIF control port) high. The figure below shows the two-stage buffering technique used.
Vpp_EN
quency
indicate signals to the smart card that are still active
CS_8004_Wr
SCIF Data Bus 8 Bits
Latches
Buffers
DAC
Analogue Output
The outputs from U26 are disabled by setting Vpp-EN high. When disabled, the outputs are pulled high, inverted at U21 (U20) and applied to the DAC, U11. A zero voltage is obtained when all inputs to the DAC are low. Digital to Analogue Conversion The DAC is one of the 1408 series of 8-bit multiplying digital to analogue converters. An 8-bit byte is written to the DAC which converts it to a binary weighted current. A regulated 5 volt supply gives a stable reference source for the conversion. A -10 volt signal, generated on-board, allows the DAC to operate in a current sink mode. An operational amplifier (OP AMP) U5, with negative feedback, converts the current to a voltage level. The conversion circuit uses the Virtual Earth Principle which states that the output voltage changes to remove the voltage error between the inverting and non-inverting inputs. The OP AMP noninverting input is connected to ground. A variable resistor (VR1), when adjusted, removes errors from the output voltage due to input offset bias currents.
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7.8-16
The following figure shows the DAC circuit.
OP AMP DAC
Buffers
Vpp
Vpp Current Limiting The Vpp circuit is designed to provide a maximum current of 50mA while the smart card programming takes place. Under short circuit conditions, current foldback circuits ensure that the programming voltage is disabled when the currents exceed 55mA. Smart Card Clock Generation Six clock frequencies can be selected under software control. These frequencies are derived from two independent crystal clock oscillators with frequencies of 19.6608 MHz and 14.31818 MHz. The six frequencies are given below with Fi defined as the base frequency.
Fi x 4 Fi x 2 Fi 19.6608 MHz 9.8304 MHz 4.9152 MHz 14.31818 MHz 7.15909 MHz 3.579545 MHz
A dedicated bit (CLK_EN), located at the control port, enables the clock signal out to the smart card. The control port is located at memory-mapped I/ O address 8003H. The operation of the port bits is shown in the following truth table:
SCRW Control Bit 7 L H H H H H H H H 5 X L L L L H H H H 4 X L L H H L L H H 3 X L H L H L H L H L Fi x 4 Fi x 2 Fi L Fi x 4 Fi x 2 Fi L Fi = 3.579545, 14.31818 or derivatives Fi = 4.9152, 19.6608 or derivatives Clock O/P Frequency
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FEBRUARY 2001
The clock frequencies are switched by the following sequence: On power-up the clock is off due to system reset and CLK_EN being low. The appropriate base frequency is selected. CLK_EN is set high to enable the clock out to the card. The frequency is switched by: z Setting CLK_EN low z Selecting new frequency z Selecting CLK_EN high. 5. The frequency is disabled and switched off by: z Setting CLK_EN low z Setting bit 3 and 4 of the smart card control port high. Smart Card Data (ISO and AFNOR/CP8) The SCRW can interface with two different smart card contact positions that is AFNOR/CP8 and ISO. This is provided by two independent receive and transmit lines which are buffered from the CPU to the smart card through two bi-directional ports. To distinguish between AFNOR/CP8 and ISO cards, the AFNOR/CP8 data line from the SCRW is looped back to port 3 bit 2 of the CPU port. Smart Card Vcc The smart card requires a regulated 5 volts with a tolerance of 0.25 volts. it also requires a maximum current of 200mA. The 5 volt supply is obtained by strapping down the +12V supply to +5V using a voltage regulator. The 5 volt output circuit contains current detection circuits that detect currents greater than 230 mA. When currents greater than 230 mA are detected the 5 volt supply to the smart card is switched off. This is hardware detected of over-current and, therefore, is very fast. The figure below is a block diagram of the Vcc voltage regulation and current protection circuit.
5V Regulator 5V Smart Card Vcc 5 Volt regulated and short circuit protected
1. 2. 3. 4.
Current Sensor
Power Fail Interface Schematic sheets 11 and 12 show part of the SCIF circuit which is not used in 56XX SSFTs but is used by the power-fail module in 50XX ATMs. This is described in Chapter 3.9 of the manual D2-0040-A, ATM SYSTEM FIELD SERVICE INFORMATION, MODULE DESCRIPTION.
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7.8-18
Test Connectors Refer to schematic sheets 8, 10 and 17. Three test connectors are provided, a test evaluation connector, a remote diagnostic interface connector, and a smart card signal connector. Test Evaluation Connector Dual 4-way connector J16 provides an interface for test evaluation processes. It is used mainly during board manufacture. The signals available at J16 are as follows:
z The three major clock signals 12 MHz, 14.31818 MHz and 19.6608 MHz z The serial link signals, RXD and TXD z The system reset signal, Test_Reset.
Remote Diagnostic Interface The Remote Diagnostic Interface (RDI) is a dual 10-way connector, J9, which provides the interface with the Level 0 diagnostic switch pack, U4, and LEDs. These TTL-compatible signals are 8 bits wide. A reset line, RDI_RE_SET, which is also TTL-compatible, is also provided and can be used to reset the SCIF hardware. Smart Card Signals Connector Dual 3-way stake pin header J12 is provided to make it easier to test and monitor the smart card signals rather than via the flexible signal connectors J8 and J10. The signals on J12 pass via the flexible circuit connectors and, therefore, breaks in the tracks on the SCIF pcb will also be detected.
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FEBRUARY 2001
ERROR CODES AND DIAGNOSTICS

LEVEL 0 DIAGNOSTICS
Level 0 diagnostics tests for the SCIF/EMV SCIF execute whenever power is applied or a hardware reset occurs. There are two modes of operation:
z Start-up. A sequence of tests which takes no longer than 10 seconds to run z Extended Level 0 diagnostics. Individual tests can be selected to run.
All the diagnostics tests performed during the start-up diagnostics can also be performed by using the extended diagnostics. NOTE: There are no Loop or Continue on Error options available with these diagnostics. Switch Settings Select the diagnostic mode using the eight switches (SW1 to SW8) located on switchpack U5 (U4). These switches are numbered 1 (LSB), for the right-most switch, to 8 (MSB), for the left-most switch.
Switch No. Start-Up Selected 0 = Switch open 1 = Switch closed SW8 0 1 SW7 0 0 SW6 0 0 SW5 0 SW4 0 SW3 0 SW2 0 SW1 0
<--------------------TEST ID------------------>
LEDs The test results display on the eight LEDs, D1 to D8. These LEDs are numbered 1 (LSB), for the right-most LED, to 8 (MSB), for the left-most LED. The test number displays on LED 1 to 5. If a test fails, the test number shows for one second and the test result shows for two seconds. If a bad switch setting is made, the LEDs do not flash but display the following error code:
z ODH - Bad Switch Setting.
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7.8-20
Test Descriptions SCIF The tests available are identified by a unique number. The following table shows the test ID, the test description and whether they are available in the Start-up or Selected mode. The majority of tests is available only in Selected mode.
Test ID 01 02 03 04 06 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E Test Description CPU and EPROM Test RAM Data Test RAM Address Test NVRAM Initialize Smart Card Contacts Test Card VPP Slow Staircase Card VPP Fast Sawtooth Card VPP = 5 Volts Card VPP = 21 Volts Card Clock = 1 x 3.579545 MHz Card Clock = 2 x 3.579545 MHz Card Clock = 4 x 3.579545 MHz Card Clock = 1 x 4.9152 MHz Card Clock = 2 x 4.9152 MHz Card Clock = 4 x 4.9152 MHz Card Reset Toggle Card I/O Toggle Card Vcc Toggle Exercise Stopper Pin Exercise Contact Unit X Start-Up X X X Selected X X X X X X X X X X X X X X X X X X X X
Test 01 - CPU and EPROM Description The following tests are performed:
z z z z z
CPU registers. All register banks are tested CPU instructions. Arithmetic and bit manipulation instructions are tested Stack, Push and Pop sequence EPROM - Cyclic Redundancy Check (CRC) calculation Internal RAM. This is tested by writing alternate 55, AA and FF bytes in RAM. These values are checked. If O.K., inverted and checked again z CPU special purpose timers and interrupt registers are tested.
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Test Results
LEDs 00H 08H 09H 0AH 0BH 0CH 0DH Status Test passed CPU fault CPU internal RAM/stack fault CPU timer fault CPU interrupt register fault Serial control register fault EPROM CRC check fault
Test 02 - External Data Memory Description The following tests are performed:
z Volatile RAM. This is tested by writing alternate 55, AA and FF bytes in z Non-volatile memory data. Header checked. CRC check of contents. Only
performed when smart card encryption (SCE) is not used. Test Results
LEDs 00H 08H 09H 0DH Status Test passed Volatile RAM error Non volatile memory error - possible battery failure Non volatile memory CRC fail - possible corruption of NVRAM
RAM. These values are checked. If O.K., inverted and checked again
NOTE: If test results 09 or 0D are returned, corrective action must be taken to replace the battery or SRAM. On replacement Test 04 must be performed to ensure that the SCIF is installed. This test will write a header block to NVRAM, calculate and store a CRC for the contents of NVRAM. Test 03 - External Data Memory Address and Data Lines Description The volatile RAM is filled with zeroes, except for byte 00, which is filled with FF hex. The contents of RAM is then verified. The RAM contents is then read using an address of 1 left rotating zero that is 1, 2, 4, 8, 16.... . If the data read from these addresses equals FF hex, the external connection of that address line is faulty. If the data read of one of the addresses is neither 00 or FF hex, one or more data lines are faulty. The non-volatile memory contains FF hex on byte 00 zero bytes on addresses having only one bit set that is 1, 2, 4... . If the data read from these addresses equals FF hex, external connection of that address line is faulty. If the data read from one of the addresses is neither 00 nor FF hex, one or more data lines are faulty.
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7.8-22
The information stored in the non-volatile memory is placed so that it does not interfere with the check bytes. This test is not applicable when a smart card encryptor is used. Test Results
LEDs 00H 08H 09H xAH xBH xCH xDH Status Test passed Data error while verifying 00 hex write Data error while verifying FF hex write Volatile RAM address bus error, address line x (0-F) Volatile RAM data bus error, data line x (0-7) Non-volatile memory address bus error, address line x (0-F) Non-volatile memory data bus error, data line x (0-7)
Test 04 - NVRAM Initialize Description The area of NVRAM from external data memory addresses 7000H to 8000H is initialized. During this process the memory is over written with zeros, a header block is written into NVRAM and a CRC is done over the contents of NVRAM and the result written. This test is done to indicate a start of life condition for the SCIF board. Test Results
LEDs 00H Status Test passed
NOTE: This test must be performed the first time the SCIF is powered on. If this test has not been run, the header block and CRC will not have been written into NVRAM. Test 04 will always fail. Similarly if the battery or SRAM has been replaced, this test must be run the first time the SCIF is powered on. Test 06 - Smart Card Contacts and Communication Description The power off detection is checked for one of the contacts not being at ground level as follows:
z z z z
Vcc is applied The power switch off detection is checked for Vcc Vcc is switched off which is then checked The above sequence is then carried out for the following lines: z Vpp is (5 volt) z Reset z Clock z Input/output.
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FEBRUARY 2001
Smart card communication. Data transmission to the card input/output contacts is checked by using the power off switched detection. Data received from the card input/output contact is tested by sending data through the AFNOR/CP8 detect line of the CPU. Test Results
LEDs 00H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Status Test passed One of the contacts not at ground level Vcc contact fault Vpp contact fault Reset contact fault Clock contact fault Input/output contact fault Send to input/output contact fault Receive from input/output contact fault
Test 10 - Card Vpp Slow Staircase Description The SCIF sends a staircase voltage to the smart card Vpp contact. The values of the staircase are 5, 9, 13, 17 and 21 volts. Each voltage is output for 3 seconds to enable measurement with a suitable meter. Voltages should be within 2.5%. If adjustment is necessary, use Test 12 to adjust the 5V card Vpp. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 11 - Card Vpp Fast Sawtooth Description The SCIF sends a sawtooth voltage to the smart card Vpp contact. The values of the sawtooth voltage range between 5 and 21 volts in increments of 0.1 volt. Each step is output for 100 microseconds to enable measurement with a suitable oscilloscope. Voltages should be within 2.5%. If adjustment is necessary, use Test 12 to adjust the 5V card Vpp. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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7.8-24
Test 12 - Card Vpp = 5.0 Volt Description The SCIF sends a fixed Vpp of 5.0 volts to the smart card Vpp contact. This value can be measured to show if an adjustment of the voltage is required. The value must be measured with a current of 50 mA, therefore, a load resistor of 100 ohm, 0.25 watt must be used between pin 3 of J12 and ground. Use VR1 to set Vpp within the band 4.875V to 5.125V, with the load resistor in place. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 13 - Card Vpp = 21.0 Volt Description The SCIF sends a fixed Vpp of 21.0 volts to the smart card Vpp contact. This value can be measured to show if an adjustment of the voltage is required. The value must be measured with a current of 50 mA, therefore, a load resistor of 420 ohm, 1.0 watt must be used between pin 3 of J12 and ground. The voltage should be within the range 20.475V to 21.525V. If adjustment is necessary, use Test 12 to adjust the 5V card Vpp. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 14 - Card Clock = 1 x 3.579545 MHz Description The SCIF sends a clock signal of 1 x 3.579545 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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Test 15 - Card Clock = 2 x 3.579545 MHz Description The SCIF sends a clock signal of 2 x 3.579545 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 16 - Card Clock = 4 x 3.579545 MHz Description The SCIF sends a clock signal of 4 x 3.579545 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 17 - Card Clock = 1 x 4.9152 MHz Description The SCIF sends a clock signal of 1 x 4.9152 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 18 - Card Clock = 2 x 4.9152 MHz Description The SCIF sends a clock signal of 2 x 4.9152 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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Test 19 - Card Clock = 4 x 4.9152 MHz Description The SCIF sends a clock signal of 4 x 4.9152 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 1A - Card Reset Toggle Description The reset line is toggled at about 5 Hz. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 1B - Card Input/Output Toggle Description The SCIF toggles the smart card input/output line at about 5 Hz. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 1C - Card Vcc Toggle Description The SCIF toggles the smart card Vcc line at about 5 Hz. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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Test 1D - Exercise Stopper Pin Description The SCIF performs the following sequence: 1. 2. 3. 4. 5. 6. 7. Activates the stopper pin solenoid. Checks for lower pin position. Waits one second. Deactivates the stopper pin solenoid. Checks for upper pin position. Waits one second. Repeats steps 1 to 6.
NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test Results Test No. and test results shown on the LEDs are:
LEDs 09H Status Stopper pin failed to reach either the low or high position
Test 1E - Exercise Contact Unit Description The SCIF performs the following sequence: 1. 2. 3. 4. 5. 6. 7. Activates the contact unit solenoid. Checks for lower contact unit position. Waits one second. Deactivates the contact unit solenoid. Checks for upper contact unit position. Waits one second. Repeats steps 1 to 6.
NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test Results
LEDs 09H Status Contact Unit failed to reach either the low or high position
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Test Descriptions EMV-SCIF The tests available are identified by a unique number. The following table shows the test ID, the test description and whether they are available in the Start-up or Selected mode. The majority of tests is available only in Selected mode.
Test ID 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Test Description CPU and EPROM Test RAM Data Test RAM Address Test NVRAM Initialize (Dual Voltage Disabled) NVRAM Initialize (Dual Voltage Enabled) Smart Card Test Card Clock - Stop Low Card Clock = XTAL/2 MHz Card Clock = XTAL/4 MHz Card Clock = XTAL/8 MHz Card Clock = FINT/2 Card Clock - Stop High Card Signals Toggle Exercise Stopper Pin Exercise Contact Unit X Start-Up X X X Selected X X X X X X X X X X X X X X X
z z z z z
CPU registers. All register banks are tested CPU instructions. Arithmetic and bit manipulation instructions are tested Stack, Push and Pop sequence EPROM - Cyclic Redundancy Check (CRC) calculation Internal RAM. This is tested by writing alternate 55, AA and FF bytes in RAM. These values are checked. If O.K., inverted and checked again z CPU special purpose timers and interrupt registers are tested. Test Results
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Test 02 - External Memory Description The following tests are performed:
performed when smart card encryption (SCE) is not used. Test Results
NOTE: If test results 09 or 0D are returned, corrective action must be taken to replace the battery or SRAM. On replacement Test 04 or 05 must be performed to ensure that the EMV-SCIF is installed. This test will write a header block to NVRAM, calculate and store a CRC for the contents of NVRAM. Test 03 - External Data Memory Address and Data Lines Description The volatile RAM is filled with zeroes, except for byte 00, which is filled with FF hex. The contents of RAM is then verified. The RAM contents is then read using an address of 1 left rotating zero that is 1, 2, 4, 8, 16.... . If the data read from these addresses equals FF hex, the external connection of that address line is faulty. If the data read of one of the addresses is neither 00 or FF hex, one or more data lines are faulty. The non-volatile memory contains FF hex on byte 00 zero bytes on addresses having only one bit set that is 1, 2, 4... . If the data read from these addresses equals FF hex, external connection of that address line is faulty. If the data read from one of the addresses is neither 00 nor FF hex, one or more data lines are faulty. The information stored in the non-volatile memory is placed so that it does not interfere with the check bytes. This test is not applicable when a smart card encryptor is used. Test Results
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Test 04 - NVRAM Initialize Disabled Description The area of NVRAM from external data memory addresses 7000H to 8000H is initialized. During this process the memory is over written with zeros, a header block is written into NVRAM and a CRC is done over the contents of NVRAM and the result written. This test is done to indicate a start of life condition for the EMV-SCIF board. Test Results
Test 05 - NVRAM Initialize Enabled Description The area of NVRAM from external data memory addresses 7000H to 8000H is initialized. During this process the memory is over written with zeros, a header block is written into NVRAM containing an additional byte indicating the support of Dual Voltage Cards, and a CRC is done over the contents of NVRAM and the result written. This test is done to indicate a start of life condition for the EMV-SCIF board. Test Results
NOTE: Either test 04 or 05 must be performed the first time the EMV-SCIF is powered on. If either test has not been run, the header block and CRC will not have been written into NVRAM. Test 02 will always fail. Similarly if the battery or SRAM has been replaced, this test must be run the first time the EMV-SCIF is powered on. Test 06 - Smart Card Communication Test Description The interface to the IC card on the EMV-SCIF is controlled exclusively by the Phillips TDA8006 Device thus constricting direct access to the SC signals. The level of testing performed by this test depends on whether it is called as part of the Start-up test, or as a Selected Test. Start-up testing performs a limited compared to the Selected Test. Test Results
LEDs 00H 08H 09H 0AH Status Test passed Initialisation of system failure (Error at library procedure Init_System) I/O line not at zero Card Present (For Start-Up: Error at library procedure Power-Up)
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Test 07 - Card Clock - Stop Low Description The EMV-SCIF sets the card clock low. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 08 - Card Clock = XTAL/ 2 MHz Description The EMV-SCIF sends a clock signal of XTAL/ 2 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 09 - Card Clock = XTAL/ 4 MHz Description The EMV-SCIF sends a clock signal of XTAL/ 4 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 0A - Card Clock = XTAL/ 8 MHz Description The EMV-SCIF sends a clock signal of XTAL/ 8 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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Test 0B - Card Clock = FINT/ 2 MHz Description The EMV-SCIF sends a clock signal of FINT/ 2 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 0C - Card Stop High Description The EMV-SCIF sets the card clock high. The clock signal can be measured with an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 0D - Card Signal Toggle Description The EMV-SCIF toggles the smart card Vcc, Reset and I/O line. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs flash the test ID. No error response is returned. Test 0E - Exercise Stopper Pin Description The EMV-SCIF performs the following sequence: 1. 2. 3. 4. 5. 6. 7. Activates the stopper pin solenoid. Checks for lower pin position. Waits one second. Deactivates the stopper pin solenoid. Checks for upper pin position. Waits one second. Repeats steps 1 to 6.
NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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Test Results Test No. and test results shown on the LEDs are:
Test 0F - Exercise Contact Unit Description The EMV-SCIF performs the following sequence: 1. 2. 3. 4. 5. 6. 7. Activates the contact unit solenoid. Checks for lower contact unit position. Waits one second. Deactivates the contact unit solenoid. Checks for upper contact unit position. Waits one second. Repeats steps 1 to 6.
LEDs 09H Status Contact Unit failed to reach either the low or high position
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LEVEL 1 DIAGNOSTICS
The level 1 diagnostic tests available for smart card are:
z z z z z z z z z
SMART CARD STAGE SMART CARD RESET SMART CARD RELEASE SCIF INITIALISE SCIF SOLENOID SCIF IDENTIFY RUN-TO-RUN 1 RUN-TO-RUN 2 RUN-TO-RUN 3.
SMART CARD STAGE The SMART CARD STAGE test moves the card from the MCRW transport into the SCRW and brings the contacts down on to the card. SMART CARD RESET The SMART CARD RESET applies power to the card under the contacts. The resultant data stream from the smart card is displayed. SMART CARD RELEASE The SMART CARD RELEASE test raises the card contacts and moves the card out of the SCRW back into the MCRW transport. SCIF INITIALISE The SCIF INITIALISE test causes the SCIF board to switch into SCRW mode and toggle the SCIF reset line. Power is removed from any card present and the smart card contacts and stopper pin solenoids are de-energized. The SCIF board switches to MCRW mode. SCIF SOLENOID The SCIF SOLENOID test activates the SCRW stopper pin and contact solenoids. NOTE: The card should not be in the SCRW when this test is selected. SCIF IDENTIFY The SCIF IDENTIFY test allows the operator to display or print the ROM firmware number as T_DATA.
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RUN-TO-RUN 1 The RUN-TO-RUN 1 test automatically performs the following tests in sequence:
z z z z z z z z z z
SHUTTER/SENSOR ENTER READ ISO TRACK 1 (If configured) READ ISO TRACK 2 READ ISO TRACK 3 (If configured) SMART CARD STAGE SMART CARD RESET SMART CARD RELEASE EJECT CAPTURE.
NOTE: See the appropriate MCR/MCRW chapters in this manual for discriptions of tests not specific to smart card. RUN-TO-RUN 2 The RUN-TO-RUN 2 test automatically performs the following tests in sequence:
z ENTER z CAPTURE.
NOTE: See the appropriate MCR/MCRW chapters in this manual for discriptions of tests not specific to smart card. RUN-TO-RUN 3 The RUN-TO-RUN 3 test automatically performs the following tests in sequence:
z z z z z z z z
ENTER READ ISO TRACK 1 (If configured) READ ISO TRACK 2 READ ISO TRACK 3 (If configured) SMART CARD STAGE SMART CARD RESET SMART CARD RELEASE EJECT.
NOTE: See the appropriate MCR/MCRW chapters in this manual for discriptions of tests not specific to smart card.
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M_STATUS M_STATUS values, and their meaning for the SCRW, are shown below. Original severity is also shown. The M_STATUS codes for the associated MCRW are given in the appropriate Chapter in this manual, refer to Chapter 7.2, 7.3 or 7.7 as required.
M_STATUS 50 51 52 53 54 55 57 Meaning Card not in SCRW stage position. Smart card stopper pin lowered, unable to capture. This is only in response to card capture. Invalid smart card command code error. Invalid smart card command data error. SCIF not configured/not responding. SCIF response timeout exceeded. Invalid smart card response length. Original Severity 2 4 2 2 2 2 2
Additional M_STATUS codes may be returned by the SCIF as shown below.

M_STATUS 00 64 65 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Good Invalid command code Invalid command format Invalid key ID Invalid key type Invalid host key type Invalid key - does not exist Invalid password - not decimal Invalid password - no match Key integrity error Key parity error Invalid data format Stopper pin failure Contact unit failure Card movement failure SC switch off failure Smart card removed error No smart card response Smart card transmission error Smart card switched off Illegal card type/parameter Power up time exceeded ANSI X9.8 pin block error Meaning
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M_DATA Entries are returned in Byte 0 and 4 as follows: Byte 0

70H = SCIF Command.
Byte 4
Bit 0 - PD7 (1 = blocked). Bit 1 - PD5/6 (1 = stopper pin/contacts down).
LEVEL 2 DIAGNOSTICS
None.
LEVEL 3 DIAGNOSTICS (TALLIES)

The SCRW firmware updates a number of tallies. These tallies are updated in diagnostic and normal modes. The tallies are as follows:
z SMART CARD STOPPER PIN SOLENOID ACTUATION ATTEMPTS z

(SPSOLOPS) - Incremented when the smart card stopper pin solenoid is actuated during execution of the command to stage the smart card SMART CARD STOPPER PIN SOLENOID ACTUATION FAIL (SPSOLERR) - Incremented when the smart card stopper pin solenoid is actuated but the stopper pin is detected not to have moved, during execution of the command to stage the smart card SMART CARD CONTACTS SOLENOID ACTUATION ATTEMPTS (CTSOLOPS) - Incremented when the smart card contacts solenoid is actuated during execution of the command to stage the smart card SMART CARD CONTACTS SOLENOID ACTUATION FAIL (CTSOLERR) - Incremented when the smart card contacts solenoid is actuated but the contacts are detected not to have moved, during execution of the command to stage the smart card NON SMART CARD DETECTED (NONSCDET) - Incremented when the card present is detected not to be a smart card, during the execution of the command to power on the smart card SMART CARD DETECTED (SCDETECT) - Incremented when the card present is detected to be a smart card, during the execution of the command to power on the smart card ISO SMART CARD DETECTED (ISOSCDET) - Incremented when the card present is detected to be an ISO type smart card, during the execution of the command to power on the smart card AFNOR/CP8 SMART CARD DETECTED (CP8SCDET) - Incremented when the card present is detected to be a AFNOR/CP8 type smart card, during the execution of the command to power on the smart card SMART CARD RESET ATTEMPT (SCRESETS) - Incremented when a smart card reset is carried out during the execution of the command to power on the smart card SMART CARD ANSWER TO RESET FAIL (SCRSTERR) - Incremented when an error is found in the answer to reset during the execution of the command to power on the smart card
z z
z z z z z z
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z SMART CARD POWER ON TIMEOUT (SCPWRTIM) - Incremented when z SCIF COMMS ATTEMPTS (SCIFCMAT) - Incremented when an attempt z z z z z z
is made by the device controller to send or receive a message to or from the SCIF SCIF COMMS FAIL (SCIFCMFL) - Incremented when the device controller fails in its attempt to send or receive a message to or from the SCIF SCIF RESPONSE TIMEOUT (SCIFRSPT) - Incremented when the SCIF fails to respond within the timeout specified by the SCIF command message SMART CARD COMMS ATTEMPTS (SCCOMAT) - Incremented when a communication is attempted between the SCIF and the smart card SMART CARD COMMS RETRIES (SCCOMRTY) - Incremented when a communication retry was successfully carried out during the execution of a smart card related command SMART CARD RESPONSE TIMEOUT (SCRSPTIM) - Incremented when the SCIF reports that the smart card has failed to respond within the specified timeout SMART CARD INTERFACE REINITIALIZATION ATTEMPTS (SCIF_RES) - Incremented when Reinitialization command issued. Tally numbering and threshold values are shown in the following table.
Tally Mnemonic SPSOLOPS SPSOLERR CTSOLOPS CTSOLERR NONSCDET SCDETECT ISOSCDET CP8SCDET SCRESETS SCRSTERR SCPWRTIM SCIFCMAT SCIFCMFL SCIFRSPT SCCOMATT SCCOMRTY SCRSPTIM SCIF_RES Number 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS CTSOLOPS SCRESETS SCRESETS SCRESETS SCRESETS SPSOLOPS Frame of Reference Threshold REF10000 10 REF10000 10 N/A N/A N/A N/A REF1000 1000 N/A N/A N/A N/A N/A N/A N/A N/A
the limit on the specified smart card power on time has been reached
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STRAPPING
None.
ADJUSTMENTS
CARD VPP
The smart card voltage Vpp is adjusted using level 0 diagnostics test 12. Refer to the section Level 0 Diagnostics in this chapter.
PD7 SENSE
There is a pull up resistor in the PD7 line from the SCIF board. This resistor is located in the SCRW in an adjustment harness wired between the +5V input to the PD5/PD6 Sensor pcb and the PD7 line on the Card Position Sensor pcb (refer to the schematic diagram in the section Interconnections, Solenoids and Photodetector connectors). The resistor must be matched to PD7. This is a Dundee or Rework Centre adjustment only and is not to be attempted in the field. If the photo transistor is to be replaced then the pull up resistor must also be replaced with one chosen as described here. The adjustment procedure is as follows: 1. Use a wire link instead of the pull-up resistor (that is, a short to the +5V line). 2. With light from the LED falling on the photo transistor, measure the light current through the sensor PD7. 3. Select the value of the pull-up resistor from the following table:
Light Current (I) 68< I =<100 uA 100< I =<150 uA 150< I =<220 uA 220< I =<320 uA 320< I =<450 uA 450< I =<680 uA 680< I =<1.0 mA 1.0< I =<1.5 mA 1.5< I =<2.2 mA 2.2< I =<3.2 mA Pull-Up Resistor 220 K 150 K 100 K 68 K 47 K 33 K 22 K 15 K 10 K 6K8
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TEST EQUIPMENT
DIAGNOSTIC TEST CARDS
You need the following test cards to perform level 1 diagnostic testing on the SCRW:
z AFNOR/CP8 test card - NCR part number 009-0009493 z ISO test card - NCR part number 009-0009494 z Cleaning card - NCR part number 998-0052929.
PREVENTIVE MAINTENANCE
The only preventive maintenance necessary for the SCRW is to clean the feed roller. This should be done using the diagnostic clean facility and cleaning card for the associated MCRW. Refer to the details given in the Chapter for the associated MCRW in this manual, that is Chapter 7.2, 7.3 and 7.7.
INTERCONNECTIONS
The interconnections between the SCRW, the MCRW and the SCIF are shown in the following figures.
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SOLENOIDS AND PHOTODETECTOR CONNECTORS
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MOTOR AND SHUTTER CONNECTOR
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SDC MCRW TO SCIF PIA INTERFACE BOARD
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SCIF TO MCRW CONTROLLER PIA CONNECTOR
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POWER CONNECTIONS
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SMART CARD SIGNALS AND POWER
SCHEMATIC AND ASSEMBLY DIAGRAMS

The following fold-out pages FO-1 to FO-21 contain the assembly drawings and schematic diagrams of the SCIF board as follows:
z FO-1 and FO-2 - Assembly 455-0612681 z FO-3 to FO-21 - Schematic Diagram for 455-0602440.
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EMV SMART CARD READER/WRITER
Contents
EMV Smart Card Reader/Writer
Chapter 7.14
INTRODUCTION ...................................................................................................... 7.14-1 GENERAL DESCRIPTION ....................................................................................... 7.14-1 FUNCTIONAL DESCRIPTION ................................................................................ 7.14-3 EMV SCRW MODULE ............................................................................................. 7.14-3 MECHANICAL OPERATION ............................................................................. 7.14-3 SOFTWARE OPERATION ................................................................................. 7.14-4 Modes of Operation........................................................................................... 7.14-4 Card Entry ......................................................................................................... 7.14-4 Normal Sequence .............................................................................................. 7.14-4 ELECTRICAL OPERATION................................................................................ 7.14-5 Input Signals...................................................................................................... 7.14-5 Output Signals ................................................................................................... 7.14-5 Contacts (16 Pin) ............................................................................................... 7.14-5 Contacts (8 Pin)................................................................................................. 7.14-5 Power Requirements ......................................................................................... 7.14-7 EMV SCIF BOARD ................................................................................................... 7.14-7 EMV SCIF CORE ELECTRONICS...................................................................... 7.14-8 Processor and Support Circuitry ....................................................................... 7.14-8 Memory and Address Decode ........................................................................... 7.14-9 Level 0 Diagnostics......................................................................................... 7.14-10 INTERFACES ..................................................................................................... 7.14-10 Power Interface ............................................................................................... 7.14-11 PIA Interface ................................................................................................... 7.14-11 SCRW Interface .............................................................................................. 7.14-14 Smart Card Interface ....................................................................................... 7.14-16 Smart Card Signal Chaacteristics .................................................................... 7.14-24 Power Fail Interface ........................................................................................ 7.14-25 Test Connectors............................................................................................... 7.14-25 ERROR CODES AND DIAGNOSTICS.................................................................. 7.14-27 LEVEL 0 DIAGNOSTICS .................................................................................. 7.14-27 Switch Settings................................................................................................ 7.14-27
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LEDs................................................................................................................ 7.14-27 Test Descriptions EMV-SCIF ......................................................................... 7.14-28 Test 01 - CPU and EPROM ............................................................................ 7.14-28 Test 02 - External Memory ............................................................................. 7.14-29 Test 03 - External Data Memory Address and Data Lines ............................. 7.14-29 Test 04 - NVRAM Initialize Disabled ............................................................ 7.14-30 Test 05 - NVRAM Initialize Enabled ............................................................. 7.14-30 Test 06 - Smart Card Communication Test..................................................... 7.14-30 Test 07 - Card Clock - Stop Low .................................................................... 7.14-31 Test 08 - Card Clock = XTAL/ 2 MHz ........................................................... 7.14-31 Test 09 - Card Clock = XTAL/ 4 MHz ........................................................... 7.14-31 Test 0A - Card Clock = XTAL/ 8 MHz .......................................................... 7.14-31 Test 0B - Card Clock = FINT/ 2 MHz ............................................................ 7.14-32 Test 0C - Card Stop High ................................................................................ 7.14-32 Test 0D - Card Signal Toggle ......................................................................... 7.14-32 Test 0E - Exercise Stopper Pin........................................................................ 7.14-32 Test 0F - Exercise Contact Unit ...................................................................... 7.14-33 LEVEL 1 DIAGNOSTICS .................................................................................. 7.14-33 SMART CARD STAGE ................................................................................. 7.14-33 SMART CARD RESET.................................................................................. 7.14-33 SMART CARD RELEASE ............................................................................ 7.14-33 SCIF INITIALISE........................................................................................... 7.14-34 SCIF SOLENOID ........................................................................................... 7.14-34 SCIF IDENTIFY ............................................................................................. 7.14-34 RUN-TO-RUN 1 ............................................................................................. 7.14-34 RUN-TO-RUN 2 ............................................................................................. 7.14-35 RUN-TO-RUN 3 ............................................................................................. 7.14-35 M_STATUS .................................................................................................... 7.14-35 M_DATA ........................................................................................................ 7.14-36 LEVEL 2 DIAGNOSTICS .................................................................................. 7.14-37 LEVEL 3 DIAGNOSTICS (TALLIES) .............................................................. 7.14-37 STRAPPING............................................................................................................. 7.14-39 ADJUSTMENTS ...................................................................................................... 7.14-39 TEST EQUIPMENT................................................................................................. 7.14-39 DIAGNOSTIC TEST CARDS ............................................................................ 7.14-39 PREVENTIVE MAINTENANCE ........................................................................... 7.14-39 INTERCONNECTIONS .......................................................................................... 7.14-39 SOLENOIDS AND PHOTODETECTOR CONNECTIONS ............................. 7.14-40 MOTOR AND SHUTTER CONNECTOR ......................................................... 7.14-41 SDC MCRW TO SCIF PIA INTERFACE BOARD ........................................... 7.14-42 SCIF TO MCRW CONTROLLER PIA CONNECTOR .................................... 7.14-43 POWER CONNECTIONS .................................................................................. 7.14-44 SMART CARD SIGNALS AND POWER ........................................................ 7.14-44 SCHEMATIC AND ASSEMBLY DIAGRAMS ..................................................... 7.14-45
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Contents
Chapter 7.14
EMV Smart Card Reader/Writer
INTRODUCTION
This chapter describes the EMV Smart Card Reader/Writer (SCRW) modules that are attached to MCRWs in NCR ATMs to provide the ability to read and write to smart cards. The combined SCRW and MCRW is refered to as the Magnetic Smart Card Reader (MSCR). There are two types: 1. The MSCR reads and writes to smart cards and ISO magnetic cards in compliance with the ISO 7816 (parts 1, 2 and 3) and the AFNOR/CP8 I.C. card standards. The associated electronic circuits for the EMV SCRW are contained on the EMV Smart Card Interface (SCIF) board. 2. The EMV MSCR replaces the above module. It provides the same functions and additionally is designed to be compatible with EMV, GIE CB (France), and Mondex. The term EMV is derived from Europay, Master Card, and Visa. Its associated electronics board is termed the EMV SCIF. There are two types of Smart Card Reader/Writer (SCRW:)
z The 16-pin version reads and writes to smart cards and ISO magnetic
cards in compliance with EMV 3.1.1, ISO 7816 (parts 1, 2 and 3) and the AFNOR/CP8 I.C. card standards. z The 8-pin version only reads and writes to smart cards and ISO magnetic cards in compliance with EMV 3.1.1, ISO 7816 (parts 1, 2 and 3) card standards.
GENERAL DESCRIPTION
The EMV Smart Card Reader/Writer (SCRW) reads and writes to smart cards and ISO magnetic cards in compliance with EMV 3.1.1 and ISO 7816 (parts 1, 2 and 3) and the AFNOR/CP8 I.C. card standards. The Smart Card must have the contacts at the front of the card and may have a magnetic strip at the reverse side. Smart Cards with contacts in either the ISO position or the AFNOR (CP8) position are supported. The EMV SCRW feature adds on to the Magnetic Card Reader/Writer (MCRW) or Magnetic Card Reader (MCR) modules for the 56XX/personaSXX range of NCR Self Service Financial Terminals. The additional electronic functions necessary for reading and writing of smart cards are provided by the EMV Smart Card Interface (EMV SCIF) board which is also attached to the
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MCRW. The main functional areas of the EMV SCIF board are shown in the following block diagram.
SDC I/F
EMV SCIF
PIA
MCRW I/F
MCR/MCRW SDC I/F Board
PIA
SCRW
MCRW
When an EMV SCRW module and EMV SCIF are configured in the host machine the EMV SCIF interfaces with the same PIA bus (from the SDC MCRW Interface Board) as the MCRW. A smart card command sent by the host is identified by the EMV SCIF, which then disables the PIA interface to the MCRW and takes control of the MCRW. Once the smart card operation is complete, control is passed back to the host/MCRW interface. The following figure shows the EMV SCRW feature attached to an MCRW
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FUNCTIONAL DESCRIPTION
The functional description of the EMV SCRW Module and EMV SCIF Board is provided in the following sub-sections: z EMV SCRW Module: z Mechanical Operation z Software Operation z Electrical Operation z EMV SCIF Board: z SDC Interface z EMV SCRW Interface z MCRW Interface. In addition to the above interfaces, there are circuits associated with handling power failure and providing test connectors.
EMV SCRW MODULE

MECHANICAL OPERATION
The figure below shows the components of the EMV SCRW Module:
Contact Solenoid Stopper Pin Solenoid
Flexible Printed Cables Solenoid Sensors PCB
Stopper Pin
Card Sensor
Card Entry Mouth Contacts (8-pin or 16-pin version)
The EMV SCRW attaches to the rear of the MCRW/MCR. The rear transport shaft of the MCRW/MCR is modified to have a double belt pulley turned by a pint through the shaft which creates a half-turn clutch. A rubber wheel on the shaft bears down on a lower nylon wheel to drive a card, passing between them, into the EMV SCRW. The card is pushed against a reference surface on the right-hand side of the EMV SCRW by a flat metal spring attached to the left-hand side.
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The card is detected in the EMV SCRW by an optical sensor (PD7). A solenoid energizes to lower a pin into the path of the card and stop it in position under a set of spring metal contacts. The action of the solenoid is detected by a photodetector (PD5) looking at a flag on the solenoid arm. With the card correctly in position, a second solenoid is energized to lower the spring metal contacts on to the contact area of the card. Another sensor (PD6) detects the movement of this solenoid. An O-belt from the MCRW rear transport pulley drives a shaft at the rear of the EMV SCRW. This shaft carries a rubber wheel which bears down on a lower nylon wheel to drive cards into the card capture bin. In a normal transaction the card will not reach these drive wheels but remain in the grip of the MCRW rear transport wheels which reverse direction to drive the card back to the cardholder.
SOFTWARE OPERATION
Control of the EMV SCRW is provided by the EMV SCIF board which has its own on-board firmware. This firmware communicates with the host SSFT via the SDC MCRW Interface Board, to control the solenoid and card movement when in the smart card mode. Modes of Operation At initialization the MCRW/SCRW device driver and the EMV SCIF board adopt MCRW mode. The device driver interrogates the hardware to determine if the EMV SCIF is present and functioning correctly. If all is O.K. the device driver will control the EMV SCRW by sending EMV SCIF commands to the SCIF board (see the section Normal Sequence for a list of SCIF commands). All hardware signals, including MCRW signals, are routed through the EMV SCIF board. When a EMV SCIF command is received by the board, it switches to EMV SCRW mode, produces the associated signals to achieve that command and then switches back into the MCRW mode. The EMV SCIF switches into the SCRW mode for the duration of each EMV SCIF command. Card Entry Card entry is identical to MCRW/MCR card entry. Once the card width and card sense requirements are met and under application control, the card is accepted and staged in the transport by the motor in the MCRW/MCR. An EMV SCIF command is then issued to stage the smart card in the EMV SCRW so that it is ready to be read from or written to. Normal Sequence The normal sequence of events for smart card operation is as follows:
z The MCRW/MCR Accept command stages the card z The EMV SCIF command Stage Smart Card moves the card into the EMV z The EMV SCIF command Power On Card applies to the card and produces z The EMV SCIF command Smart Card Direct reads/writes to the card. z The EMV SCIF command Power Off Card removes power from the card z The EMV SCIF command Release Card moves the card back to the
MCRW/MCR stage position. These commands are card specific an Answer To Reset from the card SCRW
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ELECTRICAL OPERATION
The electrical logic to control the EMV SCRW is wholly located on the EMV SCIF board as described on the section EMV SCIF Board. Connectors on the EMV SCRW carry the power supplies, the signals from the smart card, the sensor status, and the solenoid control signals, to the EMV SCIF board. Refer to the section Interconnections for pinouts of these connectors. Input Signals The input signals are as follows:
z STP - When this signal is activated, the card stage stopper pin mechanism z TUD - When this signal is activated, the Connector lowering mechanism is
lowered. Output Signals The following TTL compatible output signals are generated: is lowered
z PD5 - This signal becomes logically high when the card stopper pin is lowz PD6 - This signal becomes logically high when the smart card contacts are z PD7 - This signal becomes logically high when the smart card is correctly
staged in the EMV SCRW. Contacts (16 Pin) Two rows of eight contacts are lowered on to the card. Of the 16 contacts, eight are in the ISO contact group position and eight are in the AFNOR/CP8 contact group position. The contacts provide power, and read or write, to cards of both the ISO and AFNOR/CP8 formats. Contacts (8 Pin) Two rows of four contacts are lowered on to the card. The contacts provide power, and read or write, to cards of ISO formats only. lowered on to the card ered
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Smart Card Contacts for ISO The positions of the contacts on an ISO standard card are shown in the figure below, with the position of the magnetic strip (on the underside of the card), shown by dotted lines.
1 2 3 4
5 6 7 8
Smart Card Contacts for AFNOR/CP8 The positions of the contacts on a AFNOR/CP8 standard card are shown in the figure below, with the position of the magnetic strip (on the underside of the card), shown by dotted lines.
8 7 6 5
4 3 2 1
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Function of Contacts The following table lists the functions of the card contacts.
Signal VCC RST CLK RFU GND VPP I/O RFU Contact No. 1 2 3 4 5 6 7 8 Function Card power supply voltage Reset signal Clock signal Reserved for future use Ground Not used Data input/output Reserved for future use
Power Requirements Power for the SCRW is supplied from the SCIF board for stopper pin lowering, lowering of contacts, and sensor operation. The maximum power required for these functions is shown below.
Voltage +VDD 24 Vdc +VDD 5 Vdc Current 800 mA (operating 50 mA (operating Regulation 10% 5% 250 mA p-p
EMV SCIF BOARD
SDC I/F
EMV SCIF
PIA
MCRW I/F
MCR/MCRW SDC I/F Board
PIA
SCRW
MCRW
In the following text the functions of the EMV SCIF are described with reference to four areas in the block diagram above.
z z z z z z
EMV SCIF core electronics MCR/MCRW SDC I/F Board SDC I/F MCRW I/F SCRW I/F SCRW/MCRW. In addition the following interfaces are also provided:
z Power interface
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z Power fail interface z Test connectors.

The schematics for the EMV SCIF Board are included at the end of this chapter. Refer to these schematic diagrams while reading the following circuit description. NOTE: Sheets 4 and 5 of the schematics show a possible future expansion to the interface board. This circuit is not described.
EMV SCIF CORE ELECTRONICS

The core of the EMV SCIF is the controlling electronics which is designed around an 8 bit embedded controller. The controlling electronics is described in the following subsections:
z z z z
Processor and support circuitry Memory and address decode Level 0 diagnostics Smart card interface signals.
Processor and Support Circuitry Refer to schematic sheet 3 when reading the following text. The processor is an TDA8006 8bit embedded controller operating at a frequency of 14.745 MHz which is provided by a TTL compatible clock oscillator with a 2K pull up resistor. This clock is also used to drive the smart card encryptor timing circuits. Port 0 of the processor operates as a multiplexed address/data bus with the address latched by the ALE signal. The serial port provides the communication interface with the smart card. The power-up/power-down and reset circuits are provided by a dedicated microprocessor supervisory circuit. (Maxim 691) device which supplies a continuous voltage to the RAM, thereby providing an area of non-volatile memory. A 3.6 volt 1 ampere-hour lithium battery supplies the RAM in the event of a power failure. Two fast reacting Schottky diodes are incorporated in the series path from the battery to the Maxim 691A device to prevent a possible charging current flowing into the battery. This satisfies UL/CSA safety requirements. A1 microfarad capacitor is included in the Maxim output circuit to provide smoothing when switching. The Maxim 691 also provides a reset signal which is used with the powerup cycle. This reset signal, which is active high, lasts for approximately 35 to 70 ms (typically 50 ms). A 2K pull-up resistor ensures a strong reset signal.
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Memory and Address Decode Refer to schematic sheet 4 when reading the following text. The memory available on the board consists of 64 KB of EPROM and 32 KB of battery backed RAM. Memory-mapped I/O is located from8000H upwards. This is above the 32K battery backed RAM. The overall memory map is shown in the following figure.
Code Area Data Area
0FFFFH
0FFFFH
Not Populated
9000H 8FFFH EPROM I/O 8000H 7FFFH NVRAM 7000H
Not Used
2000H 1FFFH SRAM 0000H 0000H
Owing to the high population density of the board, all decodes for address locations are performed by a 44-pin PLCC EPLD device. This device has a large number of output ports which allow both RD- and WR- qualification on address selection. The RD- and WR- qualification originates from the processor. Two 0.47 microfarad capacitors decouple the noise from the voltage plane as required by the EPLD internal architecture.
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The positions of the various ports in the memory-mapped I/O portion of the overall memory map are shown in the following table:
RD/WR RDWRRDRDWRWRWRRDWRRDWRport MCRW Port A MCRW Port A MCRW Port B SCRW Status Port SCRW Card Control Port Not used Not used Not used Not used Switch Pack Level 0 LEDs Level 0 8006H 8003H 8004H 8005H 8001H 8002H Address 8000H
Level 0 Diagnostics Refer to schematic sheet 5 when reading the following text. The Level 0 diagnostics are performed using an 8-way switch pack and eight LEDs. The 8-way switch pack U4 is used for setting and running the extended level 0 testing. The appropriate switch setting is obtained by reading memory mapped I/O at address 8006H. When the switch is open a logical low is read and, when closed, a logical high. The 8 LEDs display information about the level zero tests that are being run and also the result of the tests. The LEDs are accessed by writing to memory location 8006H. Each LED can be written to individually. A logical low signal turns the LED on, and a logical high turns the LED off. The switch pack and LED signals are brought out to a DUAL 10-way RDI connector along with a reset signal. This allows the board to be tested using a remote level 0 testing device.
INTERFACES
The SCIF provides the following interfaces:
z Power z PIA z Port A z Port B z SCRW interface z Input port z Output port z Solenoid drivers z Smart card interface z Smart card programming voltage (VPP) z Digital to analogue conversion z Vpp current limiting z Smart card clock generation z Smart card data (ISOn and AFNOR/CP8) z Smart card Vcc
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z Power fail interface z MVF and MCB sense circuit z MCF and MCB control output z Test connectors z Test evaluation connector z Remote diagnostic interface.
Power Interface Refer to the schematic sheet 2 when reading the following text. Dual 4-way connector J11 provides three power lines (+24V, +12V, +5V) and associated return Grounds. T ensure good noise immunity, these lines are connected directly into the inner planes of the PCB. PIA Interface Refer to the schematic sheets 1 and 9 when reading the following text. The EMV SCIF monitors the PIA interface. When a smart card instruction is recognised the EMV SCIF latches the data to the MCRW and assumes control. The SCIF executes the smart card instruction then passes control back to the host. The PIA interface can be divided into the sections, Port A interface and Port B interface. These are shown in the following figure:
Buffer 1 74ALS652 EMV SCIF EMV SCRW
MCRW Buffer 2 74F623 Buffer 3 Host PIA I/F 74ABT623 Status Information Data
Port A Interface Port A is an 8-bit wide bi-directional port which interconnects the following status information:
z z z z
EMV SCIF to host Host to EMV SCIF MCRW to host Host to MCRW.
NOTE: EMV SCIF to MCRW and MCRW to EMV SCIF never occur.
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The format of the signals is divided into sections A select, B select and C select as shown below. For more information on the signal functions refer to Chapters 7.2, 7.3, or 7.7.
Bit 0 1 2 3 4 5 6 7 A Select DW0 DW1 DW2 DW3 DW4 DW5 DW6 Not Used B Select DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 C Select PD1 PD2 PD3 Busy SW2 SW1 PD7 PD5 - PD6
The schematics (sheet 1 and 9) for the interconnections of Port A, show that a communication link is present between the host and the MCRW and between the host and the EMV SCIF. There is no direct communication between the EMV SCIF and the MCRW. The data is read and written by the EMV SCIF through buffer 1 (a 74ALS652, U37) which is mapped at memory location 8000H. Buffer 2 (a 74F623, U44) provides the interface between the host and the MCRW/SCRW. Buffer 3 (74F623, U36) enables bit 0 to 5 from the MCRW and PD5, PD6 and PD7 from the SCRW on to the hosts bus. When the SCIF is in the smart card mode buffer 2 and 3 are set to a high impedance.
DTA_s
DTAR
Data
Valid Data EMV SCIF to Host Handshaking Sequence
Data is written to the host using a handshaking mechanism that exists between the host and the MCRW and uses signals DATR and DTA. A similar method is used to transfer the data between the host and the EMV SCIF but using signals DTA_s and DATR_s. When a smart card command is identified, the data is latched into buffer 3 by writing to location 8000H. The host requests data by setting DATR low. The data is then put on the host bus by setting DATR_s low, DTA_s is also set low to indicate that data is present from the EMV SCIF. The host acknowledges receipt of the data by setting DATR high. The Handshake sequence is completed by setting DTA_s high.
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DTA_s
DTAR
Data
Valid Data Host to EMV SCIF Handshaking Sequence
A similar method of hand-shaking is used to read data from the host. The EMV SCIF sets DTA_s low to indicate to the host that data is required. The host responds to outputing the data to the bus and setting DATR low. The SCIF reads the data by reading memory location 8000H. DTA_s is reset high by the SCIF after the data is read and accepted. The host then resets the DATR signal high and DATR is checked to ensure that the host to EMV SCIF communication link is functioning correctly. Port B Interface The Port B interface carries the commands from the host to both the MCRW and the EMV SCIF. It is through this interface that the smart card instruction is sent. When the latch clock signal, LC, goes from a high to low transition an interrupt is generated and the EMV SCIF firmware checks for a smart card command. A smart card command is generated when:
z The SELECT signal is low z The SC MODE signal is low z The LC signal is an active low pulse.
The lower five bits of Port B are multiplexed by bit 7 of this port and are referenced as register A and register B. These signals are detailed below. NOTE: A hardware reset is generated by toggling PB3, Register A.
Port B Bit PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Register A MCF MCB SHE Reset SC Mode DATR Select LC Register B TS0 TS1 RW0 RW1 DT
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Port B is located in memory mapped I/O at address 8001H. The Port B commands from the host to the MCRW are interfaced through buffer 5 (a transparent latch 74LS373, U45). When the EMV SCIF detects a smart card command the SCIF_En signal is set high latching the signal from Port B to the MCRW. SCRW Interface Refer to schematic sheet 6 and 7. The MCRW interface is mapped in memory I/O at location 8002H and consists of an input and an output port. All signals associated with the status, that is, the sensors and control for the solenoids, are connected through this interface. Input Port The input port (a 74HCT244,) is accessed by reading data from memory location 8002H. The signals associated with each bit are listed below:
Bit 0 1 2 3 4 5 6 7 Signal PD7 PD5 PD6 Not used Not used Not used Not used Not used
A description of each bit follows:
z Bit 0 - PD7 indicates if a card is present in the SCRW. A logical high signal z z z z z z z
on this line indicates that a card is present. On power up, when no card is present, this signal is low Bit 1 - PD5 reflects the status of the SCRW stop pin which is used to position the card for correct contact alignment. The signal is low if the pin is in the lowered position Bit 2 - PD6 indicates the position of the smart card contacts. If the contacts are down and in contact with the card PD6 is a logical low. If the contacts are up and not in contact with the card PD6 is high Bit 3 - Not used Bit 4 - Not used Bit 5 - Not used Bit 6 - Not used Bit 7 - Not used.
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Output Port U24 (a 74F259 latch) generates the signals on the SCRW output port. This allows each bit to be individually addressed. A coded byte is written to location 8002H in the memory mapped I/O area. The byte is then decoded by the hardware and the appropriate output bit set. The coded bytes should be written to the output port, and the expected output, are given in the table below:
Data Bit Bit 0 1 2 3 4 5 6 7 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 4 L L L L H H H H 5 L L H H L L H H 6 L H L H L H L H Byte (hex) 00-low 10-low 20-low 30-low 40-low 50-low 60-low 70-low 01-high 11-high 21-high 31-high 41-high 51-high 61-high 71-high O/P Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Signal MCF_s MCB_s STP TUD SCIF_En Not used Not used Not used
A description of each signal follows:
z MCF_s - This signal controls, in conjunction with the MCB_s signal, the z z z z z
motor direction. When MCF_s is high and MCB_s is low the card moves forward in the MCRW MCB_s - This signal controls, in conjunction with the MCF_s signal, the motor direction. When MCB_s is high and MCF_s is low the card moves backwards in the MCRW STP - This signal operates the card stop solenoid. The solenoid is activated when STP is set high TUD - This signal operates the smart card contact solenoid. When TUD is set high the solenoid activates lowering the contacts on to the smart card SCIF_En - This bit is set high to enable the SCIF and disable/latch the PIA signals to the MCRW CLK_SEL (CLOCK_SELECT) - Not used.
NOTE: The outputs of this buffer are all set low by a system reset. Solenoid Drivers The card stop pin and card contact solenoids are controlled by Darlington power transistors. The STP and TUD signals are pulled high to 5 volts through 2K2 resistors. This ensures sufficient base drive to saturate the transistors. Current limiting is obtained by a 470R resistor in the series path of the base. Noise decoupling from the transistor base is obtained by a 0.1 microfarad capacitor. This reduces any ringing effect that may result from high speed switching. Any back emf is decoupled by connecting two Schottky diodes in reverse mode across the solenoid coils.
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Smart Card Interface Refer to schematic sheet 3. The smart card signals originate from the Philips TDA8006 custom microprocessor. This custom device is designed with compatibility for emerging standards such as EMV, GIE CB and Mondex. All these standards request that Vpp is not connected to contact C6 as specified by ISO 7816. An enable link is implemented on the EMV SCIF interface so that where systems require Vpp it may be configured. The default is Vpp disconnected. The TDA8006 supports all other signals from the smart card (Data I/O, reset, Vcc, clock). TDA8006 Internal Architecture) The Philips TDA8006 custom microprocessor has three major blocks associated with the setup and control of the smart card signals. The 80C52 core addresses these blocks through four address lines (P1.2 to P1.5), two control lines (P1.6 and P1.7), and an 8-bit data bus (P4.0 to P4.7). The figure below shows the basic structure:
80C52 Core P4.0 to P4.7 P1.6 & P1.7 P1.2 to P1.5 Control Lines Address Bus Data Bus
En& R/W-
ADO to AD3
Data Bus
En& R/W-
ADO to AD3
Data Bus
En& R/W-
ADO to AD3
Data Bus
ISO 7816 UART
ON/OFF Sequencer
Clock Generator
Smart Card Interface Circuitry
Smart Card
Each block contains registers that require setting before the device becomes operational. The mechanism to address, read and write to/from these blocks listed in the table below: Two control signals are used to transfer data to or from the data bus. The enable signal (En-), when set to low, permits data to flow between the 80C52 core and the registers within each functional block. The second contgrol signal (R/W-), controls the direction the data flows, if R/W- is set high then data is read and if R/W- is low, then data is written.
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NOTE: After resetting En- high, the controller must set P4 high to free up the data bus. The address lines AD0 to AD3 are used to select the appropriate register. The read and write procedures are summerized as follows:
z Read operation z Set P4 to FFH z Select the appropriate register with AD0, AD1, AD2, AD3 z Set R/W- high z Set En- low, the data is available on the data bus z Read the data z Set En- high z Set P4 to FF hex, the bus is back to high Z z Write operation z Select the correct register with AD0, AD1, AD2, AD3 z Set R/W- low z Write the data to the data bus z Set En- low, the data is written into the register z Set En- back high z Set P4 to FF hex, the bus is back to high Z.
These sequences are summarized as follows :
P4 XX FF DATA FF DATA FF
R/W
AD0...3
AD
AD
EN READ DATA CYCLE WRITE DATA CYCLE
The addresses of the various control registers are listed in the table below.
Functional Block Clock Generator Register Clock Configuration Register (CCR) Programmable Divider (PDR) ISO 7816 UART Synchronous Out Register (SOR) Synchronous In Register (SIR) UART Transmit Register (UTR) UART Receive Register (URR) UART Status Register (USR) UART Configuration Register (UCR) Guard Time Register (GTR) ON/OFF sequencer Peripheral Extension Register (PER) W/R- AD0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 AD1 0 0 1 1 0 0 0 0 1 1 AD2 0 0 0 0 1 1 1 1 1 1 AD3 0 0 0 0 0 0 0 0 0 0
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The setup procedures and functions of each register is explained in the following sections. Clock Generator Configuration The clock to the microcontroller (OSC), the clock to the card (CLK), the clock to the ISO 7816 UART and the clock to the external world (LCLKOUT) are derived from the main clock signal (XTAL = 14.745 MHz), or the internal oscillator (f INT). The frequencies at which each clock operates is determined by the contents of two, write only, registers - namely the CCR and the PDR. The following two tables show the possible setup configurations: Clock Configuration Register (CCR)
D7 X X X x X X X X X X X 0 0 1 1 D6 X X X x X X X X X X X 0 1 0 1 D5 X X X x X X X X 0 0 1 X X X X D4 X X X x X X X X 0 1 0 X X X X D3 X X 0 0 0 0 1 1 X X X X X X X D2 X X 0 0 1 1 0 0 X X X X X X X D1 X X 0 1 0 1 0 1 X X X X X X X D0 0 1 X X X X X X X X X X X X X UART /31 /32 Stop low XTAL/2 XTAL/4 XTAL/8 Fint/2 Stop high XTAL/4 XTAL XTAL/2 Fint/8 XTAL XTAL/2 Fint/2 CLK CLKOUT OSC
Programmable Divider Register (PDR)

D7 x7 D6 x6 D5 x5 D4 x4 D3 x3 D2 x2 D1 x1 D0 x0 Division factor x7x6x5x4x3x2x1x0 hex
After power-on or reset, the microcontroller is clocked with fINT/8. On completion of the power-on sequence, the application may decide to change the operating clock frequency to f INT/2, or fXTAL/2 or fXTAL. All frequency changes are aynchronous, ensuring no hang-up due to short spikes etc. It is possible to select one of four different frequencies for the smart card clock (CLK) output. The frequencies are fXTAL/2, fXTAL/4, fXTAL/8 or fINT/2 (1.2 MHz), the clock signal can also be stopped in either the high or low logical states. All transitions are synchronous, ensuring correct pulse length during start or change in frequency, in accordance with ISO 7816. After power-on or reset, CLK is stopped at low level.
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The clock that drives the ISO 7816 UART originates from the clock that drives the smart card clock contact. To achieve the different baud rates on I/O as defined by the F and D parameters (as specified in ISO 7816 part 3), a prescaler (divide by 31 or 32) and an autoreload 8 bit programmable counter is implemented (internal to the TDA8006). The following table shows what values should be loaded to archive the appropriate F and D values.
D
\F
0000
0001
0010
0011
0100
0101
0110
1001
1010
1011
1100
1101
0001 0010
31;F4 31;F4 31;EE 31;E8 31;DC 31;D0 31;C4 32;F0 32;E8 32;E0 32;D0 32;CD 31;FA 31;FA 31;F7 31;F4 31;EE 31;E8 31;E2 32;F8 32;F4 32;F0 32;E8 32;E0 31;FA 31;F7 31;F4 31;F1 32;FC 32;FA 32;F8 32;F4 32;F0 31;FD 31;FA 31;FD 32;FE 32;FD 32;FC 32;FA 32;F8 32;FF 32;FE 32;FD 32;FC 32;FF 32;FE
0011 31;FD 31;FD 0100 0101 0110 1000 -
31;FF 31;FF -
31;FE 31;FD 31;FC 31;FB 31;FD -
32;FE -
32;FC -
1001 -
NOTE: The prescalar value is first and the PDR value is second. On/Off Sequencer Configuration The on/off sequencer block main function is to control the activation/ deactivation of the smart card interface. The register that addresses this function is called the Peripheral Extension Register (PER). The PER is a write only register. The bit allocation of the PER is as follows:
Bit D0 D1 D2 Name CMDVCC RSTIN FIP (Force Inverse Parity) Description Set high to start activation sequence Set low to start de-activation sequence Set card RST control to minimum Set low to process data parity as specified by ISO7816 part 3. Set high to process data in an inverse format. (This forces parity errors in transmission and NAKs in reception - to aid testing) Set high to allow automatic control of ATR processing. Set low to disable automatic ATR processing. Auxiliary 2mA push-pull output control (Inverted output) Auxiliary 2mA push-pull output control (Inverted output) Auxiliary 2mA push-pull output control (Inverted output) Auxiliary 2mA push-pull output control (Inverted output)
D3 D4 D5 D6 D7
ATREN (Automatic ATR processing enable) K0K1K2K3-
The activation and de-activation sequences can only be initiated after the ISO7816 UART has been reset and the card present bit is set. The activation sequence is initiated by setting CMDVCC (PER, bit D0) high, conversely to deactivate the smart card contacts this bit must be set low. To initiate a warm reset, toggle RSTIN (PER, D1). Activation/de-activation of the smart card contacts can be set to automatic or manual mode by configuring bit D3 of the PER. When set for automatic mode the UART starts counting the clock cycles during the ATR and the smart card RST signal is controlled as specified by ISO7816 part 3. Data is received before 2x45,000 smart card CLK cycles, if data is detected, this bit is reset and
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the ATR is collected. If the UART detects no data within the specified time frame then the card is declared mute, this bit (PER, D3) is reset by the hardware. The UART can be forced to operate with inverse parity checking. This is used to generate parity errors in transmission of data and generate NAKs during reception of data. This is only used as a debug tool. ISO 7816 UART The UART associated with the smart card signals is fully compliant with ISO 7816 part 3 supporting both T=0 and T=1 protocols (in conjunction with the appropriate libraries). Synchronous cards are also supported by this device. There are seven registers associated with this functional block, two registers (GTR and UCR) are used to configure the UART, the remaining registers are used for data and status information. The registers are listed in the following table, with subsequent sections describing their functions.
Symbol UTR URR USR SIR SOR GTR UCR Expanded name UART Transmit Register UART Receive Register UART Status Register Synchronous In Register Synchronous Out Register Guard Time Register UART Configuration Register Function Data control Data control Status Information Data control Data control Control Control
UART Configuration Register (UCR) The UART Configuration Register (UCR) is used to configure the UART. The UCR is a write only register. The bit allocation and association functions are as follows:
Bit D0 D1 Symbol RIUN SS Name Reset ISO UART Start Session Description Set low to reset the UART Must be set high to allow UART use. Set high to allow auto detection of the convention indicated by the initial character during ATR. Set high to allow automatic toggling between transmission and reception after a successful transmission. Set high to enable transmission mode. Set low to enable reception mode. An interrupt is generated when TRN is set. Not used Protocol Selection 3V/5V Synchronous/Asynchronous -N Set high to enable protocol T=1. Set low to enable protocol T=0. Set high to enable 3V operation. Set low to enable 5V operation. Set high to allow direct monitoring of I/O. Set low to allow I/O to feed into the UART.
D2
LCT
Last Character to Transmit
D3
TRN
Transmit/Receive - N
D4 D5 D6 D7
Not used PS TFN SAN
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In order to start a session with the card, the bit RIUN (UCR,D0), which resets the ISO7816 UART when low, must be set high. Reception: During reception, the UART recognises the convention (direct or inverse) on the characters received while the Start Session (SS) bitis high. The UART automatically converts any transmitted or received characters accociated to this convention into characters written in direct convention. NOTE: Thetart Session bit must be reset after correct reception of the first character (TS) of the ATR and before complete reception of the next character. Reception mode is selected when TRN is set low. An interrupt is generated (if set to do so) that indicates when a character has been received. The interrupt is cleared on the rising edge of the En- signal during a read cycle from the UART Receiv Register (URR). ISO7816 part 3 defines the format and protocol characteristics of the received data. Transmission: Transimssion mode is selected by setting TRN high. If enabled, an interrupt is generated on the rising edge of TRN, indicating that the transmission buffer is empty and may be written to. The character is written into the UTR on the falling edge of En- and during the write operation. Its transmission starts on the rising edge of En-. ISO7816 part 3 defines the format and protocol characteristics of the transimtted data. Guard Time Register (GTR) The Guard Time (GT) is a requirement of ISO7816 part 3, and is used to slow down the transmission and reception of characters. the GT value is generally passed back by the smart card when powered on initially (although the application can also set GT using the protocol type select command). The GTR ia a writ only register and is structured as follows:
D7 x7 1 D6 x6 1 D5 x5 1 D4 x4 1 D3 x3 1 D2 x2 1 D1 x1 1 D0 x0 1 Guard time T=0 Guard time T=1
x7x6x5x4x3x2x1x0 hex x7x6x5x4x3x2x1x0 hex 0 -1
UART Receive Register (URR) The UART Receive Register (URR) is located at address 4 and is read only. The data received from the card is transferred in direct convention (as specified by ISO7816 part 3). The received character is loaded into the URR 0.5 etu after receipt of the parity bit. It is therefore essential that the previous character is read prior to this time, otherwise the old character will be over written and lost. The parity is automatically verified during character reception, the Parity Error (PE) flag in the USR is set if an error is detected. At the same time the Receiv Buffer Full (RBF) flag is also set in the USR.
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UART Transmit Register (UTR) The UART Transmit Register (UTR) is located at address 4 and is write only. The data to be transmitted is written to register in direct convention (as specified by ISO7816 part 3), the UART will then re-structure the data (as specified by the TS format character). The Transmit Buffer Empty (TBE) flag is set in the USR to indicate when data can be loaded into the UTR. If this occurs beyond 12.5 etu + GT after the previous start bit, then the transmission starts on the rising edge of En- during the write operatiopn. If this occurs before 12.5 etu + GT, then the UART will wait until 12.5 etu + GT after the previuus start bit before starting the transmission. UART Status Register (USR) The UART Status Register (USR) is located at address 5 and is a read only register. The register supplies information relating to the activity of the UART and is used extensively to control the flow of traffic while receiving/ transmittion data.
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NOTE: All bits with the exception of bit D5 will generate an internal interrupt (INT-) when reset. In case of Early Answer (EA) or Mute Card (MC) during automatic ATR processing, the card is not automatically deactivated. An interrupt is generated if enabled, and it is up to the controller to deactivate or not.
Bit D0 Symbol TBE Name TX Buffer Empty Description This bit is set when the UART has finished transmitting data, or on the rising edge of TRN. It is reset on the rising edge of En-, during a read status operation. This bit is set when the UART has finished receiving a character from the card. It is reset on the falling edge of En-, during the read character operation. This bit is set on the falling edge of the first start bit if SS = 1. It is reset on the rising edge of En-, during a read status operation. This bit is set when a parity error is detected (by the UART) when the UART is transmitting or receiving data. It is reset on the rising edge of En-, during a read status operation. This bit is set if a start bit is detected on I/O between 200 and 400 CLK pulses (when the UART is configured in Automatic ATR poeration). It is reset on the rising edge of En-, during a read status operation. This bit is set if th ecard is present and reset if the card is not present. If CMDVCC is high, it may also be reset if a hardware problem causing an emergency deactivation sequence has occurred. OFF Interrupt This bit is set when OFF (bit D5) changes. It is reset on the rising edge of En-, during a read status operation. This bit is set if a card has not answered after 90000 CLK pulses when the ISO7816 UART is configured in Automatic ATR processing. It is reset on the rising edge of En-, during a read status operation.
D1
RBF
RX Buffer Full
D2
FSD
First Start Detect
D3
PE
Parity Error
D4
EA
Early Answer
D5
OFF
D6
OFFI
D7
MC
Mute Card
Synchronous Cards It is not a requirement of the EMV SCIF to provide an interface for synchronous cards. However, the TDA8006 is capable of communicating with synchronous cards and therefore, for completeness, this section briefly describes the synchronous function. If SAN (UCR, D7) is set then the software may deal with synchronous card. I/O is copied on bit data0 of the data bus when SIR or SOR registers are selected, without entering the UART. The synchronous cards clock can be controlled by selecting STOP HIGH or STOP LOW on CLK. When the Synchronous Input Register (SIR) is selected, I/O is copied on data0 (P40). When the Synchronous Output Register (SOR) is selected, then data0 (P40) is output onto the I/O line on the falling edge of En-.
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Smart Card Signal Chaacteristics Reset Signal The drive capabilities of the Reset signal pin is as follows:
Symbol VOL VOH tr tf Parameter Low level output voltage High level output voltage Rise time Fall time Conditions IOL=200uA IOH=200uA C1=30pF C1=30pF Min 0 Vcc-0.5 Typ Max 0.3 Vcc 0.1 0.1 Unit V V uS uS
Clock Signal The drive capabilities of the Clock signal pin is as follows:
Symbol VOL VOH tr tf F Parameter Low level output voltage High level output voltage Rise time Fall time Frequency Conditions IOL=200uA IOH=200uA C1=30pF C1=30pF Min 0 Vcc-0.5 1.25 Typ Max 0.3 Vcc 8 8 6 Unit V V nS nS MHz
I/O Signal The drive capabilities of the smart card I/O signal is as follows:
Symbol VOL VOH VIL VIH tr, tf tr, tf Rpu Parameter Low level output voltage I/O configured as output High level output voltage I/O configured as output Low level input voltage I/O configured as input High level input voltage I/O configured as input Input transition times Output transition times Internal pull-up resistor between I/O and Vcc C1=30pF C1=30pF Conditions IOL=1mA IOH<=-50uA Min 0 Typ Max 0.3 Vcc+0.25 0.8 Vcc 1 0.1 12K Unit V V V V uS uS Ohms
0.8xVcc -0.3 1.5 8K 10K
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Vcc Signal The drive capabilities of the smart card Vcc signal is as follows:
Symbol Parameter Conditions no load 1mA injected Icc <65mA; 5V card Icc <65mA; 3V card Current pulses of 40nAs with I<200mA, t<400nS, f<20MHz; 5V card Current pulses of 24nAs with I<200mA, t<400nS, f<20MHz; 3V card Icc Output current 3V and 5V Overload detection Shutdown current Vcc shorted to ground SR Slew Rate Up or down (max cap 300nF) Min 0 0 4.75 2.8 4.6 Typ 5 3 Max 0.1 0.3 5.25 3.2 5.4 Unit V V V V V
Vo(inactive) Output voltage inactive Vcc Output voltage
2.75
3.25
0.10
80 -90 0.16
65 250 0.22
mA mA mA mA V/uS
Vpp Signal The default setting for the smart card Vpp signal is no condition as specified by the EMV requirements document. There is a link that lets the smart card Vcc signal to be routed to the Vpp signal. Voltages greater than 5V on the Vpp line are not supported. Power Fail Interface Schematic sheets 11 and 12 show part of the SCIF circuit which is not used in 56XX SSFTs but is used by the power-fail module in 50XX ATMs. This is described in Chapter 3.9 of the Test Connectors Refer to schematic sheets 8, 10 and 17. Three test connectors are provided, a test evaluation connector, a remote diagnostic interface connector, and a smart card signal connector. Test Evaluation Connector Dual 4-way connector J16 provides an interface for test evaluation processes. It is used mainly during board manufacture. The signals available at J16 are as follows:
z The three major clock signals 12 MHz, 14.31818 MHz and 19.6608 MHz z The serial link signals, RXD and TXD z The system reset signal, Test_Reset.
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Remote Diagnostic Interface The Remote Diagnostic Interface (RDI) is a dual 10-way connector, J9, which provides the interface with the Level 0 diagnostic switch pack, U4, and LEDs. These TTL-compatible signals are 8 bits wide. A reset line, RDI_RE_SET, which is also TTL-compatible, is also provided and can be used to reset the SCIF hardware. Smart Card Signals Connector Dual 3-way stake pin header J12 is provided to make it easier to test and monitor the smart card signals rather than via the flexible signal connectors J8 and J10. The signals on J12 pass via the flexible circuit connectors and, therefore, breaks in the tracks on the SCIF pcb will also be detected. This connector is only fitted to early EMV SCIF boards.
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ERROR CODES AND DIAGNOSTICS

LEVEL 0 DIAGNOSTICS
Level 0 diagnostics tests for the SCIF/EMV SCIF execute whenever power is applied or a hardware reset occurs. There are two modes of operation:
z Start-up. A sequence of tests which takes no longer than 10 seconds to run z Extended Level 0 diagnostics. Individual tests can be selected to run.
All the diagnostics tests performed during the start-up diagnostics can also be performed by using the extended diagnostics. NOTE: There are no Loop or Continue on Error options available with these diagnostics. Switch Settings Select the diagnostic mode using the eight switches (SW1 to SW8) located on the diagnostic switchpack. These switches are numbered 1 (LSB), for the right-most switch, to 8 (MSB), for the left-most switch.
Switch No. Start-Up Selected 0 = Switch open 1 = Switch closed SW8 0 1 SW7 0 0 SW6 0 0 SW5 0 SW4 0 SW3 0 SW2 0 SW1 0
<--------------------TEST ID------------------>
LEDs The test results display on the eight LEDs, D1 to D8. These LEDs are numbered 1 (LSB), for the right-most LED, to 8 (MSB), for the left-most LED. The test number displays on LED 1 to 5. If a test fails, the test number shows for one second and the test result shows for two seconds. If a bad switch setting is made, the LEDs do not flash but display the following error code:
z ODH - bad Switch Setting.
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Test Descriptions EMV-SCIF The tests available are identified by a unique number. The following table shows the test ID, the test description and whether they are available in the Start-up or Selected mode. the majority of tests available only in Selected mode.
Test ID 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Test Description CPU and EPROM Test RAM data Test RAM Address Test NVRAM Initialize (Dual Voltage Disabled) NVRAM Initialize (Dual Voltage Enabled) Smart Card Test Card Clock - Stop Low Card Clock = XTAL/2 MHz Card Clock = XTAL/4 MHz Card Clock = XTAL/8 MHz Card Clock = FINT/2 Card Clock - Stop High Card Signals Toggle Exercise Stopper Pin Exercise Contact Unit X Start-Up X X X Selected X X X X X X X X X X X X X X X
z z z z z
CPU registers. All register banks are tested CPU instructions. Arithmetic and manipulation instructions are tested Stack, Push and Pop sequence EPROM - Cyclic Redundancy Check (CRC) calculation Internal RAM. This is tested by writing alternate 55, AA and FF bytes in RAM. These values are checked. If O.K., inverted checked again z CPU special purpose timers and interrupt registers are tested. Test Results
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Test 02 - External Memory Description The following tests are performed:
performed when smart card encrypyion (SCE) is not used. Test Results
NOTE: If test results 09 or 0D are returned, corrective action must be taken to replace the battery or SRAM. On replacement Test 04 or 05 must be performed to ensure that the EMV-SCIF is installed. This test will write a header block to NVRAM, calculate and store a CRC for the contents of NVRAM. Test 03 - External Data Memory Address and Data Lines Description The volatile RAM is filled with zeroes, except for byte 00, which is filled with FF hex. The contents of RAM is then verified. The RAM contents is then read using an address of 1 left rotating zero that is 1, 2, 4, 8, 16.... . If the data read from these addresses equals FF hex, the external connection of that address line is faulty. If the data read of one of the addresses is neither 00 or FF hex, one or more data lines are faulty. The non-volatile memory contains FF hex on byte 00 zero bytes on addresses having only one bit set that is 1, 2, 4... . If the data read from these addresses equals FF hex, external connection of that address line is faulty. If the data read from one of the addresses is neither 00 nor FF hex, one or more data lines are faulty. The information stored in the non-volatile memory is placed so that it does not interfere with the check bytes. This test is not applicable when a smart card encryptor is used. Test Results
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Test 04 - NVRAM Initialize Disabled Description The area of NVRAM from external data memory addresses 7000H to 8000H is initialized. During this process the memory is over written with zeros, a header block is written into NVRAM and a CRC is done over the contents of NVRAM and the result written. This test is done to indicate a start of life condition for the EMV-SCIF board. Test Results
Test 05 - NVRAM Initialize Enabled Description The area of NVRAM from external data memory addresses 7000H to 8000H is initialized. During this process the memory is over written with zeros, a header block is written into NVRAM containing an additional byte indicating the support of Dual Voltage Cards, and a CRC is done over the contents of NVRAM and the result written. This test is done to indicate a start of life condition for the EMV-SCIF board. Test Results
NOTE: Either test 04 or 05 must be performed the first time the EMV-SCIF is powered on. If either test has not been run, the header block and CRC will not have been written into NVRAM. Test 02 will always fail. Similarly if the battery or SRAM has been replaced, this test must be run the first time the EMV-SCIF is powered on. Test 06 - Smart Card Communication Test Description The interface to the IC card on the EMV-SCIF is controlled exclusively by the Philips TDA8006 Device thus constricting direct access to the SC signals. The level of testing performed by this test depends on whether it is called as part of the Start-up test, or as a Selected Test. Start-up testing performs a limited compared to the Selected Test. Test Results
LEDs 00H 08H 09H 0AH Status Test passed Initialisation of system failure (Error at library procedure Init_System) I/O line not at zero Card Present (For Start-Up: Error at library procedure Power-Up)
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Test 07 - Card Clock - Stop Low Description The EMV-SCIF sets the card clock low. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 08 - Card Clock = XTAL/ 2 MHz Description The EMV-SCIF sends a clock signal of XTAL/ 2 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 09 - Card Clock = XTAL/ 4 MHz Description The EMV-SCIF sends a clock signal of XTAL/ 4 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 0A - Card Clock = XTAL/ 8 MHz Description The EMV-SCIF sends a clock signal of XTAL/ 8 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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Test 0B - Card Clock = FINT/ 2 MHz Description The EMV-SCIF sends a clock signal of FINT/ 2 MHz to the smart card clock contact. The clock signal can be measured using an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 0C - Card Stop High Description The EMV-SCIF sets the card clock high. The clock signal can be measured with an oscilloscope. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned. Test 0D - Card Signal Toggle Description The EMV-SCIF toggles the smart card Vcc, Resety and I/O line. At the start of this test the contacts are lowered but no lower position checking is made. NOTE: During the execution of this test, the diagnostic LEDs flash the test ID. No error response is returned. Test 0E - Exercise Stopper Pin Description The EMV-SCIF performs the following sequence: 1. 2. 3. 4. 5. 6. 7. Activates the stopper pin solenoid. Checks for lower pin position. Waits one second. Deactivates the stopper pin solenoid. Checks for upper pin position. Waits one second. Repeats steps 1 to 6.
NOTE: During the execution of this test, the diagnostic LEDs display the test ID. No error response is returned.
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Test Results Test No. and test results shown on the LEDs are:
Test 0F - Exercise Contact Unit Description The EMV-SCIF performs the following sequence: 1. 2. 3. 4. 5. 6. 7. Activates the contact unit solenoid. Checks for lower contact unit position. Waits one second. Deactivates the contact unit solenoid. Checks for upper contact unit position. Waits one second. Repeats steps 1 to 6.
LEDs 09H Status
Contact Unit failed to reach either the low or high position
LEVEL 1 DIAGNOSTICS
The level 1 diagnostic tests available for smart card are:
z z z z z z z z z
SMART CARD STAGE SMART CARD RESET SMART CARD RELEASE SCIF INITIALISE SCIF SOLENOID SCIF IDENTIFY RUN-TO-RUN 1 RUN-TO-RUN 2 RUN-TO-RUN 3.
SMART CARD STAGE The SMART CARD STAGE test moves the card from the MCRW transport into the SCRW and brings the contacts down on to the card. SMART CARD RESET The SMART CARD RESET applies power to the card under the contacts. The resultant data stream from the smart card is displayed. SMART CARD RELEASE The SMART CARD RELEASE test raises the card contacts and moves the card out of the SCRW back into the MCRW transport.
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SCIF INITIALISE The SCIF INITIALISE test causes the SCIF board to switch into SCRW mode and toggle the SCIF reset line. Power is removed from any card present and the smart card contacts and stopper pin solenoids are de-energized. The SCIF board switches to MCRW mode. SCIF SOLENOID The SCIF SOLENOID test activates the SCRW stopper pin and contact solenoids. NOTE: The card should not be in the SCRW when this test is selected. SCIF IDENTIFY The SCIF IDENTIFY test allows the operator to display or print the ROM firmware number as T_DATA. The firmware ID is returned as an 21 digit ASCII coded number similar to the following:
<---------ROM Firmware ID---------> 14
00 00 00 30 30 39 30 31 36 32 31 34 30 3X 30 30 30 30 30 30 30
Where,
z The first 3 digits are 0 z The next nine digits contain the EPROM ID number. The example above
shows the EMV EPROM number 009016214. Notice that the number after the 9 is one digit short of the actual part number that appears on the EPROM label. The full number is 009-0016214. z Digit 13 and digits 15 to 21 all have the value 0. z Digit 14 (X) can take the following values: z 0 = non-EMV SCIF z 5 = 5 V only, is applied to the smart card during the Power Up sequence z 3 = 3 V is applied to the smart card during the Power Up sequence and, if no valid ATR is returned, then 5V is applied. The value 3 therefore means that Dual Voltage Support is enabled. Refer to Level 0 Diagnostics Test 05H, in Chapter 4.2.9). RUN-TO-RUN 1 The RUN-TO-RUN 1 test automatically performs the following tests in sequence:
z z z z z z z z z z
SHUTTER/SENSOR ENTER READ ISO TRACK 1 (If configured) READ ISO TRACK 2 READ ISO TRACK 3 (If configured) SMART CARD STAGE SMART CARD RESET SMART CARD RELEASE EJECT CAPTURE.
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NOTE: See the appropriate MCR/MCRW chapters in this manual for disruptions of tests not specific to smart card. RUN-TO-RUN 2 The RUN-TO-RUN 2 test automatically performs the following tests in sequence:
z ENTER z CAPTURE.
NOTE: See the appropriate MCR/MCRW chapters in this manual for disruptions of tests not specific to smart card. RUN-TO-RUN 3 The RUN-TO-RUN 3 test automatically performs the following tests in sequence:
z z z z z z z z
ENTER READ ISO TRACK 1 (If configured) READ ISO TRACK 2 READ ISO TRACK 3 (If configured) SMART CARD STAGE SMART CARD RESET SMART CARD RELEASE EJECT.
NOTE: See the appropriate MCR/MCRW chapters in this manual for disruptions of tests not specific to smart card. M_STATUS M_STATUS values, and their meaning for the SCRW, are shown below. Original severity is also shown. The M_STATUS codes for the associated MCRW are given in the appropriate Chapter in this manual, refer to Chapter 7.2, 7.3 or 7.7 as required.
M_STATUS 50 51 52 53 54 55 57 Meaning Card not in SCRW stage position. Smart card stopper pin lowered, unable to capture. This is only in response to card capture. Invalid smart card command code error. Invalid smart card command data error. SCIF not configured/not responding. SCIF response timeout exceeded. Invalid smart card response length. Original Severity 2 4 2 2 2 2 2
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Additional M_STATUS codes may be returned by the SCIF as shown below.

M_STATUS 00 64 65 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Good Invalid command code Invalid command format Invalid key ID Invalid key type Invalid host key type Invalid key - does not exist Invalid password - not decimal Invalid password - no match Key integrity error Key parity error Invalid data format Stopper pin failure Contact unit failure Card movement failure SC switch off failure Smart card removed error No smart card response Smart card transmission error Smart card switched off Illegal card type/parameter Power up time exceeded ANSI X9.8 pin block error Meaning
M_DATA Entries are returned in Byte 0 and 4 as follows: Byte 0

70H = SCIF Command
Byte 4
Bit 1 - PD5/6 (1 = stopper pin/contacts down) Bit 0 - PD7 (1 = blocked).
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LEVEL 2 DIAGNOSTICS
None.
LEVEL 3 DIAGNOSTICS (TALLIES)

The EMC SCRW firmware updates a number of tallies. These tallies are updated in diagnostic and normal modes. The tallies are as follows:
z SMART CARD STOPPER PIN SOLENOID ACTUATION ATTEMPTS z

(SPSOLOPS) - Incremented when the smart card stopper pin solenoid is actuated during execution of the command to stage the smart card SMART CARD STOPPER PIN SOLENOID ACTUATION FAIL (SPSOLERR) - Incremented when the smart card stopper pin solenoid is actuated but the stopper pin is detected not to have moved, during execution of the command to stage the smart card SMART CARD CONTACTS SOLENOID ACTUATION ATTEMPTS (STSOLOPS) - Incremented when the smart card contacts solenoid is actuated during execution of the command to stage the smart card SMART CARD CONTACTS SOLENOID ACTUATION FAIL (STSOLERR) - Incremented when the smart card contacts solenoid is actuated but the contacts is detected not to have moved, during execution of the command to stage the smart card NON SMART CARD DETECTED (NONSCDET) - Incremented when the card present is detected not to be a smart card, during the execution of the command to power on the smart card SMART CARD DETECTED (SCDETECT) - Incremented when the card present is detected to be a smart card, during the execution of the command to power on the smart card ISO SMART CARD DETECTED (ISOSCDET) - Incremented when the card present is detected to be an ISOtype smart card, during the execution of the command to power on the smart card AFNOR/CP8 SMART CARD DETECTED (CP8SCDET) - Incremented when the card present is detected to be a AFNOR/CP8 type smart card, during the execution of the command to power on the smart card SMART CARD RESET ATTEMPT (SCRESETS) - Incremented when a smart card reset is carried out during the execution of the command to power on the smart card SMART CARD ANSWER TO RESET FAIL (SCRSTERR) - Incremented when an error is found in the answer to reset during the execution of the command to power on the smart card SMART CARD POWER ON TIMEOUT (SCPWRTIM) - Incremented when the limit on the specified smart card power on time has been reached SCIF COMMS ATTEMPTS (SCIFCMAT) - Incremented when an attempt is made by the device controller to send or receive a message to or from the SCIF SCIF COMMS FAIL (SCIFCMFL) - Incremented when the device controller fails in its attempt to send or receive a message to or from the SCIF SCIF RESPONSE TIMEOUT (SCIFRSPT) - Incremented when the SCIF fails to respond within the timeout specified by the SCIF command message SMART CARD COMMS ATTEMPTS (SCCOMAT) - Incremented when a communication is attempted between the SCIF and the smart card
z z
z z z z z z z z z z z
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z SMART CARD COMMS RETRIES (SCCOMRTY) - Incremented when a

communication retry was successfully carried out during the execution of a smart card related command z SMART CARD RESPONSE TIMEOUT (SCRSPTIM) - Incremented when the SCIF reports that the smart card has failed to respond within the specified timeout z SMART CARD INTERFACE REINITIALIZATION ATTEMPTS (SCIF_RES) - Incremented when Reinitialization command issued. Tally numbering and threshold values are shown in the following table.
Tally Mnemonic SPSOLOPS SPSOLERR CTSOLOPS CTSOLERR NONSCDET SCDETECT ISOSCDET CP8SCDET SCRESETS SCRSTERR SCPWRTIM SCIFCMAT SCIFCMFL SCIFRSPT SCCOMATT SCCOMRTY SCRSPTIM SCIF_RES Number 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS SCRESETS CTSOLOPS SCRESETS SCRESETS SCRESETS SCRESETS SPSOLOPS Frame of Reference Threshold REF10000 10 REF10000 10 N/A N/A N/A N/A REF1000 1000 N/A N/A N/A N/A N/A N/A N/A N/A
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STRAPPING
None.
ADJUSTMENTS
None.
TEST EQUIPMENT
DIAGNOSTIC TEST CARDS
You need the following test cards to perform level 1 diagnostic testing on the SCRW:
z AFNOR/CP8 test card - NCR part number 009-0009493 z ISO test card - NCR part number 009-0009494 z Cleaning card - NCR part number 998-0052929.
PREVENTIVE MAINTENANCE
The only preventive maintenance necessary for the SCRW is to clean the feed roller. This should be done using the diagnostic clean facility and cleaning card for the associated MCRW in this manual, that is Chapter 7.2, 7.3 and 7.7.
INTERCONNECTIONS
The interconnections between the SCRW, the MCRW and the SCIF are shown in the following figures.
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SOLENOIDS AND PHOTODETECTOR CONNECTIONS
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MOTOR AND SHUTTER CONNECTOR
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SDC MCRW TO SCIF PIA INTERFACE BOARD
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SCIF TO MCRW CONTROLLER PIA CONNECTOR
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POWER CONNECTIONS
SMART CARD SIGNALS AND POWER
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SCHEMATIC AND ASSEMBLY DIAGRAMS

The following pages contain the assembly drawings and schematic diagrams of the EMV SCIF board as follows:
z Page-46 Assembly 455-0650241 z Page-47 to -55 - Schematic Diagram for 455-0650243.
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445-0650241
EMV SCIF board Assembly Drawing
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EMV SCIF board Schematic Diagram (Sheet 1 of 9)
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Smart Card Reader

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Smart Card Reader

Încărcat de

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UPDATE NOTIFICATION

Document No.: Document Title:

Change No.: Print Date:

NCR- CONFIDENTIAL AND PROPRIETARY Use Pursuant to Company Instructions

13. Depository and Envelope Dispensers

SMART CARD READER/WRITER

Smart Card Reader/Writer

SMART CARD READER/WRITER

SMART CARD READER/WRITER

SMART CARD READER/WRITER

SMART CARD READER/WRITER

Smart Card Reader/Writer

SMART CARD READER/WRITER

The following figure shows the SCRW feature attached to an MCRW

SMART CARD READER/WRITER

Contact Solenoid Stopper Pin Solenoid Solenoid Sensors PCB

Flexible Printed Cables

Card Entry Mouth Contacts (8-pin or 16-pin version)

SMART CARD READER/WRITER

SMART CARD READER/WRITER

lowered on to the card

SMART CARD READER/WRITER

SMART CARD READER/WRITER

PRE-EMV SCIF BOARD

SCIF Core Electronics

z Power interface z Power fail interface z Test connectors.

SCIF CORE ELECTRONICS

SMART CARD READER/WRITER

9000H 8FFFH EPROM I/O 8000H 7FFFH NVRAM 7000H 6FFFH

2000H 1FFFH SRAM 0000H 0000H

SMART CARD READER/WRITER

SMART CARD READER/WRITER

PD7 PD_PD4 Buffer 2 Buffer 5

SMART CARD READER/WRITER

SCIF to host Host to SCIF MCRW to host Host to MCRW.

SMART CARD READER/WRITER

SMART CARD READER/WRITER

NOTE: A hardware reset is generated by toggling PB3, Register A.

A description of each bit follows:

SMART CARD READER/WRITER

A description of each signal follows:

SMART CARD READER/WRITER

SCIF DATA Bus

SCIF Control Bus

Data and Clock

Output to Smart Card

Resettable Latch Vpp

A brief description of each bit follows:

SMART CARD READER/WRITER

indicate signals to the smart card that are still active

SCIF Data Bus 8 Bits

SMART CARD READER/WRITER

The following figure shows the DAC circuit.

SMART CARD READER/WRITER

SMART CARD READER/WRITER

SMART CARD READER/WRITER

ERROR CODES AND DIAGNOSTICS

z ODH - Bad Switch Setting.

SMART CARD READER/WRITER

SMART CARD READER/WRITER

SMART CARD READER/WRITER

SMART CARD READER/WRITER

SMART CARD READER/WRITER