CHAPTER 2 OPERATIONAL AMPLIFIERS

Chapter Outline
2.1 The Ideal Op Amp
2.2 The Inverting Configuration
2.3 The Noninverting Configuration
2.4 Difference Amplifiers
2.5 Integrators and Differentiators
2.6 DC Imperfections
2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance
2 8 Large Signal Operation of Op Amp
NTUEE Electronics L. H. Lu 2-1
2.8 Large-Signal Operation of Op Amp
2.1 Ideal Op Amp
Introduction
Their applications were initially in the area of analog computation and instrumentation.
Op amp is very popular because of its versatility.
Op amp circuits work at levels that are quite close to their predicted theoretical performance.
We will first treat the op amp as a building block and study its terminal characteristics and its applications.
Op-amp symbol and terminals
Two input terminals: inverting input terminal () and noninverting input terminal (+)
One output terminal
Two dc power supplies V
+
and V

NTUEE Electronics L. H. Lu 2-2

Other terminals for frequency compensation and offset nulling
Circuit symbol for op amp Op amp with dc power supplies
Ideal characteristics of op amp
Differential-input single-ended-output amplifier
Infinite input impedance
i
1
= i
2
= 0 (regardless of the input voltage)
Zero output impedance
v
O
= A(v
2
v
1
) (regardless of the load)
Infinite open-loop differential gain
Infinite common-mode rejection
Infinite bandwidth
iff i i Differential and common-mode signals
Two independent input signals: v
1
and v
2
Differential-mode input signal (v
Id
): v
Id
= (v
2
v
1
)
Common-mode input signal (v
Icm
): v
Icm
= (v
1
+ v
2
)/2
Alternative expression of v
1
and v
2
:
v
1
= v
Icm
v
Id
/2
v
2
= v
Icm
+ v
Id
/2
NTUEE Electronics L. H. Lu 2-3
2.2 The Inverting Configuration
The inverting close-loop configuration
External components R
1
and R
2
form a close loop.
Output is fed back to the inverting input terminal.
Input signal is applied from the inverting terminal.
Inverting-configuration using ideal op amp
The required conditions to apply virtual short for op-amp circuit:
Negative feedback configuration
Infinite open-loop gain
Closed-loop gain: G v
O
/v
I
= R
2
/R
1
Infinite differential gain: v v = v /A = 0 Infinite differential gain: v
2
v
1
= v
O
/A = 0
Infinite input impedance: i
2
= i
1
= 0
Zero output impedance: v
O
= v
1
i
1
R
2
= v
I
R
2
/R
1
Voltage gain is negative
Input and output signals are out of phase.
Closed-loop gain depends entirely on external passive
components (independent of op-amp gain).
Close-loop amplifier trades gain (high open-loop gain)
for accuracy (finite but accurate closed-loop gain).
NTUEE Electronics L. H. Lu 2-4
Equivalent circuit model for the inverting configuration
Input impedance: R
i
v
I
/i
I
= v
I
/ (v
I
/R
1
) = R
1
For high input closed-loop impedance, R
1
should be large, but is limited to provide sufficient G.
In general, the inverting configuration suffers from a low input impedance.
Output impedance: R
o
= 0
Voltage gain: A
vo
= R
2
/R
1
Other circuit example for inverting configuration
NTUEE Electronics L. H. Lu 2-5
Application: the weighted summer
A weighted summer using the inverting configuration
A weighted summer for coefficients of both signs
) ... ( 0
2
2
1
1 1
n
n
f f f
n
k
k f O
v
R
R
v
R
R
v
R
R
i R v + + + = =

=
A weighted summer for coefficients of both signs
NTUEE Electronics L. H. Lu 2-6
|
|
.
|

\
|

|
|
.
|

\
|

|
|
.
|

\
|
|
|
.
|

\
|
+
|
|
.
|

\
|
|
|
.
|

\
|
=
4
4
3
3
2
2
1
1
R
Rc
v
R
R
v
R
R
R
R
v
R
R
R
R
v v
c
b
c a
b
c a
O
2.3 Noninverting Configuration
Application: the weighted summer
External components R
1
and R
2
form a close loop.
Output is fed back to the inverting input terminal.
Input signal is applied from the noninverting terminal.
Noninverting configuration using ideal op amp
The required conditions to apply virtual short for op-amp circuit:
Negative feedback configuration
Infinite open-loop gain
Closed-loop gain: G v
O
/v
I
= 1 + R
2
/R
1
Infinite differential gain: v v = v /A = 0 Infinite differential gain: v
+
v

= v
O
/A = 0
Infinite input impedance: i
2
= i
1
= v

/R
1
Zero output impedance: v
O
= v

+ i
1
R
2
= v
I
(1 + R
2
/R
1
)
Closed-loop gain depends entirely on external passive
components (independent of op-amp gain).
Close-loop amplifier trades gain (high open-loop gain)
for accuracy (finite but accurate closed-loop gain).
Equivalent circuit model for the noninverting configuration
Input impedance: R
i
=
Output impedance: R
o
= 0
Voltage gain: A
vo
= 1 + R
2
/R
1
NTUEE Electronics L. H. Lu 2-7
(1+R
2
/R
1
)v
i
The voltage follower
Unity-gain buffer based on noninverting configuration
Equivalent voltage amplifier model:
Input resistance of the voltage follower R
i
=
Output resistance of the voltage follower R
o
= 0
Voltage gain of the voltage follower A
vo
= 1
The closed-loop gain is unity regardless of source and load.
It is typically used as a buffer amplifier to connect a source with a high impedance to a low-impedance load.
NTUEE Electronics L. H. Lu 2-8
2.4 Difference Amplifiers
Difference amplifier
Ideal difference amplifier:
Responds to differential input signal v
Id
Rejects the common-mode input signal v
Icm
Practical difference amplifier:
v
O
= A
d
v
Id
+ A
cm
v
Icm
A
d
is the differential gain
A
cm
is the common-mode gain
Common-mode rejection ratio (CMRR):
| |
l 20
d
A
CMRR
Single op-amp difference amplifier
NTUEE Electronics L. H. Lu 2-9
| |
| |
log 20
cm
d
A
A
CMRR =
+
=
+
= v v
R R
R
v
I 2
4 3
4
2
4 3
1 2
1
1
2
2
1
1
2
/ 1
/ 1
I I O
v
R R
R R
v
R
R
R
R
v v
v iR v v
+
+
+ =
|
|
.
|

\
|
+ = + =


( ) ( ) 2 /
/ 1
/ 1
2 /
4 3
1 2
1
2
Id Icm Id Icm
v v
R R
R R
v v
R
R
+
+
+
+ =
|
|
.
|

\
|
+
+
+
=
1
2
4 3
1 2
/ 1
/ 1
2
1
R
R
R R
R R
A
d
|
|
.
|

\
|

+
+
=
1
2
4 3
1 2
/ 1
/ 1
R
R
R R
R R
A
cm
Id Icm
v
R
R
R R
R R
v
R
R
R R
R R
|
|
.
|

\
|
+
+
+
+
|
|
.
|

\
|

+
+
=
1
2
4 3
1 2
1
2
4 3
1 2
/ 1
/ 1
2
1
/ 1
/ 1
Superposition technique for linear time-invariant circuit
1 1 2 1
) / (
I O
v R R v =
2
4 3
4
1
2
2
1
I O
v
R R
R
R
R
v
|
|
.
|

\
|
+
|
|
.
|

\
|
+ =
2
4 3
1 2
1
1
2
2 1
/ 1
/ 1
I I O O O
v
R R
R R
v
R
R
v v v
+
+
+ = + =
Set v
I2
= 0
Set v
I1
= 0
Id Icm
v
R
R
R R
R R
v
R
R
R R
R R
|
|
.
|

\
|
+
+
+
+
|
|
.
|

\
|

+
+
=
1
2
4 3
1 2
1
2
4 3
1 2
/ 1
/ 1
2
1
/ 1
/ 1
)
`

|
|
.
|

\
|

+
+
|
|
.
|

\
|
+
+
+
=
1
2
4 3
1 2
1
2
4 3
1 2
/ 1
/ 1
/
/ 1
/ 1
2
1
log 20
R
R
R R
R R
R
R
R R
R R
CMRR
v
I1
v
O1
The condition for difference amplifier operation: R
2
/R
1
= R
4
/R
3
v
O
= (R
2
/R
1
)(v
2
v
1
)
For simplicity, the resistances can be chosen as: R
3
= R
1
and R
4
= R
2
.
Differential input resistance R
id
:
Differential input resistance: R
id
= 2R
1
Large R
1
can be used to increase R
id
R
2
becomes impractically large to maintain required gain.
Gain can be adjusted by changing R
1
and R
2
simultaneously.
NTUEE Electronics L. H. Lu 2-10
)
. \
+
. \
+
1 4 3 1 4 3
/ 1 / 1 2 R R R R R R
|
|
.
|

\
|
+
+
+
=
1
2
4 3
1 2
/ 1
/ 1
2
1
R
R
R R
R R
A
d
|
|
.
|

\
|

+
+
=
1
2
4 3
1 2
/ 1
/ 1
R
R
R R
R R
A
cm
v
I2
v
O2
Instrumentation amplifier
Differential-mode gain can be adjusted by tuning R
1
.
Common-mode gain is zero.
Input impedance is infinite.
Output impedance is zero.
Its preferable to obtain all the required gain in the first stage, leaving the second stage with a gain of one.
NTUEE Electronics L. H. Lu 2-11
) ( 1
1 2
1
2
3
4
I I O
v v
R
R
R
R
v
|
|
.
|

\
|
+ =
|
|
.
|

\
|
+ =

1
2
3
4
1 2
1
R
R
R
R
v v
v
A
I I
O
d
2.5 Integrators and Differentiators
Inverting configuration with general impedance
R
1
and R
2
in inverting configuration can be replaced by Z
1
(s) and Z
2
(s).
The closed-loop transfer function: V
o
(s) /V
i
(s) = Z
2
(s) /Z
1
(s)
The transmission magnitude and phase for a sinusoid input
can be evaluated by replacing s with je.
Inverting integrator
Time domain analysis:
} }
+ = + =
t
I
C
t
C C
dt
R
t v
C
V dt t i
C
V t v
0 0
1
) ( 1
) (
1
) (
t
V dt t t t
}
) (
1
) ( ) (
Frequency domain analysis:
Also known as Miller integrator.
Integrator frequency (e
int
) is the inverse of the integrator time-constant (RC) e
int
= 1/RC
The capacitor behaves as an open-circuit at dc (e = 0) open-loop configuration at dc (infinite gain).
Any tiny dc in the input could result in output saturation.
NTUEE Electronics L. H. Lu 2-12
C I C O
V dt t v
RC
t v t v = =
}
0
) ( ) ( ) (
RC j Z
Z
j V
j V
i
o
e e
e 1
) (
) (
1
2
= =
RC V
V
i
o
e
1
=
| = 90
The miller integrator with parallel feedback resistance
In order to prevent integrator saturation due to infinite dc gain, parallel feedback resistance is included.
e (log scale)
G (dB)
RC
1
C R
F
1
Closed-loop gain = 1/(jeR
F
+ R/R
F
)
Closed-loop gain at dc = R
F
/R
Closed-loop gain at high frequency (e >>1/R
F
C) 1/ jeRC
Corner frequency (3dB frequency) = 1/R
F
C
The integrator characteristics is no longer ideal.
Large resistance R
F
should be used for the feedback.
NTUEE Electronics L. H. Lu 2-13
RC j R R j Z
j Z
j V
j V
F i
o
e e
e
e
e
+
== =
/
1
) (
) (
) (
) (
1
2
The op-amp differentiator
Time domain analysis
Frequency domain analysis
dt
t dv
C i
I
) (
=
dt
t dv
RC t v
I
O
) (
) ( =
RC j
Z
Z
j V
j V
i
o
e
e
e
= =
1
2
) (
) (
RC
V
V
i
o
e =
| = 90
Differentiator operation:
Differentiator time-constant: RC
Gain (= eRC) becomes infinite at very high frequencies.
High-frequency noise is magnified (generally avoided in practice).
NTUEE Electronics L. H. Lu 2-14
i
The differentiator with series resistance
To prevent magnifying high-frequency noise, series resistance R
F
is included.
e (log scale)
G (dB)
C R
F
1
RC
1
RC j j V
o
e e
=
) (
Closed-loop gain = jeRC / (1 + jeR
F
C)
Closed-loop gain at infinite frequency = R/R
F
Closed-loop gain at low frequency (e << 1/R
F
C ) jeRC
Corner frequency (3dB frequency) = 1/R
F
C
The differentiator characteristics is no longer ideal.
NTUEE Electronics L. H. Lu 2-15
C R j j V
F i
e e +
=
1 ) (
2.6 DC Imperfections
Offset voltage
Input offset voltage (V
OS
) arises as a result of the unavoidable mismatches.
The offset voltage and its polarity vary from one op-amp to another.
The analysis can be simplified by using the circuit model with an offset-free
op amp and a voltage source V
OS
at input terminal.
Typical offset voltage is a few mV.
Effect of offset voltage for a closed-loop amplifier
A dc voltage V
OS
(1+R
2
/R
1
) exists at the output at zero input voltage.
The input offset voltage is effectively amplified by the closed-loop gain as the error voltage at output.
Some op amps are provided with two additional terminals for offset nulling.
NTUEE Electronics L. H. Lu 2-16
) / 1 (
1 2
R R V V
OS O
+ =
Input bias and offset current
DC bias currents I
B1
and I
B2
are required for certain types of op amps.
Input bias current is defined by I
B
= (I
B1
+I
B2
)/2
Input offset current is defined as I
OS
= |I
B1
I
B2
|.
Typical values for general-purpose op amps that use bipolar transistors are I
B
= 100 nA and I
OS
= 10 nA.
Effect of input bias current for a closed-loop amplifiers
Output dc voltage due to input bias current: V
O
= I
B1
R
2
~ I
B
R
2
The value of R
2
and the closed-loop gain are limited.
NTUEE Electronics L. H. Lu 2-17
Effect of input offset voltage on the the inverting integrator
The output voltage is given by
The output voltage increases with time until the op amp saturates.
Effect of input bias current on the inverting integrator
The output voltage is given by
The output voltage also increases with time unitl the op amp saturates.
t
RC
V
V t d
R
V
C
V v
OS
OS
t
OS
OS O
+ = + =
}
0
1
t
C
I
R I t d I
C
R I v
OS
B
t
OS B O
+ = + =
}
2
0
2
1
NTUEE Electronics L. H. Lu 2-18
2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance
Practical op-amp characteristics
Op amp with finite open-loop gain: A(je) = A
0
Op amp with finite open-loop gain and bandwidth: A(je) = A
0
/ (1 + je /e
b
)
Frequency response of op amp:
Open-loop op-amp
The frequency response of an open-loop op amp is approximated by STC form: A(je) = A
0
/(1+ je/e
b
).
At low frequencies (e << e
b
), the open-loop op amp is approximated by |A(je)| A
0
At high frequencies (e >> e
b
), the open-loop op amp is approximated by |A(je)| eA
0
/e
b
Unity-gain bandwidth (f
t
= e
t
/2t) is defined as the frequency at which |A(je
t
)| 1 e
t
= A
0
e
b
NTUEE Electronics L. H. Lu 2-19
Inverting configuration using op-amp with finite open-loop gain
Closed-loop gain:
Closed-loop gain approaches the ideal value of R
2
/R
1
as A
0
approaches to infinite.
To minimize the dependence of G on open-loop gain, we should have A
0
>> 1+ R
2
/R
1
I t i d
1
0
1
0
1
/ ) / (
R
A v v
R
A v v
i
O I O I
+
=

=
2
1
0
0
2 1
0
/
R
R
A v v
A
v
R i
A
v
v
O I O O
O
|
|
.
|

\
| +
= =
0 1 2
1 2
/ ) / 1 ( 1
/
A R R
R R
v
v
G
I
O
+ +

=
1
R v v v
I I I
Input impedance:
Output impedance:
Inverting configuration using op amp with finite gain and bandwidth
NTUEE Electronics L. H. Lu 2-20
0
1
1 0 1 0 1
/ 1 / ) / ( / ) / ( A G
R
R A G v v
v
R A v v
v
i
v
R
I I
I
O I
I I
i
+
=
+
=
+
= =
0 =
o
R
| | ) / 1 /( / ) / 1 ( 1
/
) ( / ) / 1 ( 1
/
0 1 2
1 2
1 2
1 2
b
j A R R
R R
j A R R
R R
G
e e e + + +

=
+ +

=
| | | |
0 1 2 0 1 2
1 2
/ ) / 1 ( / ) / 1 ( 1
/
A R R j A R R
R R
b
e e + + + +

=
if A
0
>> 1+R
2
/R
1
G G
0
/(1+je /e
3dB
)
where G
0
= R
2
/R
1
and e
3dB
= A
0
e
b
/(1+R
2
/R
1
) (A
0
/|G
0
|)e
b
2.8 Large-Signal Operation of Op Amps
Output voltage saturation
Rated output voltage (v
O,max
) specifies the maximum output voltage swing of op amp
Linear amplifier operation (for the required v
O
< v
O,max
): v
O
= (1+R
2
/R
1
)v
I
Clipped output waveform (for the required v
O
> v
O,max
): v
O
= v
O,max
The maximum input swing allowed for output voltage limited case: v
I,max
= v
O,max
/ (1+R
2
/R
1
)
Output is typically limited by voltage in cases where R
L
is large
Output current limits
Maximum output current (i
O,max
) specifies the output current limitation of op amp
Linear amplifier operation (for the required i
O
< i
O,max
): v
O
= (1+R
2
/R
1
)v
I
and i
L
= v
O
/R
L
Clipped output waveform(for the required i > i ): i = i i Clipped output waveform (for the required i
O
> i
O,max
): i
L
= i
O,max
i
F
The maximum input swing allowed for output current limited case: v
I,max
= i
O,max
[R
L
||(R
1
+R
2
)]/(1+R
2
/R
1
)
Output is typically limited by current in cases where R
L
is small
NTUEE Electronics L. H. Lu 2-21
Slew rate
Slew rate is the maximum rate of change possible at the output: (V/sec)
Slew rate may cause non-linear distortion for large-signal operation.
max
dt
dv
SR
O
=
) 1 ( ) (
t
O
t
e V t v
e
=
Input step function Small-signal distortion (finite BW) Large-signal distortion (SR)
Full-power bandwidth
Defined as the highest frequency allowed for a unity-gain buffer with a sinusoidal output at v
O,max
NTUEE Electronics L. H. Lu 2-22
e
v
O
v
O,max
e
M
SR
max ,
max
max
2 2
distortion |
) (
|
less distortion |
) (
|
cos
) (
sin ) ( sin ) (
O
M
M
o
o
o
o
o
o
o o o i
v
SR
f
SR V
dt
t dv
SR V
dt
t dv
t V
dt
t dv
t V t v t V t v
t t
e
e
e
e e
e e
= =
> =
< =
=
= =