Proceedings of 2007 International Symposium on Intelligent Signal Processing and Communication Systems Nov.28-Dec.

1, 2007 Xiamen, China

DESIGN AND ANALYSIS OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED

LOOP

Yawgeng A. Chau, Chen-Feng Chen and Kwn-Dai Tsai

Department of Communication Engineering

Yuan Ze University, Taiwan 320
eeyaw@saturn.yzu.edu.tw

ABSTRACT filters are adaptively adjusted according to the input

To obtain better locking performance and wider locking
range, the adaptive-bandwidth all-digital phase-locked loop
(AB-ADPLL) is proposed and designed in the paper. With
the AB-ADPLL, the parameters of the digital loop filter can
be adaptively adjusted using a parameter estimator in
accordance with the input frequency. From the design
example given in the context and corresponding simulation
results, it is disclosed that the AB-ADPLL outperforms the
non-adaptive ADPLL.
frequency.
In Section II, the analog adaptive-bandwidth PLL is
reviewed, and the design criterion of the AB-ADPLL is
derived. In Section III, the adaptive algorithm with
parameter estimation is developed, and a CMOS design
example is illustrated. In Section IV, the simulation and
analysis results for the AB-ADPLL are given, and the
locking performance of the AB-ADPLL is compared to that
of the non-adaptive ADPLL. The conclusions are drawn in
Section V.

Index Terms— All-Digital Phase-Locked Loop II. DESIGN OF THE AB-ADPLL

I. INTRODUCTION The general PLL can be characterized by Fig. 1 that consists

of the three main components: the phase detector, the loop
The phase-locked loop (PLL) has various applications in filter, and the voltage-controlled oscillator (VCO). The
frequency synthesis, digital modulation, synchronization, etc. closed-loop transfer function of a second-order analog PLL
The traditional fixed-bandwidth PLL employs fixed loop is given by [4]
parameters, and its bandwidth is constrained to be a decade φ (s) 2ξωn s + ωn2
H APLL ( s ) = out = 2 (1)
below the lowest desired operating frequency to obtain a φref ( s ) s + 2ξωn s + ωn2
stable output [1]. Thus, the fixed-bandwidth PLL will result
in suboptimal performance in the upper frequency range. where ωn is the natural frequency, and is the damping factor.
On the other hand, the adaptive-bandwidth PLL scales
its operating bandwidth to the input frequency to yield an
optimal locking performance. The analog adaptive-
bandwidth PLL and its design methodology has been
proposed in [1], where a constant ratio between the loop
bandwidth and input reference frequency is maintained, and
the damping factor is also kept as a constant regardless the
variation of process, temperature, and voltage. The
implementation of the analog adaptive-bandwidth PLL was Fig. 1 The general concept of a PLL.
addressed in [2] and [3]. However, in the design of analog
adaptive-bandwidth PLL, the leakage of MOS capacitors Let K P = 2ξωn and K I = ωn2 be the proportional and
and the sub-threshold leakage of MOS switches pose
integral gains [1]. Then, (1) can be written as
potential problems to the charge pump of the analog PLL
K p s + KI
and its realization [1], which is difficult to control in the H APLL ( s ) = 2 (2)
practical MOS process. s + K p s + KI
In the paper, based on the discrete form of the analog that represents the closed-loop transfer function of the PLL
adaptive-bandwidth PLL [1], the second-order AB-ADPLL given by Fig. 2.
is proposed and designed, where the design criterion is
derived. In the AB-ADPLL system, the parameters of loop

1-4244-1447-4/07/$25.00 ©2007 IEEE 804

 Proceedings of 2007 International Symposium on Intelligent Signal Processing and Communication Systems Nov.28-Dec.1, 2007 Xiamen, China

Denote the input reference frequency by ωref . To ωn2

K 2 = ωn2Ts = 4π 2 (8)
achieve the adaptive-bandwidth PLL, the following ωs2
identities
ωn
= constant (3) φref [ n ] φerr [ n ] z −1
ωref K1
1 − z −1
and φout [ n ]
ς = constant (4)
1
K2
must be maintained [1]. 1 − z −1
If the continuous-time PLL given in Fig. 2 is
transformed into the corresponding discrete one with the z-
transform, we will obtain the discrete-time PLL with the
sampling frequency 1/ Ts = ωs . The transfer function of the Fig. 3 The block diagram of a discrete-time PLL.
digital controlled oscillator (DCO) in the discrete-time PLL
has the form Recall that the damping factor ς in (7) is a constant
T z −1 given by (4). Then, using (3) and letting ωn / ωref = C , we
H DCO ( z ) = s −1 . (5)
1− z can rewrite (7) as
ωP ωref
φref ( s ) φerr ( s ) 1 K1 = 4πς C = 2ς K 2 (9)
KP
s ωs
φout ( s ) that depends on ωref , and K 2 in (8) can be expressed as
KI ωI
ωref
2
⎛K ⎞
2
s
K 2 = 4π 2 C 2
=⎜ 1 ⎟ (10)
ωs ⎝ 2ς ⎠
2

that is a function of K1 and also depends on ωref .

Fig. 2 The block diagram of a continuous-time PLL. Consequently, the design criterion of the AB-ADPLL is
characterized by (9) and (10) with a constant C , and the two
In Fig. 2, the transfer function of integration K I / s is parameters ( K1 , K 2 ) will be adaptively adjusted according to
replaced by the equivalent discrete integration Ts /(1 − z −1 ), ωref .
and the VCO is replaced by the DCO given by (5). Thus, the
closed-loop transfer function of the discrete-time PLL given III. PARAMETER ESTIMATION FOR ADAPTIVE
by Fig. 3 is [5] LOOP FILTERS

H DPLL ( z ) = 2
(
K pTs + K I Ts2 z − K pTs ) To achieve an AD-ADPLL, an adaptive loop filter is
(
z + K pTs + K I Ts2 − 2 z + 1 − K pTs ) designed. From (10), since K 2 can be obtained from K1 , we

=
( K1 + K 2 ) z − K1 (6)
only need to estimate K1 for the adaptive loop filter.
z 2
+ ( K1 + K 2 − 2 ) z + 1 − K1 In (9). the sampling frequency ωs is fixed, and
where K1  K pTs , and K 2  K T . According to the transfer 2 thus K1 can be estimated with the estimation of ωref .
I s

function given by (6), we obtain an equivalent block However, for locking a specific ωref , since the input signal
diagram of the discrete-time PLL (see Fig. 3) that can be into the loop filter at the n-th locking cycle is the phase error
implemented as an ADPLL. For an AB-ADPLL, the signal φerr (n) = φref (n) − φout (n), ωref is estimated as
parameters ( K1 , K 2 ) should be able to adapt and adjust φref (n) − φref (n − 1)
themselves to different values of ωref . ωˆ ref (n) = 2π
Ts
From the definitions of ( K1 , K 2 ) and ( K P , K I ) , we = ωs [φref (n) − φerr (n − 1) − φout (n − 1)]
obtain the relations
= ωs [φerr (n) − φerr (n − 1)] + ωs [φout (n) − φout (n − 1)]
ω
K1 = 2ςωnTs = 4πς n (7) = ωs Δφerr (n) + ωs Δφout ( n) (11)
ωs
where
and
Δφerr ( n)  φerr (n) − φerr (n − 1) ≠ 0 (12)

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 Proceedings of 2007 International Symposium on Intelligent Signal Processing and Communication Systems Nov.28-Dec.1, 2007 Xiamen, China

and Δφout (n)  φout (n) − φout (n − 1). where Bref is the bandwidth of input reference signal. For a
Therefore, for Δφerr ( n) ≠ 0, the estimates of ( K1 , K 2 ) large locking cycle n, if the high-order terms of phase errors
are in (19) are neglected, the bandwidth of the loop filter can be
evaluated by
Kˆ 1 (n) = 4πς C[Δφerr (n − 1) + Δφout (n − 1)] (13)
π C (4ς 2 + 1)[Δφerr (n) + Δφout ]
and Bl ≅ ⋅ Bref
4ς 1 − [Δφerr (n) + Δφout ]
Kˆ 2 (n) = 4π 2 C 2 [Δφerr (n − 1) + Δφout (n − 1)]2 . (14)
πC 2
When Δφerr (n) = 0 and thus φerr (n) = φerr (n − 1) , which ≅ (ς + 0.25)[Δφerr (n) + Δφout ]Bref (20)
ς
means that ( K1 , K 2 ) are already suitably selected, the
for Δφerr ( n) ≠ 0, where it is assumed that
estimates should be maintained as Kˆ j (n) = Kˆ j (n − 1) for
Δφerr (n) + Δφout  1 for a large n. When Δφerr ( n) finally
j = 1, 2. In the implementation of parameter estimation in
approaches zero, the value of Bl will stay at the previous
this context, K̂1 is first obtained, and then is used to yield cycle and is a function of Δφerr (n − 1) + Δφout (n − 1) that is a
K̂ 2 and ωˆ ref . narrow bandwidth to pass the desired signal only.
The AB-ADPLL with the estimation procedure of
( K1 , K 2 ) is illustrated in Fig. 4, where the block of K- IV. IMPLEMENTATION AND RESULTS
estimator executes the functions characterized by (13) and
In Fig. 4, the estimates of ( K1 , K 2 ) are multiplied by the
(14).
In the implementation and estimation of ( K1 , K 2 ), there phase error φerr ( n) , and results in
will be estimation errors from quantization, round-off, and φ (n) Kˆ (n) = 4πς Cφ (n)[Δφ (n − 1) + Δφ ( n − 1)] (21)
err 1 err err out
the delay in circuit realization, which can be characterized and
by 2
⎛ Kˆ 1 (n) ⎞
K j (n) = Kˆ j (n) + δ Kˆ j (n) φerr (n) Kˆ 2 (n) = φerr (n) ⎜
⎜ 2ς ⎟⎟
(15)
at the n-th locking cycle for j = 1, 2, where ⎝ ⎠
= 4π C φerr (n)[Δφerr (n − 1) + Δφout (n − 1)]2
2 2
δ Kˆ 1 (n) = 4πς C[δΔφerr (n − 1) + δΔφout (n − 1)] (16)
(22)
and
that can be implemented by a lookup-table (LUT) to achieve
δ Kˆ 2 ( n) fast processing for the parameter estimation of the adaptive
= 8π 2 C 2 [Δφerr (n − 1) + Δφout (n − 1)][δΔφerr (n − 1) + δΔφout ( n − 1)]. loop filter
(17)
The impact of the estimation error of K̂ 2 and Δφerr (n) on K-Estimator

ωˆ ref is characterized by
φref [n] φerr [n ] −
z1
δωˆ ref (n) = ωsδΔφerr (n) + ωsδΔφout (n) K1 −
1− z 1
φout [n]
= ωs [δφerr ( n) − δφerr (n − 1)] + ωs [δφout (n) − δφout (n − 1)].
(18) K2
1
−
From the relation given by (18), it is noticed that 1− z 1

estimation error δωˆ ref can be neglected if the estimation

errors δφerr and the output error δφout (n) have similar values Fig. 4 The block diagram of a discrete-time PLL with the
estimates of ( K1 , K 2 ) .
for consecutive locking cycles n and n-1 .
With the estimates of ( K1 , K 2 ) for Δφerr ( n) ≠ 0, the In Fig. 5 and Fig. 6, we compare the simulation results
bandwidth of the adaptive loop filter is given by [5] of using the traditional ADPLL and the AB-ADPLL, where
2 Kˆ 12 + Kˆ 1 Kˆ 2 + 2 Kˆ 2 input signal is 20MHz that is switched to 62MHz first, and
Bl = Bref then to 31MHz. Notice that the AB-ADPLL locks well,
2(4 Kˆ − 2 Kˆ 2 − Kˆ Kˆ )
1 1 1 2
while the traditional ADPLL cannot lock into the desired
π C (4ς + 1)[Δφerr + Δφout ] + 2ςπ C[Δφerr + Δφout ]2
2
frequency after switching as shown at UnLock_A and
= ⋅ Bref
4ς 1 − 2ςπ C[Δφerr + Δφout ] − π 2 C 2 [Δφerr + Δφout ]2 UnLock_B.
(19)

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 Proceedings of 2007 International Symposium on Intelligent Signal Processing and Communication Systems Nov.28-Dec.1, 2007 Xiamen, China
Fig. 5 Simulation results of the traditional ADPLL.
The chip layout of the designed AB-ADPLL is
illustrated in Fig. 7, where the UMC 0.18um 1P6M process
is employed for the realization. In Table 1, the measured
performance of the realized chip is presented and compared
to the design specification, where the measured specification
is very close to the design goal.
Fig. 6 Simulation results of the traditional AB-ADPLL.
Fig. 7 Chip layout
Fig. 8 gives the input signal for testing with the
reference phase varying from 13 MHz to 62 MHz.
Fig. 8 Testing waveform
807
Table 1 Summary of chip performance
V. CONCLUSIONS
In the paper, the adaptive-bandwidth PLL is implemented
with an all-digital design and the corresponding design
criterion is derived. By using the design criterion, the
parameter of the loop filter can be adaptively adjusted in
accordance with the input frequency and phase. The AB-
ADPLL can be realized with a CMOS process. From the
results of function and timing simulation, the AB-ADPLL
can be used to synthesize 120 MHz output frequencies.
Higher output frequencies will be obtained with pipelined
and parallel structures, which is under investigation.
V. REFERENCES
[1] J. Kim, M.A. Horowitz, and G. Wei, “Design of CMOS
adaptive-bandwidth PLL/DLLs: A general approach,” IEEE Trans.
CIircuits and Systems—II: Analogand Digital Signal Processing,
Vol. 50, pp. 860-869, Nov. 2003.
[2] S. Sidiropoulos, D. Liu, J. Kim, G. Wei, and M. Horowitz,
“Adaptive bandwidth DLLs and PLLs using regulated supply
CMOS buffers,” IEEE Symp. VLSI Circuits Dig. Tech. Papers,
June 2000, pp. 124–127.
[3] J. G. Maneatis, “Low-jitter process-independent DLL and PLL
based on self-biased techniques,” IEEE J. Solid-State Circuits, vol.
31, pp. 1723–1732, Nov. 1996.
[4] R. E. Best, Phase-Locked Loops, 5th ed, McGraw-Hill, 2003.
[5] K.D. Tsai, “Design, Implementation and Analysis of All Digital
Adaptive-Bandwidth PLL,” Master Thesis, Yuan-Ze University,
June 2006.