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Stefano Olivieri Senior Application Engineer MathWorks Daniele Bagni DSP Specialist EMEA Xilinx
Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45
Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up
9/21/2011
MathWorks: accelerate the pace of engineering and science by providing best in class Software for:
De elopment and verification of algorithms and control logic Development erification Embedded Systems implementation
Xilinx: providing best in class Silicon including FPGAs and embedded system hardware platforms :
Offers FPGAs and Zynq an Extensible Processing Platform P t Partner with MathWorks to provide an integrated workflow ith M thW k t id i t t d kfl
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MathWorks at a Glance
Headquarters: Natick, Massachusetts US N ti k M h tt Other US Locations: California, Michigan, Texas, Washington DC Europe: France, Germany, Italy, Spain, the Netherlands, Sweden, Switzerland, UK Asia-Pacific: Australia, China, India, Japan, Korea Worldwide training and consulting Distributors in 25 countries
5 Earths topography on an equidistant cylindrical projection, created with MATLAB and Mapping Toolbox.
MathWorks Today
Revenues ~$600M in 2010 Privately held More than 2000 employees worldwide Worldwide revenue balance: 45% North America, 55% international More than 1 million users in 175+ countries
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Key Industries
Aerospace and Defense Automotive Biotech and Pharmaceutical Communications Education Electronics and Semiconductors Energy Production Financial Services Industrial Automation and Machinery
Who is Who???
Who is a System Engineer? Who is Wh i an FPGA designers ? d i Who is using MATLAB? Who is using Simulink?
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Things to remember .
DESIGN
Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time
Algorithm Development
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Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45
Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up
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Customized interfaces to peripherals High-speed communication interfaces to other processors Finite state machines, digital logic, timing and memory control High speed, highly parallel DSP Algorithms or Control Algorithms
Analog I/O Memory Memory Memory
Bridge
FPGA
Digital I/O
ARM
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Algorithm Design
Fixed-Point Timing / Control Logic Architecture Exploration Algorithms / IP
RTL Design
IP Interfaces HW Architecture
Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation
Back Annotation
FPGA Hardware
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FPGA Requirements
Hardware Specification Test Stimulus
Simulating designs? Creating designs and test benches? Analyzing and combining results from multiple tools? Exploring implementation ideas and architectures? Floating point to fixed-point? Writing HW specifications? Iterating over designs with the FPGA designer? Blaming the FPGA designer?
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Simulating designs and validating against HW specs? Creating designs and writing test benches? Hardware architecture design? Writing interfaces to existing IP? Synthesis, Map, PAR cycles? Iterating over designs with the system designer? Blaming the system designer?
FPGA Designer
RTL Design
IP Interfaces Hardware Architecture
Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation
Implement Design
Back Annotation
FPGA Hardware
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3.
4.
Increase simulation speed Simplify design entry, system test harness creation, and exploration Shorter iteration cycles required for RTL design & verification Integrate the separate workflows to facilitate collaboration, re-use, and prototyping
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RTL Design
IP Interfaces Hardware Architecture
Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation
Back Annotation
FPGA Hardware
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RTL Design
IP Interfaces
Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation
Hardware Architecture
Implement Design
Synthesis Map Place & Route
Back Annotation
FPGA Hardware
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Verification
Behavioral Simulation
Functional Simulation
Behavioral Simulation
Implement Design
Synthesis Map Place & Route
Back Annotation
FPGA Hardware
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Verification
Functional Simulation
Behavioral Simulation
Implement Design
Back Annotation Synthesis Map
Back Annotation
Implement Design
Synthesis Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
FPGA Hardware
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Behavioral Simulation
Back Annotation
Implement Design
Synthesis Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
FPGA Hardware
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Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles Integrate FPGA development tools to reduce verification time 27
Behavioral Simulation
Back Annotation
Implement Design
Synthesis Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
AT4 wireless Increases Internal Test Coverage to Over 90% for LTE Physical Layer Test Equipment Designs
Ch ll Challenge
Develop test systems for LTE wireless equipment
AT4 wireless LTE layer 1 tester.
Solution
Use MATLAB and Simulink to design and simulate the LTE physical layer, verify the FPGA implementation, and analyze test results
MATLAB is a universal language that makes it easy to exchange algorithms and test results across our team. Our physical layer model in MATLAB and Simulink enabled us to better understand the LTE specifications, and Model-Based Design enabled us to verify that our FPGA implementation conformed to those specifications.
Francisco Javier Campos AT4 wireless
Link to user story
Results
Internal test coverage increased to over 90% Test harness reused throughout the project life cycle Development effort reduced by 2530%
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Challenge g
Accelerate the development of optimized digital receiver chains for wireless RF devices
The Semtech SX1231 wireless transceiver.
Solution
Use MathWorks tools for Model-Based Design to generate production VHDL code for rapid FPGA and ASIC implementation
Writing VHDL is tedious, and the handwritten code still needs to be verified. With Simulink and Simulink HDL Coder, once we have simulated the model we can generate VHDL directly and prototype an FPGA. It saves a lot of time, and the generated code contains some optimizations we hadnt thought of.
Frantz Prianon Semtech
Link to user story
Results
Prototypes created 50% faster Verification time reduced from weeks to days Optimized, better-performing design delivered
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Behavioral Simulation
Back Annotation
Implement Design
Synthesis Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
Choice of best modeling methods (Simulink, MATLAB and Stateflow) Integrate with MATLAB Algorithm Design
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Automatically generate bit true, cycle accurate HDL code from Simulink, MATLAB and Stateflow
Requirements
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Communications Blocks
Psuedo-random Sequence Generators, Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders
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MATLAB
Relevant subset of the MATLAB language for modeling and generating HDL implementations eml_hdl_design_patterns: Useful MATLAB Function Block Design Patterns for HDL
Stateflow
Graphical tool for modeling Mealy and Moore Finite State Machines
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Break
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Things to remember .
DESIGN
Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time
Algorithm Development
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What Wh t would you like to get ld lik t t from automatic code generation?
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Algorithm Development
Optimize HDL code Verify optimized HDL Place & Route Analyze result
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Behavioral Simulation
Back Annotation
Implement Design
Synthesis Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
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Critical Path highlighting: Visual representation of critical path in your model Easier to identify bottlenecks of your model
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parallel paths
critical path
Multiple parallel paths through your model High risk to have unmatched latencies
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Distributed Pipelining
Speed Optimization
Distributed pipelining (model retiming) Automatic balancing of pipeline registers (focus on critical path only) You are in full control of your pipelining strategy Bottom-up and top-down
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Distributed Pipelining
Speed Optimization
Minimum period: 23.796ns Maximum Frequency: 42.024MHz 42 024MHz
Section 1
Section 3
Section 2
Device,package,speed: xc5vsx50t,ff1136,-1
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Distributed Pipelining
Speed Optimization
Minimum period: 9.379ns Maximum Frequency: 106.62MHz 106 62MHz
Section 3
Device,package,speed: xc5vsx50t,ff1136,-1
Section 2
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MUX
SCHEDULING
X X
X X
DEMUX
X X
X X
X X X X
X X X X
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Easy to explore different sharing options Direct feedback through resource utilization report Prove correctness through validation models
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clk_enable clk
enb_1_2_1
clk_enable
Timing Controller
enb_1_2_0
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154 90 852 0 2
6 46 679 4 302
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Speed Optimization Area Optimization Make the right design choices to save power Analyze implementation results, resource utilization report Validation models to prove that implementation is correct
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Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45
Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up
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Things to remember .
DESIGN
Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time
Algorithm Development
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HDL Verification
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Verification Challenges:
HDL Verification
Many stimuli-files from MATLAB These are ideal references which require pre- and postprocessing How to analyze results?
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Verification Challenges:
HDL Verification
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DDC accepts p
A high sample-rate passband signal (may be 50 to 100 Msps)
DDC produces
A low sample-rate baseband signal ready for demodulation ~70 MSPS ~270 KSPS
Digital Down Converter
RF Section
A/D Conv
Demod
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Behavioral Simulation
Back Annotation
Implement Design
Synthesis Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
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Test Bench
HDL Simulator
Component
Replace a Broken or un-finished R l B k fi i h d block in a full HDL test bench with a working high level component Test alternate algorithms for system trade-off without developing HDL
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Ch ll Challenge
Streamline a time-consuming manual process for testing signal processing FPGA implementation
Harris FPGA-based system.
Solution
Use EDA Simulator Link to verify the HDL design from within MATLAB
EDA Simulator Link enabled us to greatly reduce functional verification development time by providing a direct cosimulation interface between our MATLAB model and our logic simulator. As a result, we verified our design earlier, identified problems faster, completed more tests, and compressed our entire development cycle.
Jason Plew Harris Corporation
Link to user story
Results
Functional verification time cut by more than 85% 100% of planned test cases completed Design implemented defect-free
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Challenges:
Testing algorithms on real hardware
Motivation: building confidence But interfaces with peripherals p p & rest of the system needed Difficult to construct testbenches in real hardware
FPGA-in-the-Loop verification
Digital Down Converter
Integration with FPGA development boards
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FPGA-in-the-Loop verification
Digital Down Converter
Re-use system level test bench for FPGA verification Flexible testbench creation in Simulink
Summary: Verification
Improved analysis, flexible testbench creation (multi domain, feedback loops) Integration with HDL verification Integration with FPGA verification
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Behavioral Simulation
Back Annotation
Implement Design
Synthesis Map Place & Route
Verification
Functional Simulation Static Timing Analysis Timing Simulation
Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45
Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up
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Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45
Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up
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Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45
Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up
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Things to remember .
DESIGN
Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time
Algorithm Development
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Shorter implementation time by 48% (total project 33%) Reduced FPGA prototype development schedule by 47% Shorter design iteration cycle by 80%
1st FPGA Prototype 2nd FPGA Prototype
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MathWorks tools provide a technology to speed up p gy p p development MathWorks services provide the support to roll out this technology in your organization
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MathWorks Training
Private training Simulink HDL Coder Public training Signal Processing with MATLAB/Simulink Signal MATLAB/Simulink Fundamental trainings for uniform knowledge, quick ramp up
MathWorks Consulting
Jumpstart service to get you up and running quickly with Simulink HDL Coder Advisory service for ongoing expert advice during technology adoption Based on industry experience, assistance with tailoring workflow On site expert customization / optimization of your workflow
Technical Support
Comprehensive, product-specific Web support resources 70% cases solved within 24 hours Included in Software Maintenance Service
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Please complete and return seminar survey forms Your comments and feedback are very important to us
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Next Steps
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Visit www.mathworks.com/fpga pg for more information Visit www.xilinx.com/dsp for more information
3.
Watch our FPGA webinars: www.mathworks.com/company/events/webinars th k / / t / bi Contact your local sales reps for a trial of our FPGA tools
4.
Questions?
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