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CS/JAN 2012/ITT430

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE COURSE CODE EXAMINATION TIME

MICROPROCESSOR ITT430 JANUARY 2012 3 HOURS

INSTRUCTIONS TO CANDIDATES 1. The question paper consists of three (3) parts: PART A (25 Questions) PART B (25 Questions) PART C (6 Questions)

Answer i) ii) iii)

ALL questions from all three (3) parts. Answer Part A in the Objective Answer Sheet Answer Part B in the True / False Answer Sheet Answer Part C in the Answer Booklet. Start each answer on a new page.

Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) the Question Paper ii) an Answer Booklet - provided by the Faculty iii) a True / False Answer Sheet - provided by the Faculty iv) an Objective Answer Sheet - provided by the Faculty

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 13 printed pages
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PART A (25 MARKS)

For each of the following questions, choose ONE (1) suitable answer and mark the answer on the Objective Answer Sheet provided.

1.

The size of the machine code for the assembly instruction "MOV CX, 12H" is A. B. C. D. 2 3 4 5 bytes bytes bytes bytes

2.

The contents of memory locations OAOOBie, OAOOOe, OAOODie, and OAOOEieare lie, 2ie, 3ie, and 4ie respectively. Determine the value of the word stored in memory starting at address 0A00BH and whether it is an aligned or misaligned word. A. B. C. D. 10203040ie and aligned word 10203040i6 and misaligned word 201 is and aligned word 20116 and misaligned word

3.

Instruction MOV [BX][DI]+2H, AH. The destination operand is accessed using A. B. C. D. register indirect addressing mode indexed addressing mode based addressing mode based-indexed addressing mode

4.

The following operation will require the stack A. B. C. D. JUMP CALL INT RET

5.

The instruction that when executed will mask off all but bit 4 and bit 1 of the base register is A. B. C. D. AND AND AND AND DX, 0080H BX, 0042H DX, 0082H BX, 0012H
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6.

If the ASCII representation for character " I " is 49H, the ASCII representation for character "i" is A. B. C. D. 19H 29H 59H 69H

7.

In a minimum-mode 8088 microcomputer, the output on S4S3 when a fetch to the stack segment is in progress will be A. B. 00 01

C.
D.

10
11

8.

The result after executing the following instructions in the MOV DX, 8123H MOV CX, 0103 ROL DX, CL

DEBUG

trace is

A. B. C. D.
9.

DX = DX = DX = DX =

091CH 91C0H 0C74H C740H

The following statements are TRUE EXCEPT I II III DMA capability permits devices such as peripherals to perform high speed data transfer between memories or memory and I/O devices. The memory or I/O bus cycles initiated as part of a DMA transfer are not performed by the MPU. DMA mode of operation is frequently used when blocks or packets of data are to be transferred. I and II I and III I, II and III None of the above

A. B. C. D.

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CS/JAN 2012/ITT430

If the value 0416 is written to the control register of an 82C55A set for mode 2, the port C affected by the operation is A. B. C. D. PC, = 1 PC 2 =0 PC 3 =1 PC 4 =0

11.

Assuming that (AX)=0123H and (BL)=02H, the remainder after executing the instruction " D I V B L " in the DEBUG trace is A. B. C. D. AH = 01H AL = 01H AH = 91H AL = 91H

12.

The following interrupt group is user defined EXCEPT A. B. C. D. Hardware Interrupts Software Interrupts Internal Interrupts Nonmaskable Interrupts

13.

The status flags will be shown after executing the following instructions in the trace is
MOV AL, 12H ADD AH, 27H CMP AL, - 2 H

DEBUG

A. B. C. D. 14.

NV UP El NV UP El NV UP El NV UP El

PL NZ NA PE NC PL NZ NA PE CY NG NZ NA PO CY PL NZ AC PE CY

The content of AH register to invoke the interrupt 21H so that it display data to the screen is A. B. C. D. (AH)=03H (AH)=05H (AH)=07H (AH)=09H

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15.

The following statements are true EXCEPT I II III A. B. Memory mapped I/O devices can reside anywhere in the 1 Mbyte memory address space of the 8088. During I/O operation in memory mapped I/O, memory read and write bus cycles are initiated instead of I/O bus cycles. Memory mapped I/O operation is generally faster than isolated I/O operation I II

C.
D.

Ill
I and III

16.

The duration of the bus cycle in the 8088-based microcomputer if the clock is 8 MHz and two wait states are inserted is

A. B. C. D.
17.

500 ns 625 ns 750 ns 875 ns

In a sixty-four-line parallel output circuit for an 8088-based microcomputer, if the address put on the bus during an output bus cycle is 800A16, the output port that the data will be written to is A. B. C. D. Port 0 Port 2 Port 4 None of the above

18.

The key differences between NMI and the other external hardware initiated interrupts are I II III A. B. C. D. NMI is masked out by IF NMI is initiated from the NMI input lead instead of from the INTR input. NMI input is edge-triggered instead of level sensitive. I and II I and III II and III I, II and III

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19.

If the bus status code SaSiSo equals 100, the bus activity that is taking place is A. B. C. D. read I/O port write I/O port halt instruction fetch

20.

The following statements are TRUE I. II. III. A. B. C. D. Signals IO/M and DT/R are set to 1 and 0 logic levels respectively at the start of T-,. Status bits S3 through S6 are output on the upper four address bus lines Ai 6 through A19 at the beginning of T2. Signal RD is switched to logic 1 at the later part of T2. I and II I and III II and III I, II, and III

21.

The value to be written to the control register of the 82C55A to configure the device such that port A and port B are configured as output ports and port C is set up as input port in mode 0 operation is A. B. C. D. 88H 89H C8H C9H

22.

This program is referred as a delay program. The "NOP" instruction is executed for
MOV CX, 2 0OH DEC CX NOP LOOP DLY

DLY:

NXT:

A. B. C. D.

128 255 256 512

times times times times

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23.

In a sixty-four-line parallel output circuit for an 8088-based microcomputer, if the address put on the bus during an output bus cycle is 800A16, the output port that the data will be written to will be A. B. C. D. Port 1 Port 3 Port 5 Port 7

24.

DEBUG

State the value of the flag register after executing the following instructions in the trace
MOV A X , SUB A X , ABCDH 1234H

A. B. C. D.

NV UP El NG NZ NA PE NC NV UP El PL NZ AC PO NC NV UP El NG NZ NA PO NC NV UP El PL NZ AC PE NC

25.

Determine the address of the vector specified by CS75:IP75. A. B. C. D. (CS) (CS) (CS) (CS) = 96H and (IP) = 98H = 75H and (IP) = 75H = 98H and (IP) = 96H = 12EHand(IP) = 12CH

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PART B (25 MARKS)

For each of the following questions, answer either TRUE or FALSE and mark your answer on the TRUE/FALSE Answer Sheet provided. 1. Assuming that (AX) = FFF2H, the new contents of AX after executing the instruction "IMUL AL" is 0144H. When the MPU recognizes the RESET input, it initiates its internal initialization routine and flags are all cleared. As a result of this process, the content of the DS register is initialized to 0000. Executing the instruction "JMP BX" will not affect the flag register. A USART has the ability to automatically check characters during data reception to detect automatically the occurrence of parity, framing, and overrun errors. When an erase operation is performed on a FLASH memory, either the complete memory array or a large block of storage locations is erased. In maximum mode, the 8088 has an external bus controller for interfacing to memory and I/O devices. The two separate internal processing units within the 8088/8086 microprocessor are Execution Unit (EU) and Bus Interface Unit (BIU). Microprocessors operate with a crystal-controlled clock signal that is responsible for the timing. Each phase of the instruction cycle requires a given number of clock cycles. Pointer and index registers can be accessed either as a whole 16 bits for word data operations or as two 8-bit registers for byte-wide data operations. The number of bus cycle required for writing a word at memory address 012AAie of an 8088-based microcomputer is two bus cycle. The control word to configure the 82C55A so that all ports are input ports arid are set up for mode 0 operation is 9AH. The VF flag register bit is set as a result of the last arithmetic operation being negative. In based addressing mode, the effective address is obtained from the contents of either BX or BP registers. In RCR (rotate right through carry), as the bits of the destination are shifted to the right into CF, the empty bits are filled with the sign bit.

2.

3. 4.

5.

6.

7.

8.

9.

10.

11. 12.

13.

14.

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15.

If (SP)=44FCH, the offset address of the first location of the stack that is available to push data into is 44FAH. If the inputs to a 74F138 decoder are Gi=1, G2A=0, G2B=0, and CBA=110forthe I/O address decoding, then the output P4 will be activated. In an 8086-base microcomputer, the logic level of A0 and BHE are 1 and 0 respectively, when a byte of data is being written to I/O address 20001H. The IP and CS registers have their contents changed during an intrasegment jump. The 8288 Bus Controller is used to provide control signals for the 8088/8086 when it is operating in minimum mode. Treating a peripheral device like a memory location is referred to as isolated memory mapping. The trap flag (TF) is reset so that the address is automatically incremented for the subroutine operation. The 82C37A has two priority schemes: fixed priority and rotating priority that can be selected under software control. The condition tested for JNE and JZ instructions is similar. The reserved memory which are saved for the storage of the pointers that are used for the 8088's user-defined interrupts are located at 00014 16 - 0008016. The maximum number of repeats that can be implemented with a loop instruction is 65535.

16.

17.

18. 19.

20.

21.

22.

23. 24.

25.

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PART C (50 MARKS) Answer ALL questions.

QUESTION 1 Encode (in hexadecimal) the following instructions using the information given in Table 1 and Table 2. Assume that the opcode for the SUB, MOV and LES operations are 001010, 100010 and 11000100 respectively.
a) MOV WORD PTR [BX] [DI] + 4815, 12CDH

(2 marks)
b) XCHG BX, [ S I ]

(2 marks)
C) ADD [BP] +85H , AX

(2 marks)

REG 000 001 010 011 100 101 110 111

W=1 AL AX CL CX DL DX BL DX AH SP CH BP DH SI BH DI Table 1: Register Field Encoding

w=o

MOD=l 1 R/M w=o 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH

EFFECTIVE ADDRESS CALCULATION W=l MOD=01 MOD=10 R/M MOD=00 (DX)+(SI)+D16 AX 000 (DX)+(SI)+D8 (DX)+(SI) CX 001 (DX)+(DI) (DX)+(DI)+D8 (DX)+(DI)+D16 DX 010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16 DX 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16 SP 100 (SI) (SI)+D8 (SI) +D16 BP 101 (DI) (DI)+D8 (DI)+D16 SI 110 Dir. address (BP)+D8 (BP)+D16 DI 111 (DX) (DX)+D8 (DX)+D16 Table 2: Register/Memory Encoding Field

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QUESTION 2 Describe the operation performed by the following stack related instructions. a) POP AX (2 marks) b) PUSH AX (2 marks) c) POPF (2 marks) d) PUSHF (2 marks)

QUESTION 3 a) Write an equivalent instruction sequence to replace the usage of string instruction for each of the following short program: i) CLD LODSB STOSB (4 marks) ii) MOV AX, DS MOV ES, AX STD CMPSW (4 marks) b) Name TWO(2) other string instructions of the 8088 instruction set beside found in a). (2 marks) Name the flag related to the instruction CLD and STD. (1 mark)

c)

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QUESTION 4 Assume that the contents of registers and memory are as follows (all in hex): AX = 0010 SI = 0100 IP = 010F
(DS: :100) (DS: :200) :201) (DS: :210) (DS: (DS: :211) (DS: :220) (DS: :221) (DS: :400) :401) (DS:

BX = 0220 CX = 0105 DX = 1234 DI = 0200 DS = 136A ES = 136A NV UP EI PL NZ NA PO NC

= = = = = = = = = 0AH 33H 55H 66H BBH BBH 66H BBH 66H

SP = FFEE BP = ABCD SS =136A CS =136A

Observe the following instructions and answer accordingly.

a) RCL BYTE PTR [DI]+10H, CL;

i)

Determine the physical address of the related memory location. (1 mark)

ii)

Determine the output stored in the specified memory location. (2 marks)

b)

MOV BX, MOV CL, STC SAR BX,

8A3BH 3 CL

i)

Determine the output of BX

(2 marks)
C) MOV AX, F0F0H CLC MOV CL, 5 RCR AX, CL i) Determine the output of the accumulator (2 marks)

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QUESTION 5 The 8088 and 8086 based microcomputer memory subsystems are implemented differently. Therefore, the memory address spaces of the 8088 and 8086 based microcomputers are organized differently. a) Explain with respect to bus cycle, when a word of data is transferred to the storage location at 0ABC5H of the 8086 memory subsystem using diagram. (6 marks) Determine the number of bus cycle involved for the above transfer. (1 mark)

b)

QUESTION 6 a) Write a program that performs a 32-bit binary addition. The content of all the 32- bit binary inputs are pointed by the source index register. Once the addition is performed, the output of the 32-bit addition is stored at the memory location pointed by the destination index register. (8 marks) Write an instruction sequence that inputs the byte contents of input port 3 to the memory location PORT_3. The address of port 3 is given as 8006H. (3 marks)

b)

END OF QUESTION PAPER

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