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CS/APR2011/ITT430

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE COURSE CODE EXAMINATION TIME

MICROPROCESSOR ITT430 APRIL 2011 3 HOURS

INSTRUCTIONS TO CANDIDATES The question paper consists of three (3) parts: PART A (25 Questions) PART B (25 Questions) PART C (6 Questions)

2.

Answer ALL questions from all three (3) parts. i) Answer Part A in the Objective Answer Sheet ii) Answer Part B in the True / False Answer Sheet iii) Answer Part C in the Answer Booklet. Start each answer on a new page. Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) the Question Paper ii) an Answer Booklet - provided by the Faculty iii) a True / False Answer Sheet - provided by the Faculty iv) an Objective Answer Sheet - provided by the Faculty

3.

4.

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 12 printed pages
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CS/APR2011/ITT430

PART A (25 MARKS) For each of the following questions, choose ONE(1) suitable answer and mark the answer on the Objective Answer Sheet provided.

1.

The size of the machine code for the assembly instruction "ADD DX, [1234]" is A. B. C. D. 2 bytes 3 bytes 4 bytes 5 bytes

2.

A data segment is to be located from address A000016 to A9FF016. The content of DS register should be A. B. C. D. 000016 0A0016 A00016 AFFF16

3.

The contents of memory locations 1000716, 1000816, 1000916, and 1000A16 are 1916, 2616, 0416, and 4416 respectively. Determine the value of the double word stored in memory starting at address 10007H and whether it is an aligned or misaligned double word. A. B. C. D. 1926044416 1926044416 4404261916 4404261916 and aligned double word and misaligned double word and aligned double word and misaligned double word

4.

In the maximum-mode I/O interface of 8088 system, the logic levels of IORC, IOWC, and AIOWC during an output bus cycle are A. B. C. D. IORC= IORC= IORC= IORC= 1, IOWC=0, 1, IOWC=1, 0, IOWC=1, 0, IOWC=1, and and and and AIOWC=0 AIOWC=0 AIOWC=1 AIOWC=0

5.

The output signal used for signaling the external circuitry that a byte of data is available on the upper half of the 8086's data bus is A. B. C. D. M/IO IO/M DEN BHE

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CONFIDENTIAL 6.

CS/APR2011/ITT430

If the data CAEOH is to be coded as ASCII and stored in memory starting at address 01C00H, the data will be A. B. C. D. (01C00H)=43H, (01C01H)=41H, (01C02H)=45H, and (01C03H)=30H (01C00H)=30H, (01C01H)=45H, (01C02H)=41H, and (01C03H)=43H (01C00H)=CH, (01C01H)=AH, (01C02H)=EH, and (01C03H)=0H (01C00H)=0H, (01C01H)=EH, (01C02H)=AH, and (01C03H)=CH

7.

In a minimum-mode 8088 microcomputer, the output on S4S3 when an instructionfetch bus cycle is in progress will be A. 00

B.
C. D. 8.

01
10 11

The result after executing the following instructions in the DEBUG trace is
MOV BX, C74EH MOV CX, 0 1 0 4 SHR BX, CL

A. B. C. D. 9.

BX= C74EH and NC BX= C74EH and CY BX= 0C74H and NC BX= 0C74H and CY

If the value 0416 is written to the control register of an 82C55A set for mode 2, which bit of port C is affected by the bit set/reset operation? Is it set to 1 or cleared to 0? A. B. C. D. PCi and logic 1 PC2 and logic 0 PC3 and logic 1 PC4 and logic 0
DEBUG

10.

The status flags will be shown after executing the following instructions in the trace is
MOV A L , - 1 5 H ADD A L , 27H CMP A L , - 2 H

A. B. C. D.

NV UP El NV UP El NV UP El NV UP El

PL NZ NA PE NC PL NZ NA PE CY PL NZ AC PE CY NG NZ NA PO CY

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CONFIDENTIAL 11.

CS/APR2011/ITT430

Assuming that (BX)=0200H, (DI)=0030H, (CS) = 1025H and (DS)=1035H, determine the physical memory location is swapped with AX when the instruction "XCHG [BX+DI], AX" is executed ?

A. B. C. D.
12.

10480H 10580H 1255H 1265H

Determine the duration of the bus cycle in the 8088-based microcomputer if the clock is 8 MHz and three wait states are inserted.

A. B. C. D.
13.

500 625 750 875

ns ns ns ns

The following statements are all true EXCEPT A. B. C. D. I/O data transfers in the 8088 and 8086 microcomputers can be either bytewide or word-wide. I/O data transfers in the 8088 and 8086 microcomputers can either take one or two bus cycle. In 8086 microcomputer, the aligned word transfer will takes two bus cycles. In 8088 microcomputer, the aligned word transfer will takes two bus cycles.

14.

If the bus status code S2S1S0 equals 100, the bus activity that is taking place is A. B. C. D. read I/O port write I/O port passive instruction fetch
"LOOP XYZ"

15.

The following groups of code that perform the same operation as

is

A. B. C. D.

DEC CL JNZ XYZ DEC CH JZ XYZ DEC CX JNZ XYZ DEC CX JZ XYZ

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CONFIDENTIAL 16.

CS/APR2011/ITT430

The following statements are all true EXCEPT A. B. C. D. The read bus cycle begins with state T^ In minimum-mode 8088, signals IO/M and DT/R are set to 0 logic levels at the start of T-i. Status bits S3 through S5 are output on the upper four address bus lines A16 through A19 at the beginning of T2. Signal RD is switched to logic 0 at the later part of T2.

17.

In a sixty-four-line parallel output circuit for an 8088-based microcomputer, if the address put on the bus during an output bus cycle is 800A16, the output port that the data will be written to will be A. B. C. D. Port Port Port Port 1 3 5 7

18.

The value of the control register 82C55A to configure the device such that both port A, B and C are configured for mode 1 output operation will be A. B. C. D. B6H A4H C8H BAH

19.

The content of AX after executing the following sequence of instructions is

MOV AX, FFF2 IMUL AL

A. B. C. D. 20.

(AX)=00C4H (AX)=0004H (AX)= FFC4H (AX)= FF04H

The interrupt service routine specified by CS1:IP1 is A. B. C. D. Divide Error. Breakpoint. NMI. Single Step.

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CONFIDENTIAL 21.

CS/APR2011/ITT430

The following statements are all true about the minimum-mode and maximum-mode of the 8088 system EXCEPT A. B. C. D. In the minimum-mode, the 8088 directly produce the control signals for the interfacing to memory and I/O devices. In the maximum-mode, the 8088 produce signals for supporting multiprocessing systems. In the maximum-mode, the 8088 control signals are encoded in the status lines and need to be decoded externally. The logic level of input MN/MX determines the mode. A logic 0 sets the 8088 system in minimum-mode and a logic 1 sets is in maximum-mode

22.

The term volatile memory means A. B. C. D. When the power supply for the memory device is turned off, its data contents are lost. When the power supply for the memory device is turned off, its data contents are not lost. Data contents of nonvolatile memory are electrically entered by users. Data contents of nonvolatile memory can be erased by exposing it to ultraviolet light.

23.

The concept of continually checking the I/O devices via program looping is known as A. B. C. D. device polling. device mapping device looping. poll mapping.

24.

When the MPU recognizes the RESET input, it initiates its internal initialization routine and flags are all cleared. As a result of this process, the content of the DS register is

A. B. C. D.
25.

0000H 00FFH FF00H FFFFH

The address of the vector 57, CS57 and IP57 stored in the interrupt vector table is A. B. C. D. CS=E6H and IP=E4H CS=BEH and IP=BCH CS=C6H and IP=C4H CS=BAH and IP=BCH

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CONFIDENTIAL PART B (25 MARKS)

CS/APR2011/ITT430

For each of the following questions, answer either TRUE or FALSE and mark your answer on the TRUE/FALSE Answer Sheet provided.

1.

The physical address for the bottom of the stack is defined by combining the SP value with the value 0000. In encoding the instructions of the 8088 microprocessor to a machine code, the third field of the second byte is used to identify the register operand. Assuming that (AX)=0089H and (BL)=02H, the new contents of AX after executing the instruction " D I V B L " is 0144H. The VF flag register bit is set as a result of the arithmetic operation being overflow. The instruction that is used to save parameters on the stack is the PUSHF instruction and that is used to retrieve them back is the POPF instruction. LOOPNZ instruction is an Instruction Pointer-relative that capable of maximum target label transfers of -256 to +255 bytes. In a maximum-mode 8088 microcomputer, code 10 is output on S4S3 when a datafetch bus cycle is in progress. Port B on PPI 0 is the parallel I/O port in memory-mapped 82C55A of the 8088-based microcomputer that will be selected for operation when the memory address output on the bus is 0040416 When 8086 reads a word from address 02440H, the logic levels of BHEL, MWRC, MRDC and A0|_ of the memory interface circuitry are 0, 0, 0 and 1 respectively. Each DMA channel has a base address register and a current address register for its address register. If (AL)=AFH, the new content of AX is 00AFH after executing the instruction
"CBW".

2.

3.

4. 5.

6.

7.

8.

9.

10.

11. 12.

Software interrupts are of higher priority than the external hardware interrupts and therefore are allowed to interrupt the external hardware interrupt when it is active. If the contents of registers DX and CX are ABCDH and OABCH respectively, the content of DX is 5EEFH after executing the instruction "SUB D X , CX". The 8086 microprocessor has two independent 256Kbyte memory banks and the 8088 microprocessor has a single 1Mbyte memory bank.

13.

14.

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15.

If (SP)=44FCH, the offset address of the first location of the stack that is available to push data into is 44FAH. The two benefits of writing programs in assembly language instead of a high-level language are it takes more memory and executes faster. The variety of static RAM ICs differs both in density and organization of the storage array. The memory address which stores the pointers for the 8088's internal interrupts and exceptions are located at 0000016- 0001316. F9H is the value of the control register of the 82C55A to configure the device such that port A is configured for bi-directional operation and port B is set up for mode 0 output operation. In a maximum mode system, the 8088 device is responsible to produce the input, output, and bus control signals for the I/O interface. The trap flag (TF) is reset so that the address is automatically incremented for the subroutine operation. The maximum number of repeats that can be implemented with a loop instruction is 255. The memory address of vector 43 is located at IP43=000AC16 and CS43=000AB16. The storage array in the bulk-erase device is a single block, whereas the memory array in both the boot block and FlashFile is organized as multiple independently erasable blocks. The name given to the part of the I/O address space from 000016 through 00FF16 is Page 1.

16.

17.

18.

19.

20.

21.

22.

23. 24.

25.

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CONFIDENTIAL PART C (50 MARKS) Answer ALL questions.

CS/APR2011/ITT430

QUESTION 1 Encode (in hexadecimal) the following instructions using the information given in Table 1 and Table 2. Assume that the opcode for the SUB, MOV and LES operations are 001010, 100010 and 11000100 respectively.
a) SUB [BX+DI + 5 9 ] , BX

(2 marks)
b) MOV [DI + 0 1 4 3 ] , DX

(2 marks)
C) LES D I , [1674]

(2 marks) REG 000 001 010 011 100 101 110 111

w=o
AL CL DL BL AH CH DH BH Table 1: Register

W=1 AX CX DX BX SP BP SI DI Field Encoding

MOD=l 1 R/M w=o 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH

EFFECTIVE ADDRESS CALCULATION W=l R/M MOD=00 MOD=01 MOD=10 AX (BX)+(SI)+D16 000 (BX)+(SI)+D8 (BX)+(SI) CX 001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16 DX 010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16 BX 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16 SP 100 (SI) (SI)+D8 (SI) +D16 BP 101 (DI) (DI)+D8 (DI)+D16 SI 110 Dir. address (BP)+D8 (BP)+D16 DI 111 (BX) (BX)+D8 (BX)+D16 Table 2: Register/Memory Encoding Field

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CONFIDENTIAL QUESTION 2 a)

10

CS/APR 2011/ITT430

Name the FIVE (5) groups of interrupts supported by the 8088/8086 microprocessor. (5 marks) Name the FOUR (4) interrupts dedicated to internal interrupt functions. (4 marks)

b)

c)

Determine the addresses of the above internal interrupts in the interrupt vector table. (4 marks)

QUESTION 3 The 888 microprocessor has dedicated instructions for handling string operations. The instructions permit operations such as to move a block of data to another location in the memory. a) Name FIVE (5) basic string instructions of the 8088 instruction set. (5 marks) b) Name the flag that is responsible for automatically incrementing or decrementing the address indices in SI and Dl. (1 mark) Determine the instruction used to set the above flag. (1 mark) d) Determine the selected mode when the above flag is set. (1 mark) e) Name the TWO (2) segments involved during the block transfer in the string operation. (2 marks)

c)

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CONFIDENTIAL QUESTION 4

11

CS/APR2011/ITT430

Assume that the contents of registers and memory are as follows (all in hex): AX = 0000 SI = 0100 IP = 010F
(DS (DS (DS (DS (DS (DS (DS (DS (DS 100) 200) 201) 210) 211) 220) 221) 400) 401)

BX = 0020 DI = 0200

CX = 0105 DS = 126A

DX = 3333 ES = 136A

SP = FFEE BP = 0000 SS =146A CS =116A

= = = = = = = = =

0AH 33H 55H 66H BBH BBH 66H BBH 66H

Determine the value of register or memory and its corresponding address after each of the following instruction is executed independently/separately.
a) ROL DX, CL;

(2 marks)
b) RCL BYTE PTR [0400H], CL;

(2 marks)
c) RCR WORD PTR [DI]+10H, CL;

(2 marks) QUESTION 5 The 82C55A is designed for easy implementation of parallel I/O in the 8088 microcomputer systems. The combination of bits of the control register determines the functions of the parallel I/O. a) The interrupt-control flag INTEA for the input port A in mode 1 is controlled by PC4. Determine the command code to be written to the control register of the 82C55A to set it to enable the control flag.

(2 marks) b) The interrupt-control flag INTEB for the input port B in mode 1 is controlled by PC2. Determine the command code to be written to the control register of the 82C55A to set it to enable the control flag.

(2 marks)
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CONFIDENTIAL QUESTION 6 a)

12

CS/APR2011/ITT430

Write a program that will modify the content of all the segment registers of the 8088 microprocessor. The new contents of the segment registers are stored at the starting address pointed by the base register. The order of the contents is based on your assumption. (8 marks) Write a program that will output AA16 to an output port located at address C00016 of the I/O address space. (3 marks)

b)

END OF QUESTION PAPER

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