Unit-4

TRANSISTOR AND ITS CHARACTERISTICS

Unit outline:
Junction transistor, Transistor current components, Transistor as an amplifier, Transistor construction, Detailed study of currents in a transistor, Transistor alpha, Input and Output characteristics of transistor in Common Base, Common Emitter, and Common collector configurations, Relation between Alpha and Beta, typical transistor junction voltage values, JFET characteristics (Qualitative and Quantitative discussion), Small signal model of JFET, MOSFET characteristics (Enhancement and depletion mode), Symbols of MOSFET, Comparison of Transistors, Introduction to SCR and UJT.

Hari Priya .M.N.

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4. TRANSISTOR and FET Characteristics

4.1 INTRODUCTION A Bipolar Junction Transistor (BJT) is a three terminal semiconductor device in which the operation depends on the interaction of both majority & minority carriers and hence, the name Bipolar. The BJT is analogous to a vacuum triode and is relatively small in size .It is used in amplifier & oscillator circuits and as switch in digital circuits. It has wide applications in computers,satellites and other modern communication systems. CONSTRUCTION OF BJT A BJT consists of a silicon (or germanium) crystal in which a thin layer of N-type silicon is sandwiched between two layers of P-type silicon. This transistor is referred to as PNP. Alternatively, in a NPN Transistor, a layer of P-type silicon is sandwiched between two layers of N-type material. The two types of BJT are represented as shown in fig:-

The symbolic representation of the two types of BJT is as shown in above fig. The three portions of the transistor are Emitter, Base, and Collector shown as E, B and C respectively. The arrow on the emitter specifies the direction of current flow, when the EB junction is forward biased. Emitter is heavily doped so that it can inject a large number of charge carriers into the base. Base is lightly doped and very thin. It passes most of the injected charge carriers from the emitter into the collector. Collector is moderately doped. Unbiased Transistor A transistor with its 3 terminals (i.e., E, B and C) left open is called as Unbiased Transistor (or) open circuited transistor. Under these conditions, the diffusion of free electrons across the junction produces two depletion layers as shown in fig.

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Fig. Unbiased Transistor It has been observed that an emitter-base depletion layer penetrates slightly into the emitter as it is heavily doped region, where as it penetrates deeply into the base, as it is a lightly doped region. Similarly, the collector-base depletion layer penetrates more into the base region and less into the collector region. The emitter-base depletion layer width is smaller than that of collector-base depletion layer. An Unbiased Transistor is never used in actual practice. Its terminals are always connected suitably by D.C. voltage sources for proper transistor action. Transistor biasing There are four possible combinations, the base-collector junction may be either forward or reverse biased, and the base-emitter junction can also be biased either way.The different modes of transistor biasing are:1. Forward -Active :In this mode, the emitter-base junction of a transistor is Forward Biased (FB) and the Collector-Base junction is Reverse Biased (RB). In the forward active biasing, the negative terminal of a battery is connected to the N-side and positive terminal to the P-side. Usually, emitter-base junction is Forward Biased (FB) & Collector-Base (CB) junction is Reverse Biased (RB). Due to FB on the emitter-base junction, an emitter current flows through the base into the collector. Though, the CB jn. Is RB, almost the entire emitter current flows through the collector circuit.

2. Saturation:In this mode, both the emitter-base and Collector-Base junctions of a transistor are Forward Biased (FB). In this mode, transistor has very large value of current. The transistor is operated in this mode, when it is used as closed switch. 3. Cut-Off:In this mode, both the emitter-base and Collector-Base junctions of a transistor are Reverse Biased (RB). In this mode, transistor has practically zero current. The transistor is operated in this mode, when it is used as an open switch.

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4. Reverse-Active:In this mode, the emitter-base junction of a transistor is Reverse Biased (RB) and the Collector-Base junction is Forward Biased (FB). The four possibilities are shown in Figure which also shows the operating region for each combination.

Operation of NPN Transistor The forward bias applied to EB junction of NPN transistor causes a lot of electrons from the emitter junction to cross over to the base jn.As, the base jn. Is lightly doped with Ptype impurity, the no. of holes in the base region is very small and hence, the no. of electrons that combine with holes in base is small. this constitutes a base current IB.The remaining electrons (more than 95%) crossover into collector region to constitute a collector current IC.Thus, base and collector current summed up gives the emitter current,i.e., IE=-(IB + IC) In the external circuit of the NPN bipolar junction transistor, the magnitudes of IE,IB, IC are related as IE=(IB + IC) .

Operation of PNP Transistor The forward bias applied to EB junction of PNP transistor causes a lot of holes from the emitter junction to cross over to the base jn.As, the base jn. Is lightly doped with N-type impurity,the no. of electrons in the base region is very small and hence,the no. of holes thet combine with electrons in base is small.this constitutes a base current IB.The remaining electrons (more than 95%) crossover into collector region to constitute a collector current IC.Thus, base and collector current summed up gives the emitter current,i.e., IE=-(IB + IC)

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In the external circuit of the PNP bipolar junction transistor,the magnitudes of IE,IB, IC are related as IE=(IB + IC) .

Transistor Current Components In the figure we show the various components which flow across the forward-based emitter junction and the reverse-biased collector junction. The emitter current IE consists of hole current IpE (holes crossing from the emitter into base) and electron current InE (electron crossing from base into the emitter). The ratio of hole to electron currents, IpE / InE, crossing the emitter junction is proportional to the ratio of the conductivity of the p material to that of the n material. In the commercial transistor the doping of the emitter is made much larger than the doping of the base. This future ensures (in a p-n-p transistor) that the emitter current consists almost entirely of the holes. Such a situation is desired since the current which results from electrons crossing the emitter junction from base to emitter does not contribute carriers which can reach the collector. Not all the holes crossing the emitter junction JE reach the collector junction Jc because some of them combine with the electrons in the n type base. If I pc is the hole current at Jc, there must be a bulk recombination current IpE - IpC leaving the base, as indicated in figure. (actually, electrons enter the base region through the base lead to supply those charges which have been lost by recombination with the holes injected into the base across JE).

Unit-4 Fig. Transistor current components

If the emitter were open-circuited so that IE = 0, then IpC would be zero. Under these circumstances, the base and collector would act as a reverse-biased diode, and the collector current Ic would equal the reverse saturation current ICO. If IE 0, then, from figure, we note that Ic = Ico - IpC For a p-n-p transistor, Ico consists of holes moving across Jc from left to right (base to collector) and electrons crossing Jc in the opposite direction. Since the assumed reference direction for Ico in figure is from right to left, then for a p-n-p transistor, Ico is negative. For an n-p-n transistor, Ico is positive. Emitter Efficiency:- () The emitter, or injection, efficiency is defined as Current of injected carriers at JE Total emitter current

In the case of a p-n-p transistor we have = IpE = IpE IpE + InE IE

Where IpE is the injected hole diffusion current at emitter junction and InE is the injected electron diffusion current at emitter junction. Transport Factor:- (*) The transport factor * is defined as * injected carrier current reaching Jc injected carrier current at JE In the case of a p-n-p transistor we have * = IpC / IpE Large signal current Gain:- () We define the ratio of the negative of the collector-current increment to the emittercurrent change from zero (cutoff) to IE as the large-signal currant gain of a common-base transistor, or = - Ic Ico / IE since Ic and IE have opposite signs, then , as defined, is always positive Typical numerical values of lie in the range of 0.90 to 0.995.

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= IpC / IE = IpC / IpE . IpE / IE = * if the transistor is in its active region,its collector current is given by, IC = - IE + Ico In the active region, IC depends on Vc and IE . The generalized equation is, Ic = - IE + Ico (1- eVc / Vt) Transistor Amplifying Action The basic circuit of a transistor amplifier is as shown in fig:-

Here, the weak signal to be amplified is applied between emitter-base circuit and output is taken across load resistor RL connected in the collector circuit. A D.C. voltage VEE is also connected in the input circuit in order to maintain in forward bias for even negative peak of applied signal. A small change in signal vtg produces an appreciable change in emitter current because the input circuit has low resistance. Now, due to transistor action, the change in emitter current causes almost same change in collector current. when Ic flows through load resistance RL,a large vtg is dropped across it. In this way, a weak signal applied in the input circuit appears in the amplified form of the output circuit. Let a small voltage Vi between E and B cause relatively large emitter current change IE. = IC / IE => IC = IE If the dynamic resistance of EB junction is re, then, Vi= re IE Output voltage across RL , =>Vo = IC RL =>Vo = IE RL Therefore, the voltage amplification, A= Vo / Vi =>A=IERL / re IE =>A= RL/ re And A is always greater than unity, and thus, the transistor acts as amplifier. Transistor Manufacturing Techniques The basic techniques used for transistor manufacturing are:1) Grown junction type 2) Alloy (or) fused junction type 3) Diffused junction type 4) Epitaxial type

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Depending upon the manufacturing technique, a transistor may be called as grown junction type transistor, Alloy (or) fused junction type transistor, Diffused junction type transistor, Epitaxial type transistor. Each type of the transistor construction is discussed as follows:1) Grown junction type In this type, a single crystal is drawn from molten silicon or germanium. The impurity concentration of the silicon crystal is changed during the crystal drawing operation by adding N-type or P-type impurities as required. Then, the grown crystal is cut into small area devices and the contacts are made to each region as shown in fig:-

2) Alloy (or) fused junction type In this type, two small dots of indium (a P-type impurity) are placed on the opposite sides of a thin wafer of N-type material. The whole structure is heated for a short time to a temperature high enough to melt indium into base material. The alloying of indium, with the original wafer produces the PN junctions. The leads may be connected to the structure as shown:-

It may be noted that collector region is made larger than the emitter region. This has an advantage that collector collects the whole emitter current and thus, prevents the current from diffusing into the base region. 3) Diffused junction type In this type, a semiconductor wafer is subjected to gaseous diffusion of both N and Ptype impurities to form both the emitter-base and collector-base junctions. This process is called planar process. The transistors manufactured by using planar process are known as silicon planar transistors. And are as shown in fig...

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The manufacturing process starts with a N-type silicon wafer. The collector-base junction area is determined by diffusion mask. This area is photo etched by photolithographic techniques. Then the P-type base is applied by gaseous diffusion process. Next, the N-type emitter is diffused into the base through a different mask. A thin layer of silicon dioxide is grown over the entire surface. This layer is photo etched to make aluminum contacts for emitter and base leads. The presence of oxide layer avoids most of the surface problems and hence, results in a very low transistor leakage current. 4) Epitaxial type :In this type, a very thin single crystal layer of silicon or germanium is grown on a heavily doped substrate of the same material. This layer forms a collector on which base and emitter regions may be diffused. The epitaxial type of transistor is as shown in fig

The techniques discussed above may be combined to form a large number of methods for constructing transistors. For example, there are diffused-alloy types, grown-diffused types, alloy-emitter epitaxial-base transistors etc TRANSISTOR CONFIGURATIONS OR CONNECTIONS A transistor has three terminals but we need two supplies hence four terminals to connect the transistor in a circuit. Therefore, one terminal of the transistor is kept common, this arrangement gives us three connections/configurations for a transistor. The input is given between the common terminal and one of the two other terminals. Similarly, output is obtained between the common terminal and the left out third terminal. But remember that for Satisfactory operation in all the configurations, the input side is to be forward biased and the output side is to be reverse biased. By keeping one transistor terminal common at a time, we can have three transistor Configurations.

Unit-4 Common base (CB) configuration Common emitter (CE) configuration Common collector (CC) configuration

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1) Common base configuration In this configuration base terminal is connected as a common terminal. The input is applied between the emitter and base terminals. The output is taken between the collector and base terminals.

2) Common emitter configuration In this configuration emitter terminal is connected as a common terminal. The input is applied between the base and emitter terminals. The output is taken between the collector and base terminals.

3) Common collector configuration In this configuration collector terminal is conncted as a common terminal.The input is applied between the base and collector terminals.The output is taken between the emitter and collector terminals

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Current gain of transistor in Common-Base Configuration:It is defined as the ratio of the collector current IC to the emitter current IE and is usually denoted as . Mathematically,

The actual value of ranges from 0.95 to 0.998. Current gain of transistor in Common-Emitter Configuration:It is defined as the ratio of the collector current IC to the base current IB and is usually denoted as . Mathematically,

Typical values of ranges from 20 to 250. Current gain of transistor in Common-Collector Configuration:It is defined as the ratio of the emitter current IE to the base current IB and is usually denoted as . Mathematically,

And the relation between and is given as, It means that the output current of a Common-Collector transistor is (1+ ) times that of input current. We know that >> 1, therefore Common-Collector current gain is approximately equal to . Relation between Current Gain and :We know that emitter current IE of a transistor is the sum of its base current IB and collector current IC. IE = (IB + IC) Dividing the above equation both sides by IC, (IE / IC) = (IB / IC) + 1 Since, = (IC / IE) and = (IC / IB) ,therefore, 1 1 1+ = +1=

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1+

The above equation may be written as , => ( + 1) = => + = => = = (1 ) => = 1 Base Spreading Resistance The width of the base region of a transistor is extremely small. Therefore, the current which enters the base region, across emitter-base junction, has a narrow path to reach the base terminal. The resistance offered by this narrow path region is called base spreading resistance and it is denoted by rb. The value of this resistance can be increased by increasing the reverse bias voltage (Vcb) across the collector-base junction. It is because of the fact that, by increasing the value of Vcb, the width of the collector base depletion layer increases. Since, the depletion layer penetrates more into the base region than that of collector, therefore, the cross sectional area of the base is reduced. The smaller the cross sectional area means a large Base Spreading Resistance. Its value is about 50 to 150. Characteristics of a transistor in Common Base Configuration The circuit diagram for determining the characteristic curves of NPN transistor in common base configuration is as shown in fig:-

Input characteristics These curves gives the relationship between the input current and input voltage for a given output voltage.i.e, it gives the relation between IE and VEB for a constant VCB. In the above circuit diagram, IE = emitter current IC = collector current VEB = emitter-base voltage VCB = collector-base voltage The VCB is varied by changing the position of potentiometer R2 while, the VEB is varied changing the position of potentiometer R1. To determine the Input characteristics, VCB is kept constant at 0v and IE is noted by increasing the VEB in small suitable steps. This is repeated for higher fixed values of V CB.A

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curve is drawn between IE and VEB at constant VCB. The Input characteristics thus obtained are as shown in fig:-

When VCB=0v, the EB junction is forward biased and the junction behaves as forward biased diode. So, IE increases rapidly with small increase in VEB. When VCB is increased above 1v, the curves shift upwards. It occurs due to phenomenon called BASE WIDTH MODULATION (or) EARLY EFFECT. The a.c. input resistance, RI=VEB/ IE Its value is about 50 . Early Effect (or) Base Width Modulation As, the VCC is made to increase, the reverse bias increases and the depletion layer between the collector and base increases. Therefore, the width of the base region decreases. This dependency of base width on VCE is known as early effect. This decrease in effective base width has 3 consequences:1) It reduces the chances of recombination of electrons with holes in base. Hence, increases with increase in VCB. 2) The concentration gradient of the minority carriers with in the base increases. This increases the emitter current IE. 3) For extremely large collector voltage, the effective base width may be reduced to zero, causing voltage breakdown of a transistor. This phenomenon is called punch through. Output characteristics These curves gives the relationship between the output current and output voltage for a given input current.i.e, it gives the relation between IC and VCB for a constant IE. To determine the output characteristics, IE is kept constant at a suitable value by adjusting the VEB .Then, VCB is increased in small suitable equal steps and the collector current IC is noted for each step. This is repeated for higher fixed values of IE .A curve is drawn between IC and VCB at constant IE. The output characteristics thus obtained are as shown in fig:-

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The output characteristics curve may be divided into 3 important regions, namely saturation region, active region and cut off region. The saturation region is the region to the left of the vertical line. Here, V CB is negative for NPN transistor. It means CB junction of a transistor is also forward biased in saturation region. In this region, a small change in VCB results in large value of current. The active region is the region between vertical line and horizontal axis. In the active region, IC is constant and is equal to IE. The cut off region is the region along horizontal axis, as shown by dashed region. It corresponds to the curve IE=0.In this region, both junctions are reverse biased. The I C flows, even when IE is zero. This current is called collector leakage current and is denoted by ICBO. The output resistance, RO= VCB/ IC The value of Ro is very high. It is about 500k. Characteristics of a transistor in Common Emitter Configuration The circuit diagram for determining the characteristic curves of NPN transistor in common emitter configuration is as shown in fig:-

Input characteristics To determine the Input characteristics, VCE is kept constant at 0v and IB is noted by increasing the VBE in small suitable steps. This is repeated for higher fixed values of VCE.A curve is drawn between IB and VBE at constant VCE. The Input characteristics thus obtained are as shown in fig:-

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When VCE=0v, the EB junction is forward biased and the junction behaves as forward biased diode. Hence, the Input characteristics for VCE=0v is similar to that of forward biased diode. When VCE is increased, the width of the depletion region at the reverse biased CB junction will increase.This effect wil decrease the base current IB. Hence, to get the same value of IB as that for VCE=0v, VBE should be increased.Therefore, curve shifts to the right, as VCE increases. The a.c. input resistance, RI=VBE/ IB Its value is about 600 to 4K. Output characteristics To determine the output characteristics, IB is kept constant at a suitable value by adjusting the VBE .Then, VCE is increased in small suitable equal steps from 0v and the collector current IC is noted for each step. This is repeated for higher fixed values of IB .A curve is drawn between IC and VCE at constant IB. The output characteristics thus obtained are as shown in fig:-

The output characteristics curve may be divided into 3 important regions, namely saturation region, active region and cut off region. As, VCE is increased from zero, the IC increases rapidly to a saturation value, depending on IB. When IB=0, a small current exists. This is called leakage current. This region is called cut off region. The central region, where the curves are uniform in spacing and slope is called active region. In this region, transistor is used as linear amplifier. The output resistance, RO= VCE/ IC The value of Ro is about 10k to 50k.

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Characteristics of a transistor in Common Collector Configuration The circuit diagram for determining the characteristic curves of NPN transistor in common collector configuration is as shown in fig:-

Input characteristics To determine the Input characteristics, V EC is kept at suitable fixed value. The collector voltage VBC is increased in steps and the corresponding IB is noted. This is repeated for different fixed values of VEC as shown in fig:-

Output characteristics The Output characteristics are same as common emitter configuration and the plot VEC versus IE is as shown in fig:-

COMPARISON OF TRANSISTOR CONFIGURATIONS:Sr.No . Characteristic Common Base Common Emitter Common Collector

Unit-4 1. 2. 3. 4. 5. 6. 7. 8. Input resistance Output resistance Input current Output current Current Gain Voltage Gain Phase Shift between Input & Output voltages Applications Low(100) High(450 k) IE IC 1 About 150 0 or 3600 For high frequency circuits Moderate(750) Moderate (45k) IB IC High About 500 1800 For Audio frequency circuits

17 High(750 k) Low(25) IB IE High Less than 1 0 or 3600 For Impedance matching

Ebers Moll model:The general expression for collector current IC of a transistor for any voltage across collector junction VC and emitter current IE is, IC= - NIE - ICO(e VC/VT - 1) Where, N is the current gain in normal operation. ICO is the collector junction reverse saturation current. In inverted mode of operation, the above equation can be written as, IE= - IIC - IEO(e VE/VT - 1) Where, I is the inverted common base current gain. IEO is the emitter junction reverse saturation current. The above 4 parameters are related by the condition, N ICO = I IEO For many transistors, IEO lies in the range of 0.5 ICO to ICO. The Ebers Moll model for a PNP transistor is as shown in fig:-

Here, two separate ideal diodes are connected back to back with saturation currents -IEO and - ICO and there are two dependent current controlled current sources shunting the ideal diodes. The current sources account for the minority carrier transport across the base. An application of Kirchhoffs current law to the collector node in the above fig. gives, IC= - NIE + I => IC= - NIE +Io(e VC/VT - 1)

Unit-4 Where, I is the diode current. As, Io is the magnitude of reverse saturation current, then , Io = - ICO Substitute, Io in the above equation, IC= - NIE - ICO(e VC/VT - 1)

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This is nothing but the general expression for collector current of a transistor. Hence, this model is valid for both forward and reverse static voltages applied across the transistor junctions. The dependent current sources can be removed, provided N = I = 0. If the base width is made much larger than the diffusion length of minority carriers in the base, all minority carriers will recombine in the base and no minority carrier will be available to reach the collector. Therefore, the transistor amplification factor becomes zero. Hence, it is possible to construct a transistor by simply placing two isolated diodes back to back. Field Effect Transistor The FET is a device in which flow of current through the conducting region is controlled by an electric field. Hence, the name Field Effect Transistor. As current conduction is only by majority carriers, FET is said to be unipolar device. In FET, the output characteristic is controlled by input voltage. Hence, it is also called as voltage controlled device. FET Classification

Junction Field Effect Transistor (JFET) The JFETs can be divided into 2 types depending upon their structure. 1) N-Channel JFET 2) P-Channel JFET

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Fig. N-channel JFET

Fig. P-channel JFET

The basic construction of an N-channel JFET is as shown in the figure above. It consists of N-type semiconductor bar with two P-type heavily doped regions diffused on opposite sides of its middle part. The P-type regions form two PN junctions. The space between the junctions is called channel. Both the P-type regions are connected internally and a single wire is taken out in the form of terminal called Gate. The electrical connections called ohmic contacts are made to both ends of N-type semiconductor and are taken out in the form of two terminals called Drain and Source. The Drain is a terminal through which electrons leave the semiconductor bar and Source is the terminal through which electrons enter the semiconductor. Whenever a voltage is applied across Drain and Source terminals, current flows through the N-channel. The current consists of only one type of carriers (i.e., electrons.). Therefore, FET is called unipolar device. Symbols for JFET

The construction of P-channel JFET is also similar to N-channel JFET,except that it consists of P-channel and N-type junctions. The current carriers in P-channel JFET are holes, which flow through P-type channel. Operation of N-Channel JFET Consider an N-Channel JFET as shown in figure. Here, P-type gate and N-type channel constitutes the PN Junction. This PN junction is always reverse biased in JFET operation. The reverse bias is applied by voltage VGG connected between Gate and Source terminals. The reverse bias across Gate-Source junction of a JFET may also be achieved by applying a voltage across Drain and Source. D is connected to the positive terminal of VDD and D is connected to the negative terminal of VDD. In the presence of positive supply voltage VDD, the electrons flow from Source to Drain through N-Channel and constitute a current known as Drain Current. The conventional current direction of drain currant is indicated from drain to source through the device.

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Fig. Depletion Regions in JFET When VGS=0 and VDS=0 When no voltage is applied between D-S and G-S, the thickness of depletion regions round the PN junctions is uniform. When VDS=0 and VGS is decreased from Zero In this case, PN junctions are reverse biased and hence, the thickness of depletion region increases. As, VGS is decreased from zero, the reverse bias voltage across PN junction is increased and Hence, the thickness of depletion region in the channel increase until the two depletion regions make contact with each other. In this condition, the channel is said to be cut off. The value of VGS which is required to cut off the channel is called Cut off voltage VC. When VGS=0 and VDS is increased from Zero D is positive w.r.t. S with VGS=0. now, majority carriers flow through N-channel from Source to Drain. Therefore, ID flows from D to S. the magnitude of current depends on the following factors:1) The number of majority carriers available in the channel. 2) The length of the channel 3) The cross-sectional area of the channel at B. 4) The magnitude of the applied voltage VDS ID = VDS / R And R = L /A => ID = AVDS / L Where, is the resistivity of the channel.

Fig: JFET under applied bias Because of the resistance of the channel and applied voltage VDS, there is a gradual increase of positive potential along the channel from S to D. thus, the reverse voltage across the PN junctions increases and hence, thickness of depletion region also increases. Therefore, channel is wedge shaped as shown in fig.

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As, VDS is increased, the cross sectional area of the channel will be reduced. At certain value, Vp of VDS, the cross sectional area at B becomes minimum. At this voltage, the channel is said to be pinched off and the drain voltage Vp is called pinch-off voltage. Even, if VDS is increased, after some voltage, avalanche break down will occur. So, ID increases abruptly. If we apply negative VGS, pinch off will occur for smaller values of VDS and maximum drain current is small. Static Characteristics These are the curves which gives the relation between input voltage,output voltage and currents. These are:1) Input or Gate or Transfer Characteristics. 2) Output or Drain Characteristics. Transfer Characteristics The curve drawn between ID and VGS at constant VDS is known as Transfer Characteristics.

Drain Characteristics The curve drawn between ID and VDS at constant VGS is known as Drain Characteristics.

There are 3 regions in Drain Characteristics. Ohmic region Pinch-off region or Saturation region Breakdown region

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In Ohmic region, ID increases linearly with increase in VDS obeying ohms law. Thus, it is useful as voltage variable resistor (VVR). In the above Drain Characteristics curve, Ohmic region is from VDS =0 to VDS = Vp. When VDS = Vp, ID becomes maximum. When VDS is increased beyond Vp, the length of Pinch-off region or Saturation region increases. Hence, there is no further increase of ID. in this region, FET is used as amplifier. At certain voltage, ID increases suddenly. This effect is due to avalanche multiplication of electrons caused by breaking of covalent bonds of silicon atoms in the depletion region between G and D. BVDGO is the voltage at which breakdown occurs. When VGS is negative and VDS is increased, when the gate is maintained at a negative voltage less than negative cut off voltage, the reverse voltage across the junction is further increased. Hence, for a negative of VGS, the curve of ID Vs VDS is similar to that for VGS=0, but values of Vp and BVDGO are lower. Circuit arrangement for plotting JFET Characteristics

Characteristic parameters of JFET In a JFET, the I D depends on VDS and VGS. Any one of these variables may be fixed and relations between the other two are determined. There are 3 parameters to determine these relations. 1) Mutual conductance (or) transconductance, gm:It is the slope of transfer characteristic curve and is defined by, gm = ID VGS VDS = ID VGS VDS held constant.

It is the ratio of small change in the drain current to the corresponding small change in gate voltage at constant VDS. Its unit is mho. 2) Drain resistance, rd:It is the reciprocal of slope of drain characteristics and is defined by, rd = VDS ID VGS = VDS ID VGS held constant.

It is the ratio of small change in the drain voltage to the corresponding small change in drain current at constant VGS. Its unit is ohms.

Unit-4 Drain conductance, gd (or) gos = (1/rd). 3) Amplification factor, :It is defined as, = VDS VGS ID = VDS VGS ID

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It is the ratio of small change in the drain voltage to the corresponding small change in gate voltage at constant ID. Here, negative sign indicates that, when VGS is increased, VDS must be decreased for ID to remain constant. 4) Relationship between FET parameters:The functional equation can be expressed as, ID = f (VDS ,VGS) The small change in I D may be obtained by applying Taylors theorem with neglecting higher order terms. ID = ID VDS + ID VGS

VDS VGS

VGS VDS =0

Dividing both sides by VGS ,and by taking ID

VGS = rd gm 5) Power Dissipation, Pd:It is the product of ID and VDS. => Pd = ID VDS Small Signal Model of JFET The low frequency model for FET has Nortons output circuit with a dependent current generator whose magnitude is proportional to VGS. The proportionality factor is the transconductance gm. the output resistance is rd.the input resistance between gate and source is infinite. Since, it is assumed that reverse biased gate draws no current, the resistance between G and D is assumed as infinite.

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Fig. Small Signal Model for JFET The high frequency model for JFET is as shown in fig. Here, the capacitances between nodes have to be added in the low frequency model. The CGS is the barrier capacitance between G and S. The CGD is the barrier capacitance between G and D. The CDS is the drain to source capacitance of the channel. These internal capacitances lead to feedback from output to input and the voltage amplification decreases at higher frequencies.

Fig. High Frequency Model for JFET Expression for Saturation Drain Current For the transfer characteristics, VDS is maintained constant at a suitable value greater than the pinch-off voltage Vp. The VGS is decreased from zero till ID is reduced to zero. The transfer characteristics shape is nearly a parabola. IDS = IDSS 1 - VGS Vp Where, IDS = Saturation Drain Current IDSS is value of IDS when VGS = 0 Vp is the pinch-off voltage Differentiating w.r.t VGS, gm = -2IDSS 1 - VGS Vp From eq (i), 1 - VG Vp = IDS IDSS
1/2 2

(i)

Vp

(ii)

(iii)

Substitute this value in eq (ii) , => gm = 2 (IDS * IDSS )1/2

Unit-4 Vp Suppose, gm = gm0 , when VGS = 0 , Therefore, from eq(ii) , gm0 = -2IDSS Vp Therefore, gm = gm0 1 - VGS Vp (iv)

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Eq (iii) shows that gm varies as the square root of Saturation Drain Current IDS. And eq (iv) shows that gm decreases linearly with increase of VGS. Applications of JFET 1. FETs are used as RF amplifiers in FM tuners and communication equipment for low noise level. 2. FETs are used in cascade amplifiers. 3. It is used in oscillator circuits. 4. FETs are used as mixer circuits in FM and TV receivers and communication equipment. 5. It is used as voltage variable resistor in operational amplifiers and tone controls. 6. FETs are used as digital circuits in computers. 7. FETs are used as buffer in measuring instruments and receivers. Comparison of JFET and BJT S.no. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Junction Field Effect Transistor In FET, the operation depends only on flow of majority carriers. It is unipolar device. FET is less noisy than BJT, as it has no junctions and conduction is through Ntype or P-type channel. FET is voltage controlled device i.e., output is controlled by input voltage. FETs occupy less space than BJTs. Thus, these are much easier to fabricate. FETs are costlier to produce. The performance of FET is unaffected by ambient temperature changes. FET has higher switching speed and cut off frequencies. Common source configuration is most popular. FET can act as buffer amplifier. Bipolar Junction Transistor In BJT, the operation depends on flow of both majority and minority carriers. It is bipolar device. BJT is more noisy than FET, as BJT has 2 junctions. BJT is current controlled device i.e., output is controlled by input current. BJTs occupy more space than FETs. Thus, these cannot be used in fabrication of ICs. BJTs are cheaper to produce. The performance of BJT is affected by ambient temperature changes. BJT has lower switching speed and cut off frequencies. Common emitter configuration is most popular. BJT cannot be used as buffer

Unit-4 amplifier. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) The MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. Like JFET, it has source, drain, gate terminals. In case of MOSFET, the gate is insulated from the channel. Because of this, it is sometimes known as Insulated Gate FET (IGFET).

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Fig. Construction of MOSFET Basically, MOSFETs are of two types. 1. Depletion type MOSFET 2. Enhancement type MOSFET The device operates in Depletion mode, when gate voltage is negative. The device operates in Enhancement mode, when gate voltage is positive. Depletion MOSFET is divided into 2 types. 1. N-Channel 2. P-Channel Enhancement MOSFET is divided into 2 types. 3. N-Channel 4. P-Channel N-Channel Depletion MOSFET The N-Channel Depletion mode MOSFET consists of lightly doped P-type substrate into which 2 heavily doped N+ regions are diffused, which acts as source and drain. The source and drain terminals are connected through metallic contacts to n-doped regions linked by N- Channel as shown. The source and drain are separated by I milliinch. A thin insulating layer of Sio2 is grown over the surface of the structure and holes are made into the oxide layer, allowing contact with the source and drain. Then, a thin layer of metal aluminium is formed over the layer of Sio2. this layer covers the entire channel region and it forms the gate G. The metal area of the gate, in conjunction with the insulting oxide layer of Sio2, and the semiconductor channel forms a parallel plate capacitor. The Sio2 layer gives an extremely high input impedance for MOSFET.

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Fig. N-Channel Depletion MOSFET When VGS= 0, and the drain is at positive potential w.r.t source, the electrons flow through the N-Channel from source and drain. Therefore, conventional current direction ID flows through the channel from drain to source. If the gate voltage is made negative, positive charge consisting of holes is induced in the channel through Sio2 of the gate channel capacitor. The introduction of positive charge causes the depletion of mobile electrons in the channel. Thus, a depletion region is produced in the channel. The shape of the depletion layer depends on VGS and VDS. Hence, the channel will be wedge shaped as shown in fig.

Fig. transfer characteristics

Fig. Drain characteristics

When VDS is increased, ID increases and becomes practically constant at a certain value of VDS, called pinch off voltage. The ID almost gets saturated beyond the pinch off voltage. As, VGS is made negative, the conductivity of the channel decreases and thus,ID drops to zero.

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The Depletion MOSFET may also be operated in Enhancement mode. It is also necessary to apply a positive gate voltage, so that negative charges are induced into the Ntype channel. Hence, conductivity of the channel increases and ID increases. As the Depletion MOSFET can be operated in both modes, it is also called as dual mode MOSFET. The Depletion MOSFET can conduct, even if the VGS=0. Hence, it is called as normally-ONMOSFET. The curve ID Vs VGS for a constant VDS is called transfer characteristic of MOSFET. This curve extends for positive values of VGS. The IDSS represents the current from drain to source with VGS=0. Circuit Symbol for Depletion type MOSFET

In the above fig., the vertical line represents channel. The D and S terminals are connected to the top and bottom of the channel. In N-type, the arrow on the P-type substrate points towards the channel. In some MOSFETs, a connection from substrate is also taken out. Such, MOSFETs have 4 terminals. But, in most of the MOSFETs, the substrate is internally connected to the source. This results in a 3 terminal device. In P-channel Depletion type MOSFET, the arrow direction is away from the channel which indicates that the channel is of P-type material. Enhancement type MOSFET It is same as the construction of Depletion MOSFET, except there is no diffused channel between source and drain terminals. The construction of Enhancement MOSFET is as shown.

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Fig. Enhancement type MOSFET The MOSFET is always operated with positive VGS. When VGS=0, the VDD supply tries to force free electrons from source and drain. But, the presence of P-region does not permit the electrons to pass through it. Thus, there is no drain current for VGS=0. so, the Enhancement type MOSFET is also called as normallyOFFMOSFET. Now, if some positive voltage is applied at the gate, it induces a negative charge in the P-type substrate, just adjacent to the Sio2 layer. The induced negative charge is produced by attracting the free electrons from the source. When the gate voltage is made positive enough, it can attract a number of free electrons. This forms a thin layer of electrons, which stretches from source to drain. This effect is equivalent to producing a thin layer of N-type channel in the P-type substrate. This layer of free electrons is called N-type inversion layer. The minimum VGS, which produces the inversion layer, is called threshold voltage and is designated by VGS(th) or VGST. When the VGS < VGST, no current flows from D to S. When the VGS > VGST, the inversion layer connects from drain and source and therefore, current flows from D to S.

Circuit Symbol for Enhancement type MOSFET

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In these symbols, broken line indicates that there is no conducting channel between source and drain, when VGS =0. The drain and source terminals are shown at the top and bottom end of the broken line. The substrate is internally connected to the source as shown. Uni Junction Transistor The basic structure of a uni junction transistor (UJT) is shown in Fig.. It is essentially a bar of N type semiconductor material into which P type material has been diffused somewhere along its length. Contacts are then made to the device as shown; these are referred to as the emitter, base 1 and base 2 respectively.

The total base resistance of silicon bar with emitter terminal open is called inter base resistance. It is given as, RBB = RB1 + RB2 Where, RB1 is resistance between B1 and E RB2 is resistance between B2 and E The resistance RB1 is variable because its value depends on the bias voltage across PN junction. Usually RB1>RB2 and RB1=60% of RBB in the equivalent circuit,VBB is connected across B1B2 and E acts as voltage divider tap on the fixed resistance RBB. A part of Vbb is dropped over R B2 and a part on RB1. let the voltage drop across RB1 is VA. Applying voltage divider rule, VA = RB1 VBB

Unit-4 (RB1+RB2) The ratio VA/VBB is called intrinsic stand off ratio and is represented by . = RB1 = (RB1+RB2) RB1 RBB

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A Unijunction transistor is a three terminal semiconductor switching device. This device has a unique characteristics that when it is triggered , the emitter current increases regenerative until is limited by emitter power supply the unijunction transistor can be employed in a variety of applications switching pulse generator saw tooth generator etc. Operation

The device has normally B2 positive w.r.t B1. If voltage VBB is applied between B2 and B1 with emitter open. Voltage gradient is established along the n type bar since emitter is located nearer to B2 more than half of VBB appears between the emitter and B1. The voltage V1 between emitter and B1 establishes a reverse bias on the pn junction and the emitter current is cut off. A small leakage current flows from B2 to emitter due to minority carriers. If a positive voltage is applied at the emitter the pn junction will remain reverse biased so long as the input voltage is less than V 1 if the input voltage to the emitter exceeds V1 the pn junction becomes forward biased. Under these conditions holes are injected from the p type material into the n type bar these holes are repelled by positive B2 terminal and they are attracted towards B1 terminal of the bar. This accumulation of holes in the emitter to B1 region results in the degrees of resistance in this section of the bar the internal voltage drop from emitter to B1 is decreased hence emitter current IE increases as more holes are injected a condition of saturation will eventually be reached at this point a emitter current limited by emitter power supply only . The device is in on state. If a negative pulse is applied to the emitter, the pn junction is reverse biased and the emitter current is cut off. The device is said to be off state. Characteristics of UJT:The curve between Emitter voltage Ve and emitter current Ie of a UJT at a given voltage Vbb between the bases,This is known as emitter characteristic of UJT.

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Initially in the cut off region as Ve increases from zero, slight leakage current flows from terminal B2 to the emitter the current is due to the minority carriers in the reverse biased diode. Above a certain value of Ve forward Ie begins to flow, increasing until the peak voltage Vp and current Ip are reached at point P. After the peak point P an attempt to increase Ve is followed by a sudden increase in emitter current Ie with decrease in Ve is a negative resistance portion of the curve.The negative portion of the curve lasts until the valley point Vv is reached with valley point voltage Vv.and valley point current Iv after the valley point the device is driven to saturation the difference Vp-Vv is a measure of a switching efficiency of UJT fall of Vbb decreases.Therefore,the curves for different Vbb are as shown:-

Advantages of UJT: It is a Low cost device It has excellent characteristics It is a low-power absorbing device under normal operating conditions Silicon Controlled Rectifier:-

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It is a four layer semiconductor device being alternate of P-type and N-type silicon. There are 3 junctions J1, J2, J3. J1 and J3 operates in forward direction while the middle operates in reverse direction. The 3 terminals are Anode (A), Cathode (K) and Gate (G). The function of gate is to control the firing of SCR. It conducts only in one direction. i.e., from A to K and hence constitutes unidirectional device.

Operation of SCR:In SCR, a load is connected in series with the anode and it is kept at positive potential w.r.t. cathode with the help of battery. There are two cases: Gate is open Gate is positive.

When Gate is open, no voltage is applied at the gate. Under this condition, J 1 and J3 are forward biased while, junction J2 is reverse biased. Due to reverse bias of J2, no current flows through RL and hence, SCR is cut off. When anode voltage is increased, a certain critical value is reached where the J2 breaks down. The SCR now conducts heavily and is said to be ON state. When Gate is positive w.r.t. cathode, J 3 is forward biased while J2 is reverse biased. The electrons from the N material move across J3 towards gate while holes from P-type material moves across J3 towards cathode. So, gate current starts flowing. Due to this, the anode current increases. This makes more electrons at junction J2. In an extremely small time, J2 breaks down and SCR conducts heavily. Once, SCR conducts, gate loses all controls. The volt-ampere characteristic of SCR for I G=0 is as shown in fig:-

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When anode is positive w.r.t. cathode, the characteristic is known as forward characteristic. It is shown by the curve OABC. When the supply voltage is increased from zero,a point A is reached, where SCR starts conducting. The voltage corresponding to A is called forward break over voltage. At this voltage,J 2 breaks down and SCR switches suddenly to a high conducting state. When Gate is open, the break down voltage is defined as minimum forward voltage at which SCR starts conducting heavily. Under this condition, the voltage across SCR suddenly drops as shown by the curve AB. The current corresponding to point B is denoted by IH. it is known as holding current. The holding current is the maximum anode current, gate being open, at which SCR is turned OFF from ON condition. Above holding current, SCR is ON state and there is maximum value of anode current at which an SCR is capable of passing without destruction. This is known as forward current rating and is expressed by IF. When anode is negative w.r.t. cathode, the characteristic is known as reverse characteristic. When the anode voltage is gradually increased, at first the anode current remains small. But, at a particular value, avalanche break down occurs and SCR starts conducting in reverse direction. This is shown by the curve DE. The voltage corresponding to D is known as reverse break down voltage. The SCR forward characteristic for different gate currents is as shown in fig:-

When the gate current is supplied, SCR fires even with much lower anode voltage. Higher the value of gate current, lower is the value of anode voltage at which break down occurs. Once, SCR has fired, the gate loses its controlling action and the SCR cannot be turned off by gate signals. The only way to bring back SCR to normal OFF condition is to reduce the anode voltage sufficiently for anode current to drop below holding current IH.

Unit-4 Two Transistors Analogy of SCR:-

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The operation of SCR can be explained by dividing it into 2 transistors. PNP transistor T1 NPN transistor T2

The collector of each transistor is coupled to the base of other. This makes positive feedback loop. If the supply voltage V is less than break over voltage, with gate open, the base current of T2 is zero. Therefore, no current flows in the collector of T2 and hence that of T1. Under this condition, SCR is open. With gate closed , a small gate current flow through the base of T 2. This increases its collector current. As, the collector current of T2 is the base current of T1, so, the collector current of T1 increases. Further, the collector current of T1 is also the base current of T2. Therefore, an increase in current of one transistor causes an increase of current in the other transistor. This process is accumulative and both transistors are driven into saturation. Now, a heavy current flows through the load and SCR is in ON condition. Applications:1) 2) 3) 4) 5) Speed control of a.c. motors Voltage regulators Speed control of d.c. motors Regulated power supplies Phase control