Miller Pole Splitting and Zero

Objective
The step response of a two-pole amplifier depends on the ratio of the pole frequencies, with less ringing of the output when the poles are widely separated. However, for any fixed ratio, the speed of the system is determined by the higher pole frequency, becoming faster as the second pole frequency increases. Thus, it becomes important to understand how the frequency of the second pole can be increased. One way to do this is to use Miller compensation. For a simple two-stage amplifier we show here how the pole frequencies behave when Miller compensation is used. We also show that the zero introduced by Miller compensation can interfere, limiting the advantages of the higher frequency pole.

Schematic
+

CC R1
+

R2
+

VA

AC Sweep

A1VIN
0

C1

+ VIN

+
+

+ V1

+
0

A2V1

C2

+ VO
0

FBVO

+
0

+ VO

FIGURE 1
A feedback voltage amplifier with Miller compensation using compensation capacitor CC

Figure 1 shows a two-stage feedback voltage amplifier with voltage feedback FB. The capacitor CC is inserted between the first and second stage to change the poles of the open-loop amplifier (the amplifier with FB = 0). Specifically, CC moves the low-frequency pole lower in frequency, and the high-frequency pole higher in frequency (pole splitting). These shifts in the poles make them further apart, which has two effects: making the higher-frequency pole higher in frequency allows a faster step response, while making the poles further apart reduces ringing of the step response.

Analysis
First, we look at the modification of the poles in the open-loop amplifier. We split the open-loop amplifier into an input and an output side. On the input side we obtain Figure 2 below, where the Miller capacitance is given by EQ. 1
V CM = CC 1 O , V1

with VO the output voltage, which is applied to the output side of CC in Figure 1.

Create Date 4/16/06 by J R Brews

Page 1

4/17/2006

R1
+

+ C1 CM V1
+ +

VA

+
AC Sweep

+ VIN

A1VIN
0

FIGURE 2
Input side of amplifier using the Miller capacitance

Based upon Figure 2 we find EQ. 2

V1 A 1 . = VIN 1 + j(C1 + CM )R1

We then move to the output side of the amplifier, as shown in Figure 3.

jCC (V1 VO )
+

R2 + A2V1 C2 VO
+

FIGURE 3
Output side of the circuit with VCCS representing the current supplied by the compensation capacitor CC

Using Figure 3 we find EQ. 3

VO A 2 + jCCR2 . = V1 1 + j(CC + C2 ) R2

which combines with EQ. 1 to provide EQ. 4

1 A 2 + jC2R2 V CM = CC 1 O = CC 1 + j(C + C ) R . V1 C 2 2

The Miller approximation neglects the frequency dependence of CM, but here we dont use this approximation because we want the exact frequency dependence. We now find the overall gain as the product of EQ. 2 and EQ. 3, to find EQ. 5

(A 2 + j CCR2 )A1 VO V V . = 1 O = VIN VIN V1 (1 + j (CC + C2 ) R2 ) (1 + j C1 R1) + j CCR1(1 A 2 + j C2R2 )

Create Date 4/16/06 by J R Brews

Page 2

4/17/2006

Pole splitting
We multiply out the denominator and collect powers of to find the denominator in the form EQ. 6
Deno min ator = (1 + j 1) (1 + j 2 ) = 1 + j (1 + 2 ) + (j )2 (12 ) ,

with the coefficients determined from EQ. 5 as EQ. 7 and EQ. 8

1 + 2 = (CC + C2 ) R2 + (C1 + CC (1 A 2 )) R1 ,

12 = (CCC1 + C2C1 + C2CC ) R1R2 .

Because our amplifier will exhibit good step response only if we make the two time constants far apart, we now assume the longer time is 1 and 1 >> 2. Then EQ. 7 is very nearly 1, and EQ. 8 provides 2 as EQ. 9

(CCC1 + C2C1 + C2CC ) R1R2 2 = 1 2 1 2 = . 1 1 + 2 (CC + C2 ) R2 + (C1 + CC (1 A 2 )) R1

Interpreting EQ. 7 as 1 and assuming A2 is large and negative, we see that CC greatly increases 1. In fact, if the term in CC dominates, we have approximately EQ. 10
1 (CC + C2 ) R2 + (C1 + CC (1 A 2 )) R1 (CC (1 A 2 )) R1 ,

which increases linearly with CC. Likewise, using EQ. 9 assuming the terms in CC dominate, we find EQ. 11
2

(CCC1 + C2CC ) R1R2 = (C1 + C2 ) R2R1 (C1 + C2 ) R2 , 12 (1 A 2 ) 1 + 2 (CC ) R2 + (CC (1 A 2 )) R1 R2 + ((1 A 2 )) R1

which is independent of CC and decreases inversely with A2. Thus the higher frequency pole increases initially in frequency as CC increases, but becomes locked in at a value independent of CC when CC is large enough.

Zero
The gain expression EQ. 5 also exhibits a zero at the frequency EQ. 12
= A 2 A 2 = , CCR2 CCR2

where we used the fact that A2 is negative. This zero can be a problem if the second-stage gain is too low, or if the compensation capacitance is too high, because the zero crowds the second pole. For frequencies where the zero becomes active, a 20dB/decade increase in slope of the gain is added, while the slope of the phase decreases by 45/decade. Both effects degrade the step response compared to the situation without the zero, because the phase and gain margins of the amplifier are not as good.

PSPICE examples
We can explore the above equations using PSPICE. The PSPICE version of Figure 1 is shown in Figure 4 below.

Create Date 4/16/06 by J R Brews

Page 3

4/17/2006

CF
+

{C_C}
R2
+

{A_v1}
+

R1 {R_1}
+

OUT_1

{A_v2}
E2
0
+ + -

OUT

E1
+ +
AC Sweep
+ -

E6
0
+ + -

C1 {C}

E3
+ + -

{R_2}
+

C2 {C}

VDB

V_AC 1V

GAIN = 1

GAIN = 1
0

GAIN = 1

GAIN = 1
0

STEP

{B_FB}

E5
+ -

E4
+ -

0
0

+ -

GAIN = 1

+ -

GAIN = 1
0

FIRST_NPAIRS = 0s,0 0.1us,0, 0.11us,1, 100,1 TSF = 1ms VSF = 1V/V

PARAMETERS:

T_1 = {10*T_2} T_2 = 1us C = 10uF A_v1 = {1Meg/A_v2} A_v2 = -100V/V

B_FB = 0 R_1 = {T_1/C} R_2 = {T_2/C}

C_C = {T_1/(1-A_v2)*R_1}

FIGURE 4
PSPICE version of Figure 1; the VCVSs of Figure 1 are implemented using a GAIN part (triangles) to allow the use of variables for gains A1 and A2; so each VCVS requires two PSPICE parts E and one GAIN part.

Figure 4 shows a PSPICE implementation of Figure 1. The parameter box allows sweeping of the value of A2 while keeping the overall gain A1A2 fixed. Also, the value of the compensation capacitor is taken from EQ. 10 to keep 1 fixed. By these arrangements, the gain plots all are similar when A2 is varies, making the effect of changing A2 easy to see.

Effects of varying the second-stage gain A2

200 (236.1K,87.3) 100 (Av2=-1V/V,318.3K,83.9) 0 (A_v2=-10V/V,17.5M,19.9) (2.23M,52.7) (23.0M,13.4)

(A_V2=-100 V/V,1.61G,-57.4) -100 1.0Hz VDB(OUT) Frequency 100Hz 10KHz 1.0MHz 100MHz 10GHz

FIGURE 5
Gain plot for open-loop amplifier with three second-stage gain values; gain at f180 is marked above the curves

Figure 5 shows how the zero encroaches on the gain plot as the second-stage gain diminishes, tending to reduce the gain margin of the amplifier compared to the case with only two poles and no zero, which resembles the high gain case out to about 100 MHz. The frequency f180 where the

Create Date 4/16/06 by J R Brews

Page 4

4/17/2006

phase flips is marked above the curves, determining the lowest values of 1/FB consistent with stability. Frequency f180 moves closer to the frequency of the zero as the gain goes down.
-0d (Av2=-10V/V,17.5M,-224.1) (2.23M,-180.0) -100d (A_v2=-100V/V,1.61G,-225.0) (23.0M,-180.0)

-200d

(236.1K,-180.0) (Av2=-1V/V,318.3K,-196.4)

-300d 1.0Hz

P(V(OUT))

100Hz

10KHz Frequency

1.0MHz

100MHz

10GHz

FIGURE 6
Phase plot for open-loop amplifier with three second-stage gain values

Figure 6 shows the phase of the open-loop amplifier with zero-frequencies from EQ. 12. At the highest gain (A2 = 100 V/V), the zero lies well above the second pole and hardly affects the phase of the amplifier, which resembles a two-pole system out to 100 MHz or so. At A2 = 1V/V, the second pole and the zero are closer in value, and the phase near the second pole is greatly affected by the zero. The frequencies f180 for a phase of 180 are marked.
80KV (A_v2=-1V/V,2.55u,50.8K)

40KV

0V (A_v2=-10V/V,1.85u,26.9K) B_FB=4.4E-5 V/V -40KV 0s V(OUT) 2us 4us Time 6us 8us 10us

FIGURE 7

Step response of closed loop amplifier with FB = 4.4 10-5 V/V, which is the maximum feedback consistent with stability for the case A2 = -1 V/V

Figure 7 shows the step response of the closed-loop amplifier. The value of FB is chosen using Figure 5, which shows the case A2 = 1 V/V has the strongest limitation on FB (requires the smallest amount of feedback to remain stable). Figure 7 shows that in this case the step response is very slow to settle (if it does at all), while the other cases with A2 = 10 V/V and 100 V/V reach a peak in 1.85 s and then remain constant. Summary When Miller compensation is used, a zero is introduced that can limit the design in some cases. An example with low second- stage gain illustrates these limitations.

Create Date 4/16/06 by J R Brews

Page 5

4/17/2006

Effects of varying CC
According to EQ. 9 and EQ. 10, as CC increases, the lower pole moves down and the higher pole moves up in frequency. Figure 8 shows the results for the case A2 = 100 V/V.

0 Phase (deg) -50 -100 -150 -200 -250 -300 1.E+00

FIGURE 8
Phase of open-loop amplifier for various values of compensation capacitance CC; A2 = 100 V/V

C_C=20nF C_C=6uF C_C=50uF

1.E+02

1.E+04 1.E+06 Frequency (Hz)

1.E+08

1.E+10

The position of the poles and the zero are marked in Figure 8. The lower pole moves down as CC increases, as expected. The zero also moves down, as shown by the heavily filled in dots on the curves, and in the case of CC = 50 F the zero is actually lower in frequency than the second pole. Even in the case CC = 6 F the zero has a big effect on the phase near the higher pole, and tends to make the amplifier less stable than when the zero is high in frequency. The higher pole moves up as CC increases, as expected, and the increase from CC = 20 nF to CC = 6 F is substantial. However, further increase in CC to 50 F does not increase the second pole frequency much at all, as expected from EQ. 11, which predicts a final value for this frequency that does not depend on CC when CC is large compared to C1//C2. Summary When Miller compensation is used, the upper pole frequency is increased, until CC reaches a value greater than C1//C2. For a given pole frequency ratio, a larger f2 allows a larger choice for the lower pole frequency f1 as well, leading to a faster amplifier for a given ratio f2/f1. A zero is introduced by CC that can limit the design in some cases. Several examples with large values of CC illustrate these limitations.

Comment: getting around the zero problem

In more advanced classes you will learn some other feedback compensation techniques that overcome the introduction of a zero, providing more flexible adjustment of the amplifier poles than Miller compensation.

Example design:
Given the open loop amplifier of Figure 1 with 1 = 10 s and 2 = 1 s, and A2 = -100 V/V, we want to build a closed loop amplifier with a step response corresponding to = 0.5 (that is, a "stable" design with slope 20 dB/decade from the new f1 all the way to f2. We specify a closedloop gain of 1000 V/V and use Miller compensation to get the fastest amplifier possible. Find the appropriate Miller compensation capacitor. We begin by finding the lowest pole frequency assuming the higher pole frequency doesnt move. The graphical approach (see document Feedback, Frequency Response and Step Response) is shown in Figure 9 below.

Create Date 4/16/06 by J R Brews

Page 6

4/17/2006

A 0

1 + FB A 0

A 0 1 1 + FB A 0 FB 1 + FB A 0

1
' 21

1 21

1 22

FIGURE 9 Determination of new pole position f1 = 1/( 21 ) We want 1 = (1+FBA0) 2 = (1 + 103 106) 1 s = 1 ms. According to EQ. 10, we want EQ. 13
C2R2 C1 R1 CC = 1 = 9.79 F. R2 + (1 A 2 )R1

According to EQ. 9, this value of CC will move the time constant of the higher pole to the value given in EQ. 14 below. EQ. 14
2 =

(CCC1 + C2C1 + C2CC ) R1R2 (CC + C2 ) R2 + (C1 + CC (1 A 2 )) R1

= 29.56 ns.

This movement of 2 will make the pole separation too big. We find 1 = (1+FBA0) 2 = (1 + 103 106) 29.56 ns = 29.6 s. The new 2 = 0.3504 s. We average the estimates of 2 and try again. We find after several iterations CC = 0.9728 F, 1 = 0.1094 ms, 2 = 0.10924 s. The gain and phase plots of the open-loop amplifier are shown in Figure 10 and Figure 11.
200 00,120.0) 100 (f_1=1.46KHz,117.0) (f_2=1.46MHz,57.0)

(f_Z=163.6MHz,-19.0) 0 (1/b_FB=60.0 dB)

-100 1.0Hz 10Hz VDB(OUT) dB(1E3)

100Hz

1.0KHz

10KHz

100KHz Frequency

1.0MHz

10MHz

100MHz

1.0GHz

10GHz

FIGURE 10
Gain plot for open-loop amplifier; pole frequencies from design are labeled

Create Date 4/16/06 by J R Brews

Page 7

4/17/2006

-0d

-100d

(f_1=1.46KHz,-45.0)

(f_2=1.46MHz,-135.5)

(f_Z=163.6MHz,-224.5) -200d

-300d 1.0Hz 10Hz P(V(OUT))

100Hz

1.0KHz

10KHz

100KHz Frequency

1.0MHz

10MHz

100MHz

1.0GHz

10GHz

FIGURE 11
Phase plot for open-loop amplifier; pole frequencies from design are labeled

Figure 10 and Figure 11 show that the open-loop amplifier with the chosen value for CC satisfies the requirements that (i) the pole separation is 1/2 = f2/f1 = (1+FBA0) = 1000, and (ii) the gain drops at 20 dB/decade all the way from the new f1 to the new f2, and (iii) the 1/FB line hits the open-loop gain plot at the new f2, making the open-loop phase at f2, (f2) = 135.
2.0KV (t_MAX=396.3ns,1.17KV) (1.19us,1.00KV) 1.0KV

0V

(t_MIN=791.3ns,971.3V)

-1.0KV

0s

V(OUT)

0.5us

1.0us

1.5us

2.0us

2.5us Time

3.0us

3.5us

4.0us

4.5us

5.0us

FIGURE 12
Step response of amplifier

Figure 12 shows the step response. After 1.2 s it has settled at the final value of gain 1000 V/V. The first maximum occurs at tMAX = 396 ns. The theoretical two-pole tMAX is (see document Feedback, Frequency Response and Step Response) EQ. 15
t MAX = N 1 2
1/ 2

1 1 2f2 1 4
1/ 2

= 396 ns,

showing that the open-loop zero has little effect on this design. This simple two-pole design gets us close enough to the design we want that we can use simulation to fine-tune it if needed.

Create Date 4/16/06 by J R Brews

Page 8

4/17/2006