Celoxica

RC1000-PP Hardware Reference Manual
Xilinx, XACTstep and M1 are trademarks of Xilinx Corp. Microsoft and MS-DOS are registered trademarks and Windows, Windows 95, Windows 98 and Windows NT are trademarks of Microsoft Corporation. This manual was written by Charles Sweeney and Bill Blyth
Celoxica Limited. All rights reserved Version 2.22
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Celoxica Ltd
Table of Contents
Conventions ............................................................................................................................. v
1. INTRODUCTION...................................................................................... 1-1
1.1 1.2 About This Manual...................................................................................................1-2 References................................................................................................................1-3
2. INSTALLATION ....................................................................................... 2-1 3. OVERVIEW.............................................................................................. 3-1 4. PCI INTERFACE...................................................................................... 4-1

4.1 4.2 Board Configuration ................................................................................................4-2 PLX PCI9080 Resources..........................................................................................4-4
4.3 Registers...................................................................................................................4-5 4.3.1 H_ARB Register Host Arbitration ...................................................................4-6 4.3.2 F_ARB Register FPGA Arbitration .................................................................4-8 4.3.3 F_CON Register FPGA Control .....................................................................4-9 4.3.4 F_STAT Register FPGA Status ...................................................................4-10 4.3.5 F_CFG Register FPGA Configuration..........................................................4-11 4.3.6 F_DAT Register FPGA Configuration Data .................................................4-13 4.3.7 F_CLK Register FPGA Programmable Clock ..............................................4-14 4.3.8 F_FCD Register FPGA Fast Configuration..................................................4-15 4.4 Reset Control .........................................................................................................4-16
5. FPGA CONTROL & STATUS.................................................................. 5-1

5.1 5.2 Control Register Port...............................................................................................5-3 Status Register Port ................................................................................................5-5
6. MEMORY BANKS & ARBITRATION ...................................................... 6-1

6.1 6.2 Memory Banks .........................................................................................................6-2 Memory Bank Arbitration ........................................................................................6-3
7. FPGA ....................................................................................................... 7-1

7.1 7.2 7.3 Configuration ...........................................................................................................7-3 Clock Source ............................................................................................................7-5 Power Supplies for BG560 Devices .......................................................................7-6
8. PMC SITES.............................................................................................. 8-1

iii
9. LEDS....................................................................................................... 9-1 10. POWER CONSUMPTION.................................................................... 10-1 11. JUMPERS............................................................................................ 11-1

11.1 11.2 11.3 FPGA Configuration Mode (JP1)......................................................................11-2 Clock Source (JP2) ............................................................................................11-3 Clock Source (JP3) ............................................................................................11-4
12. FPGA PIN CONNECTIONS................................................................. 12-1

12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 Functional Pin Groupings.................................................................................12-2 VDD Core Pins on 4000XV/Virtex .....................................................................12-3 Clocks .................................................................................................................12-4 PLX User I/O .......................................................................................................12-5 Configuration and Readback............................................................................12-6 Auxiliary I/O........................................................................................................12-7 Control and Status ............................................................................................12-9 LED Pins ...........................................................................................................12-10 SRAM Arbitration.............................................................................................12-11 SRAM Interfaces ..............................................................................................12-12
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Celoxica Ltd
Conventions
A number of conventions are used in this manual. These conventions are detailed below.
Warning Message. These messages warn you that actions may damage your hardware.
Handy Note. These messages draw your attention to crucial pieces of information.
Hexadecimal numbers appear in this document. They are prefixed with 0x. When describing the logic state of signals, the words HIGH and LOW are used for logic levels 1 and 0 respectively. Signals with names suffixed by _L are active-low.
vi
1. Introduction
1.1 About This Manual

Welcome to the RC1000-PP Hardware Reference Manual. The RC1000-PP is a PCI bus plug-in card for PCs. It has one large Xilinx FPGA with four banks of memory for data processing operations, and two PMC sites for I/O with the outside world. This manual describes the installation and setup of the board. It also contains all the information necessary to write host PC and FPGA programs for it. However, software host libraries and FPGA Handel-C macros are supplied with the board, and these should be adequate for most purposes. See the RC1000-PP Software User Guide (ref. [1]) and RC1000-PP Function Reference Manual (ref. [2]) for details of the RC1000-PP support software. The chapters in the manual are as follows. Chapter 1. Introduction, chapter summary, and references. Chapter 2. Installation of the board in a PC. Chapter 3. Brief overview of the board. Chapter 4. The PCI interface and the boards registers which are accessible from the host PC over the PCI bus. Chapter 5. The Control and Status Ports for byte-wide communication between the host PC and the FPGA. Chapter 6. Memory bank architecture and arbitration. Chapter 7. FPGA Configuration and Clock Sources. Chapter 8. PMC Sites. Chapter 9. LEDs. Chapter 10. Power consumption of the board. Chapter 11. Jumpers. Chapter 12. FPGA Pin Connections.
1-2
Introduction
1.2 References
The documents from Celoxica Ltd (including this one) are all available for download from the Celoxicas web site www.celoxica.com
[1] [2] [3] [4]
[5] [6] [7]
RC1000-PP Software User Guide v1.0. RC1000-PP Function Reference Manual v1.0. PCI9080 Data Sheet, PLX Technology. Refer to 9080_104.pdf at www.plxtech.com . ICD2061A Programmable Clock Generator. Cypress (was IC Designs). Refer to icd2061a.pdf at www.cypress.com . The Programmable Logic Data Book, Xilinx. Refer to databk98.pdf at www.xilinx.com. Xilinx XC4000XL Power Calculation, XCell Journal 27, Q1 98. www.xilinx.com/xcell/xl27/xl27_29.pdf A Simple Method of Estimating Power in XC4000XL/EX/E FPGAs Application Brief XBRF014, Xilinx, V1.0 (6/97). www.xilinx.com/xbrf/xbrf014.pdf
1-3
1-4
2. Installation
In order to ensure that the board operates correctly first time, please read these instructions completely before attempting installation. It will also help you to read the whole manual first so that you know how you want the board to be set up. Figure 1 shows the physical layout of the board. The installation instructions for your PC should be followed at all times. The RC1000-PP can be installed in any full length PCI slot that is keyed for a 5V I/O tolerant card. Both PCI bridge chips on the board conform to the PCI Version 2.1 and therefore operate correctly with PCI bus clocks from zero to 33MHz. The RC1000-PP can accommodate two PMC adapters and these should be fitted before installation.
Installation should ideally be done in an anti-static area. It is recommended that an earth strap be used when handling and installing the RC1000-PP. If an earth strap is not available then ensure that you make contact with earth before and during handling of the board, and only handle the board by its edges. Follow the installation instructions provided with your PC and ensure that the equipment is switched off. In the references to jumpers and headers in the following instructions, pin 1 is marked by a white arrow. For two-row headers, pins are numbered in a zigzag fashion as shown below.
A B C 1 3 5 2 4 6
2-2
Installation
J7 JTAG J6 FPGA LED Bank
J8 User I/O Clock Out Clock In JP2 JP3
JP4 SROM sockets
PMC #1 SIMM - SRAM Bank 3
PMC #2
Figure 1. Physical Layout 1. Fit any PMC modules that are required. If only one PMC module is to be fitted, either site can be used. PMC site #1 is positioned so that an I/O connector on the module aligns with the aperture in the RC1000-PP's edge panel. The PMC modules should be supplied with mounting kits, which normally include spacers, nuts, bolts and washers. Figure 2 shows the typical assembly of a PMC to the RC1000-PP. It is recommended that washers be used on both sides of the RC1000-PP to avoid damage to the PCB.
PMC
RC1000-PP
Figure 2. Assembly of a PMC to the RC1000-PP 2. Set the default FPGA configuration mode using JP1. The two possible default modes of configuration are Slave Serial and Master Serial. In Slave Serial mode, the two possible sources are the host computer via the PCI bus, and the Xilinx XChecker external download cable. In Master Serial
2-3
mode, the source is the on-board serial ROM. In the latter case, the SROM should have a valid configuration file programmed before allowing the FPGA to load it. The default mode is selected by connecting the pins of JP1 as shown in Table 1. JP1 pins connected 1-2 (default) 2-3 Configuration Mode Slave Serial Master Serial
Table 1. Default FPGA Configuration Mode Also, if the jumper is attached to pin 2 only (i.e. not connected), Slave Serial mode is selected.
The host program can override the mode setting using the F_CFG register to set Slave Serial mode or, in the case of Virtex, SelectMAP mode.
3. Set the FPGA Global Clock 2 (GCK2) source using JP2. The source can be either an external clock connected to SMB connector J10 "IN", or the MCLK output of the programmable clock generator. The clock source is selected by connecting the pins of JP2 as shown in Table 2. JP2 pins connected 1-2 2-3 (default) Clock Source External J10 "IN" Programmable MCLK
Table 2. GCK2 Clock Source 4. Set the FPGA Global Clock 3 (GCK3) source using JP3. The source can be either the VCLK output of the programmable clock generator, or the PCI9080 local bus clock (LCLK). The clock source is selected by connecting the pins of JP3 as shown in Table 3. JP3 pins connected 1-2 (default) 2-3 Clock Source Programmable VCLK PCI 9080 LCLK
Table 3. GCK3 Clock Source
2-4
Installation
VCLK can be replaced by a single-step clock controlled by the host program. See the F_CLK register. 5. With the PC switched off, plug the RC1000-PP into a full length PCI slot in the PC. Make sure the RC1000-PP is pushed firmly into the PCI slot and that the blue handle is in the guides located towards the front of the machine. Secure the boards back panel to the PC with the screw provided by the PC manufacturer. 6. Switch on the PC and follow the software installation instructions in ref [1].
The board ID in Version 2 boards and later versions is only set by software in the PLX EEPROM, see refs [1] and [2]. (In the version 1 board it could alternatively be set by a switch on the board.)
2-5
2-6
3. Overview
The RC1000-PP is a PCI bus plug-in card for PCs. It has one large Xilinx FPGA with four banks of memory for data processing operations, and two PMC sites for I/O with the outside world. Figure 3 shows the block diagram. 3.1 Memory
A standard complement of four memory banks of 2 MBytes each is provided. All four memory banks are accessible by both the FPGA and any device on the PCI bus. 3.2 Data Transfers
There are 3 methods of transferring data or communicating between the FPGA and any PCI device, via the PLX PCI9080 PCI controller chip. 1. Bulk data transfers between the FPGA and PCI bus are performed via the memory banks. Synchronisation between the FPGA and the other device is done using one of the other communication methods. Only PCI devices have access to the PLX registers, the FPGA does not. Hence only PCI devices can set up and initiate DMA transfers. 2. There are two unidirectional 8-bit ports, called control and status, for direct communications between the FPGA and PCI bus. Semaphores indicate when data has been written or read. 3. The PLX User I/O pins USERI and USERO are both connected to the FPGA to provide for single-bit communications. 3.3 Clocks
The FPGA has two of its pins connected to clocks. One pin is connected to either a programmable clock or an external clock, selectable by a jumper. The other pin is connected to either a programmable clock or the PCI9080 local bus clock, also selectable by a jumper. The latter programmable clock can be a single step clock driven by the host. The programmable clocks are programmed by the host PC, and have a frequency range of 400kHz to 100MHz. 3.4 FPGA
The RC1000-PP has a single site for a Xilinx FPGA in a BG560 package, examples of allowable devices being the 4085XL, 40150XV, Virtex V1000, and Virtex 2000E. Other footprintcompatible devices may be fitted as a factory option as and when they become available. Power supplies fitted on the
3-2
Overview
RC1000-PP allow installation in host computers that do not provide 3.3V power rails. The RC1000-PP FPGA can be programmed from the host PC over the PCI bus, or Xilinx XChecker download cable, or onboard serial ROM (SROM). For Virtex devices the fast SelectMAP mode configuration can be used. The internal state of the FPGA can be readback for debugging purposes either using the XChecker cable or over the PCI bus to the host. 3.5 PMC Sites
PMC modules are available from many third party suppliers. They provide a comprehensive range of I/O and processing functions to complement the RC1000-PP.
Secondary PCI PMC #1 PCI-PCI Bridge PMC #2
Host Primary PCI
PLX PCI9080 PCI Bridge SRAM BANK 512Kx32 SRAM BANK 512Kx32 SRAM BANK 512Kx32 Isolation SRAM BANK 512Kx32 +3v3/+2v5
Clocks & Control Xilinx BG560 e.g. 4085XL 40150XV V1000 V2000E V812E
Isolation
Linear Regulator
Auxiliary I/O Header
Figure 3. RC1000-PP Block Diagram
3-3
3-4
4. PCI Interface
4.1 Board Configuration

The RC1000-PP is a PCI Option Card with an on-board secondary bus. An Intel 21152 PCI-PCI bridge connects the host bus to the RC1000-PP PLX PCI9080 and PMC slots, and runs all of these devices at host-PC PCI speed. There are no switches or jumpers to configure for the PCI bus. The following information explains the allocation of resources and identification of devices by the host system. The PCI architecture defines the use of address lines to access devices during configuration cycles. Each device on a PCI bus has an IDSEL signal that is connected to an address line to provide a one-hot decode as shown in Figure 4.
Host PCI Bus
PCI-PCI bridge Secondary PCI Bus
PMC Slot 1 PMC Slot 2 PLX PCI9080
IDSEL=AD17 Device=1 IDSEL=AD18 Device=2 IDSEL=AD19 Device=3
RC1000-PP
Figure 4. IDSEL Device Decode Interrupts The interrupt structure of the RC1000-PP is arranged to meet the requirements of the PCI to PCI Bridge Specification as follows. The interrupt signals from each RC1000-PP PCI device are routed through a CPLD to the primary PCI bus according to the Boolean equations in Table 4. This ensures that the interrupt line of each agent (PMC slot 1 or 2 or PLX) is routed to the correct interrupt line on the host backplane. Most devices drive INTA but could use any of INTA-D.
Primary Interrupt INTA INTB INTC INTD = = = = PMC 1 INTD INTA INTB INTC OR OR OR OR PMC 2 INTC INTD INTA INTB OR INTA PLX
Table 4. Routing of Interrupts
4-2
PCI Interface
Configuration of the devices is performed by the host system, which maps interrupts according to Table 4. The CPLD that performs the interrupt routing is a JTAG programmable device and can be modified or updated if there are requirements to do so. The PLX can provide interrupts for all its own internal sources. In addition, the backend logic provides interrupts for the FPGA requesting access to the memory banks, the FPGA reading the control register, and the FPGA writing to the status register. Vendor and Device ID These IDs are stored in the PLX EEPROM. The Vendor ID is unique to the manufacturer, and the Device ID is unique to the board model .i.e. all RC1000-PPs have the same Vendor and Device IDs. The PCI Vendor ID is 0x4144 The PCI Device ID is 0x0020
4-3
4.2 PLX PCI9080 Resources

The PCI9080 requires resource allocation by the host PC to enable the areas of memory and I/O used for communication with the FPGA and supporting logic. The allocation of resources is controlled by the Base Address Registers (BARs) in the PCI9080 configuration space. See ref [3] for information on the PCI9080. The PCI9080 requests resources using BAR0 to BAR3 according to Table 5.
BAR 0 1 2 3 Function PCI9080 CSR PCI9080 CSR FPGA RAM Control Size 256 Bytes 256 Bytes 8 - 32 Mbytes 4 Kbytes Type Memory I/O Memory Memory Local Width n/a n/a 32 16
Table 5. Resource Allocation The PCI9080 will also request a single interrupt line. Registers The registers in the PCI9080 are accessible by the host only. Hence only the host can set up and initiate DMA transfers in either direction between the host and the board. See ref [3] for a definition of the chips registers. Local Bus The local bus of the PCI9080 provides a 32-bit non-multiplexed address and data bus with performance that matches the PCI bus to which it is attached. The local bus of the PCI9080 on the RC1000-PP is clocked at a fixed frequency of 33.33MHz derived from a 66.67MHz source. The higher frequency is used to generate timing in a CPLD for zero wait-state operation of the SRAM banks during host access.
4-4
PCI Interface
4.3 Registers
The registers mapped in by BAR3 are shown in Table 6. All are 16 bits wide and configured to run with zero local bus wait states, except for FPGA configuration.
Offset16 0 4 8 Name H_ARB F_ARB F_CON/ F_STAT C 10 14 18 F_CFG F_DAT F_CLK F_FCD Write Host Arbitration FPGA Arbitration FPGA General Purpose Control Register FPGA Configuration Control FPGA Configuration Data Programmable Clock Data Fast FPGA Configuration Data Read Host Arbitration FPGA Arbitration FPGA General Purpose Status Register FPGA Configuration Status N/A N/A Readback Data
Table 6. Registers In the following descriptions of registers: set means a value of 1, and reset or clear means a value of 0. W means Write R means Read Rst means the state after a board reset or power-up Clr means the state when the FPGA is not configured (cleared).
4-5
4.3.1 H_ARB Register Host Arbitration

15
W R R s t C l r CLR STAT 0 0
Arbitration for host access to the memory banks. Host interrupts, interrupt enables, & interrupt clears.
13 12
IA ARB INT ARB 0
14
IA ST INT ST 0
11
0 0 0
10
IE ST IE ST 0
9
IE CON IE CON 0
8
IE ARB IE ARB 0
7
0 GNT 3 1
6
0 GNT 2 1
5
0 GNT 1 1
4
0 GNT 0 1
3
REQ 3 REQ 3 0
2
REQ 2 REQ 2 0
1
REQ 1 REQ 1 0
0
REQ 0 REQ 0 0
IA CON INT CON 0
Each REQ bit is the state of the REQn line to the arbitration logic from the host indicating that access to a memory bank is requested. The GNTn status bits show which memory banks have been granted to the host. Note that the physical path to any bank is enabled only when both REQn and GNTn bits are true. On reset of the RC1000-PP board or downstream reset of the PLX, the H_ARB register defaults to all memory banks granted to the host and none requested. This ensures that the memory can be accessed by the host without the FPGA being configured. REQn GNTn r/w Set to request ownership of a bank. Clear to release control. r Set when ownership has been granted to the host by FPGA or on reset. Clear when ownership has been lost.
IE_ARB IE_CON IE_ST INT_ARB INT_CON INT_ST IA_ARB IA_CON
r/w Set to enable an interrupt when a bank has been granted. r/w Set to enable an interrupt when a control byte has been read by the FPGA. r/w Set to enable an interrupt when a status byte has been written by the FPGA. r r r Set when a bank has been granted with any of GNTn being set. Set when a control byte has been read by the FPGA. Set when a status byte has been written by the FPGA.
w1 Write with a 1 to clear the INT_ARB bit. w1 Write with a 1 to clear the INT_CON bit.
4-6
PCI Interface
IA_ST CLR_STAT
w1 Write with a 1 to clear the INT_ST bit and allow further status bytes to be written. w1 Write with a 1 to clear STA_VLD in F_STAT.
4-7
4.3.2 F_ARB Register FPGA Arbitration

15
R Rst Clr 0 0 0
State of arbitration for FPGA access to the memory banks.

13
0 0 0
14
0 0 0
12
0 0 0
11
0 0 0
10
0 0 0
9
0 0 0
8
0 0 0
7
GNT 3 0 0
6
GNT 2 0 0
5
GNT 1 0 0
4
GNT 0 0 0
3
REQ 3 F? 0
2
REQ 2 F? 0
1
REQ 1 F? 0
0
REQ 0 F? 0
The F_ARB register contains bits indicating the state of the REQn/GNTn bits between the memory bank arbitration logic and the FPGA. Upon reset, this register has all GNT bits cleared. The state of each REQn bit is determined by the bitstream loaded into the FPGA. The F? bit states on reset mean that their state is determined by the FPGA.
4-8
PCI Interface
4.3.3 F_CON Register FPGA Control

15
W Rst 0 0
Host to FPGA control data

13
0 0
14
0 0
12
0 0
11
0 0
10
0 0
9
0 0
8
0 0
Control Byte 0
The F_CON register is a write-only port for general-purpose control data from the host to the FPGA. The use of this register is application dependent. The CON_VLD bit in the F_CFG register is set automatically when F_CON is written and it is cleared when it is read by the FPGA. On reset, the F_CON register is reset to all zeroes.
4-9
4.3.4 F_STAT Register FPGA Status

15
R Rst Clr 0 0 0
FPGA to host status data. Control & status registers semaphores

13
0 0 0
14
0 0 0
12
0 0 0
11
0 0 0
10
0 0 0
9
CON VLD CON VLD CON VLD
8
STA VLD STA VLD STA VLD
Status Byte Determined by FPGA 0xFF
The F_STAT status register returns a single byte of information from the FPGA. The use of this information is application dependent. The STA_VLD bit is set when the status word is written by the FPGA and is cleared by the host reading F_STAT. STA_VLD CON_VLD r r Indicates that the status byte from the FPGA is valid. Cleared when the host toggles CLR_STAT in H_ARB to 1 and then 0. Indicates that the control byte to the FPGA is valid. Cleared when the FPGA reads the control byte.
4-10
PCI Interface
4.3.5 F_CFG Register FPGA Configuration

15
W R Rst Clr C3 C3 0 0
FPGA configuration control bits PMC cards present Card ID

13
C1 C1 0 0
14
C2 C2 0 0
12
C0 C0 0 0
11
0 PMC 2 0 0
10
0 PMC 1 0 0
9
0 0 0 0
8
0 0 0 0
7
RT RT 0 0
6
FST FST 0 FST
5
RST RST 0 RST
4
HST HST 0 HST
3
SLV MDE 0 MDE
2
0 DNE 0 0
1
INI INI 0 0
0
PRG PRG 0 PRG
The F_CFG register controls the loading of FPGA configuration bitstreams. All of the bits are true high with inverters used as appropriate on the control logic I/O pins. All of the status bits with the exception of HST reflect the actual state of the FPGA pins.
The logic for the download port from the host is disabled when not in use. The XChecker cable should not be left connected if host initiated downloads will be required.
PRG INI DNE SLV
w Assert to start an FPGA configuration clear cycle. r r r Indicates the state of FPGA PROG pin. Indicates the state of the FPGA INIT pin. Indicates the state of the FPGA DONE pin. w Allows the FPGA INIT pin to be asserted to delay configuration.
w Set this bit to force RC1000-PP to adopt serial download (SelectMAP for Virtex) from host. Clear to allow configuration mode to be determined by on-board jumper JP1. r Indicates current configuration mode set either by the on-board jumper JP1 or by SLV. MDE=1 indicates serial download whilst MDE=0 indicates on-board serial ROM.
MDE
HST
w Controls the activation of configuration signals to the FPGA. Setting this bit allows serial download to take place but only if MDE=1. With this bit clear, serial download may take place using the XCHECKER header. r Indicates the state of HST. w May be set to assert a dedicated reset signal to the FPGA. This signal is also shared by the XChecker header. The reset signal to the FPGA (FPGA_RST) is on pin AL4 and is active low. It is the
RST
4-11
inverse of RST. r FST RT PMC1 PMC2 C[3:0] Indicates the state of RST, the inverse of the reset signal to the FPGA. Indicates the state of FST. Indicates the state of RT. If set, indicates that a PCI compliant PMC has been fitted to PMC site 1. If set, indicates that a PCI compliant PMC has been fitted to PMC site 2.
w When set, the pseudo-parallel mode of FPGA download is used. r r r r w Set to initiate readback from an FPGA.
w Sets the readback length for the F_FCD register. Readback length is 16 minus the value of this register. Register value defaults to 0 on reset or after a read from F_FCD, indicating a readback length of 16. r Indicates the state of C[3:0].
4-12
PCI Interface
4.3.6 F_DAT Register FPGA Configuration Data

15
W 0
FPGA configuration data serial bitstream.

13
0
14
0
12
0
11
0
10
0
9
0
8
0
7
DAT
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Writing to this register will pass the data bit contained in bit 7 to the FPGA DIN pin accompanied by a CCLK load pulse. HST and MDE in the F_CFG register must both be set to allow the bit to be written. This can be used with all FPGA devices with the configuration mode set to Slave Serial. For faster download the F_FCD register should be used instead.
4-13
4.3.7 F_CLK Register FPGA Programmable Clock

15
W 0
Control of programmable clock generator Single-step clock

13
0
14
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
INT
2
FEA
1
DAT
0
CLK
The ICD2061 clock generator is written to via this register. Serial data streams are used to configure all of the registers in the ICD2061. The CLK and DAT bits can be used to generate the start/unlock sequence and Manchester encoding required by this device. The ICD2061 has a timeout of around 2 to 10ms, which will inhibit the input of data if allowed to expire. See ref [4] for details of how to program the chip. Utilities and libraries for programming the chip are supplied with the RC1000PP. The input reference clock is the on-board 66.67MHz clock divided down to 33.33MHz, which is also the PCI9080 local bus clock. The chip has two clock outputs, MCLK and VCLK. MCLK is connected to JP2, where either MCLK or the external clock from J10 is connected to FPGA global clock 2 (GCK2). VCLK is connected to JP3, where either VCLK or the PCI9080 local bus clock is connected to FPGA global clock 3 (GCK3). The INT bit, when set, selects the feature clock input of the ICD2061 and disables the programmable VCLK to the FPGA. Once INT is set, FEA may be toggled to provide a software controlled single-step clock to the FPGA, routed via VCLK.
4-14
PCI Interface
4.3.8 F_FCD Register FPGA Fast Configuration

15
W R
16-bit configuration data Readback

13 12 11 10 9 8 7 6 5 4 3 2 1 0
14
FPGA Configuration Data Bits 15:0 FPGA Readback Data 15:0
The F_FCD register allows 16 bits of configuration data to be written to the FPGA in one local bus transaction. The FPGA is written with bits in the following order :D7,D6D0,D15,D14D8. This matches the binary format of the Xilinx bit file and assumes a little-endian source word format. This can be used with all FPGA devices with the configuration mode set to Slave Serial, and is a faster method than using the F_DAT register. This register must be used for Virtex SelectMAP mode configuration. During readback, a read from this register returns the data from the FPGA with the first bit read in [15] and the last in [0]. With read lengths of less than 16 bits, the register will contain a value with the first bit read in bit[length-1] and the last bit in [0]. This is necessary because with non-Virtex devices, the bitstream is read in frames of fixed length per device, which varies between devices. To perform a readback, F_CFG[RT] must be set prior to the first read of F_FCD. Setting F_CFG[RT] triggers a readback process in the FPGA and the first read from F_FCD will contain the first 16 bits from the device. This word is constructed from 11 bits in [15:5] that should be ignored and 5 dummy bits in [4:0] which are actually from the device but can also be ignored. Subsequent reads will contain actual frame data from the device. The amount of bit data read must match the frame length in order to meet timing requirements for readback. Therefore the length count in F_CFG[C[3:0]] should be adjusted to match the number of bits required.
4-15
4.4 Reset Control

The PCI bus provides a reset signal originating in the host PC. This is passed through the bridge to the PMC slots and the PCI9080. The Boolean logic describing the reset topology on the RC1000-PP is shown below. For registers, the bit number is shown in square brackets. Figure 5 shows the different reset signals. S_PCIRST = P_PCIRST PCI9080_LRESET_OUT = S_PCIRST OR PCI9080_CNTRL[30] CPLD_RST = PCI9080_LRESET_OUT FPGA_RST = CPLD_RST OR F_CFG[5] OR XCHECKER_RST
Host PCI Bus P_PCIRST Secondary PCI Bus S_PCIRST PMC Slot 1 PMC Slot 2 PLX PCI9080 RC1000-PP Reset CPLD Control FPGA
PCI9080_LRESET_OUT
PCI-PCI bridge
FPGA_RST
Figure 5. Reset Signals Although it is possible to control the reset to the FPGA directly, the use of the supplied software library is advised as this will ensure that synchronisation and initialisation is performed correctly. The reset signal to the FPGA (FPGA_RST) is active low. It is the inverse of RST, bit 5 of the F_CFG register. If the F_CFG register is read, the value of RST is the register value and is therefore the inverse of the FPGA pin level.
4-16
PCI Interface
4-17
4-18
5. FPGA Control & Status
The RC1000-PP supports two ports between the host and the FPGA using two unidirectional 8-bit paths with handshaking signals. The Control register is for the host to send data to the FPGA, and the Status register is for the FPGA to send data to the host.
5-2
FPGA Control & Status
5.1 Control Register Port

The Control register is, from the host, an 8-bit register that can be written with command or other information. The action of loading this register drives the updated value directly onto FPGA pins and asserts CON_VLD in the F_STAT register. The signals are shown in Figure 6.
CPLD Q D[7:0]
CON_VLD_L CON_ACK_L
FPGA D
Figure 6. Control Register Signals

CON_VLD and CON_ACK are active low signals in the actual hardware connected to the FPGA pins.
The handshake sequence between the CPLD (host) and FPGA is a simple request and acknowledge type that can easily be implemented in the FPGA. The host CPLD will always follow this protocol as shown in Figure 7.
CON_VLD_L CON_ACK_L CON_INT IA_CON
Figure 7. Control Register Protocol CON_VLD_L is asserted when the control register in the CPLD is loaded with a new value and remains asserted until acknowledged. If a previous control register byte has not been accepted then the value will not be loaded. The FPGA must acknowledge receipt of the control byte by asserting CON_ACK_L which in turn sets CON_INT. CON_ACK_L needs to be asserted until CON_VLD_L is de-asserted. The assertion of CON_ACK_L will always cause CON_INT to be asserted.
5-3
The sequence is completed by the host detecting CON_INT, either by interrupts or by polling, and writing a 1 to IA_CON which in turn generates a synchronous 1 cycle (of the CPLD 33MHz clock) pulse. This will clear CON_VLD_L and allow the FPGA to release CON_ACK_L. It is recommended that the FPGA release CON_ACK on receipt of F_RST_L.
5-4
FPGA Control & Status
5.2 Status Register Port

The operation of the status port is similar to the control register but operates from the FPGA to the host via a CPLD. Figure 8 shows the signals. The state of STA_VLD can be read by the host in the F_CFG register.
CPLD D D[7:0]
STA_VLD_L STA_ACK_L
FPGA Q
Figure 8. Status Register Signals

STA_VLD and STA_ACK are active low signals in the actual hardware connected to the FPGA pins.
The status port handshake uses STA_VLD_L and STA_ACK_L to transfer the byte to the host. Each byte must be acknowledged before the next transfer can begin. The protocol is shown in Figure 9.
STAT_VLD_L STAT_ACK_L STAT_INT IA_ST
Figure 9. Status Register Protocol With the status port, the IA_ST signal is pulsed (30ns pulse with 33.33MHz CPLD clock) to acknowledge the transfer and clear the STA_INT signal. IA_ST is generated by writing a 1 to H_ARB[12] and is self-clearing. The STA_ACK signal remains asserted for one 30ns clock period after STA_VLD is cleared by the FPGA.
5-5
5-6
6. Memory Banks & Arbitration
6.1 Memory Banks

There are four memory banks, as shown in Figure 10. The FPGA has four 32-bit memory ports, one for each memory bank, and each bank has separate data, address and control signals. The FPGA can therefore access all four banks simultaneously and independently. All four banks also appear in the PCI address space, so they can be accessed by both the host and other PCI devices via the PCI9080 PCI bridge chip. The host support software allows the mapping of the memory into the virtual address space of a host application. Only one bank can be accessed at a time by the host or another PCI device. The arbitration between the FPGA and PCI9080 is controlled by onboard logic as described in the next section. Each bank is 2Mbytes of asynchronous SRAM, made up from four 512k x 8 memory chips - Cypress CY7C1049-17VC. The printed circuit board is designed for 2M x 8 chips as well, and these will be used as and when they become available.
6-2
Memory Banks & Arbitration
6.2 Memory Bank Arbitration

Architecture Each bank of SRAM on the RC1000-PP can be accessed by the host via the PLX PCI9080 or by the FPGA. The interface to each SRAM bank from both FPGA and PCI9080 is controlled using Quality Semiconductor QuickSwitches for maximum performance. The arrangement is shown in Figure 10.
FPGA
PLX
A,D,C
A,D,C x 4
SRAM Bank 0
SRAM Bank 1
SRAM Bank 2
SRAM Bank 3
A = address D = data C =control
Figure 10. Architecture of SRAM Banks The QuickSwitches work as four independent multiplexors, one per bank, to allow each bank to be accessed by one of the FPGA and the PCI9080 at a time, but never both. This arrangement minimises the risk of damage caused by contention if for any reason a poorly designed FPGA design is loaded. The QuickSwitches typically add 1ns of delay to address, data and control paths whilst maintaining zero wait state performance to the PCI bus. The arbitration logic is implemented in a CPLD that connects to the PCI9080 local bus and the FPGA. Any PCI device requests banks of memory via the H_ARB register, and the state of any arbitration by the FPGA is shown in the F_ARB register. The protocol is simple, so uses the minimum amount of logic on the FPGA. State Machine Figure 11 is the state machine for the CPLD arbitration logic. This controls the QuickSwitches for both the FPGA and the PCI9080.
6-3
The states HOST and FPGA enable the QuickSwitches for each device respectively.
TURN H2F REQF * /REQH 1 REQF + /REQH
reset
HOST
FPGA
1 REQH + /REQF TURN F2H
REQH * /REQF
Figure 11. Arbitration State Machine in CPLD By default, on reset, the CPLD assigns ownership of all SRAM banks to the PCI9080. This ensures that without an FPGA design loaded, the host can access the SRAM for testing. Arbitration To gain ownership of bank n, the FPGA must assert the REQn signal and wait for GNTn to be returned. At all times, the FPGA may drive address and control signals to each SRAM bank as the QuickSwitches ensure that contention is avoided. When GNTn is returned, the FPGA has ownership of the bank and may access it for as long as it needs to. When finished, REQn can be deasserted to allow the host via the PCI9080 to gain control but this will only happen if the host is asserting its REQn signal. Similarly when the host requests a bank using the H_ARB register, it must wait for the corresponding GNTn bit to be set before accessing the bank. It can either poll the H_ARB register or wait for an interrupt. The REQ and GNT signals between the FPGA and CPLD are active when asserted low. The section on the pinout of the FPGA details the signal names and pin allocations.
6-4
Memory Banks & Arbitration
The host can be interrupted when a bank is granted to it by using the interrupt INT_ARB, which is enabled in the H_ARB register.
6-5
6-6
7. FPGA
The standard RC1000-PP is fitted with a Xilinx XC40150XV-09BG560C. For a datasheet see ref [5]. Larger 4000XV devices and Virtex devices such as the V1000, V2000E, or V812E can also be fitted, and 4000XL devices such as the 4085XL can be fitted. The FPGA is connected to a number of resources including :Memory 4 banks of fast SRAM organised as 512kx32 bits with byte enable signals. Arbitration 4 sets of signals allow host and FPGA to arbitrate for ownership of each SRAM bank. Clocks 2 clock pins, possible sources are: 2 high speed programmable clocks, PCI9080 local clock, external clock, and single step clock from host. Data Ports 2 8-bit ports with handshake to host CPLD. User Signals 2 unidirectional single-bit signals connected directly to the PLX PCI9080. Auxiliary I/O 50 lines of series damped uncommitted I/O routed to a 64-way header.
7-2
FPGA
7.1 Configuration
The FPGA can be configured from 3 possible sources: 1. The host over the PCI bus using software utilities or libraries provided. 2. Any host PC using a Xilinx XChecker download cable. 3. The on-board serial ROM. The headers J6 and J7 enable both download and readback where supported by the download equipment. The connections to J6 and J7 are shown in Table 7. When using XChecker download, make sure jumper JP1 is fitted to pins 1-2. The position of JP1 does not matter for host-initiated download because the SLV bit in the F_CFG register overrides the jumper setting.
The XChecker cable must not be connected when configuring the FPGA from the host over the PCI bus.
Pin 1 2 3 4 5 6 7 8 9
J6 VCC GND POL F_CCLK F_DONE FPD0 (DIN) F_PROG_L F_INIT_L F_RST_L
J7 F_RT F_RD/XC95_TDO F_TRIG POL XC95_TDI XC95_TCK XC95_TMS N.C. N.C.
Table 7. XChecker and JTAG Connections

The XC95_* connections are for JTAG programming of the CPLDs. They should not be used.
The download connection, J6, is directly compatible with XChecker DLC4, the serial version, and is pinned to match its header. The DLC5 parallel version can also be used but has a different pinout.
7-3
FPGA Configuration Mode (JP1) This jumper sets the default configuration mode for the FPGA. 1-2 2-3 Slave Serial Mode Master Serial Mode
The FPGA configuration mode can be set by this link to enable a serial download from the host and external download cable or serially from the on-board serial ROM. In the latter case, the SROM should have a valid bitstream programmed before allowing the FPGA to load it. The serial ROM should be programmed in a suitable PROM programmer. If a Virtex device is fitted to the board the host can override the mode to be SelectMAP mode, and for other devices to Slave Serial mode.
7-4
FPGA
7.2 Clock Source

The FPGA has two clock inputs on global clock buffers GCK2 and GCK3. GCK2 is selected by JP2 to be connected to either the external clock (which could for example be driven by another RC1000-PP), or the MCLK output from the ICD2061 programmable clock. JP2 selects the clock source for GCK2 as in Table 8. JP2 pins connected 1-2 2-3 (default) Clock Source External J10 "IN" Programmable MCLK
Table 8. GCK2 Clock Source GCK3 is selected by JP3 to be connected to either the VCLK output from the ICD2061 programmable clock, or the PCI9080 local bus clock. VCLK can be setup to be a single step clock controlled by the host, see the F_CLK register description. JP3 selects the clock source for GCK3 as in Table 9. JP3 pins connected 1-2 (default) 2-3 Clock Source Programmable VCLK PCI 9080 LCLK
Table 9. GCK3 Clock Source The MCLK output from the ICD2061 programmable clock is the source for the external clock output J10 OUT. On revision 4 or greater PCB, the output on J9 is now 3.3V. On previous board revisions the output level is 5V.
7-5
7.3 Power Supplies for BG560 Devices

The BG560 site on the RC1000-PP has been designed to accommodate 4000XL, 4000XV and Virtex families. The 4000XL is a 3.3V device with 5V tolerant I/O. The 4000XV and Virtex require both 3.3V (I/O) and 2.5V (core) both of which are provided on the RC1000-PP and derived from the 5V rail. The VirtexE requires both 1.8V (core) and upto 3.3V (I/O) both of which are provided on the RC1000-PP and derived from the 5V rail. When a 4000XL is fitted, extra I/O pins are available compared to the 4000XV/Virtex but these should never be used as they correspond to the 2.5V core supply pins on the 4000XV/Virtex. Therefore, constraints files used for the 4000XL should always specify these blocks as prohibited from use.
7-6
FPGA
7-7
7-8
8. PMC Sites
The RC1000-PP is capable of supporting two 32-bit PMC modules. Each PMC site is completely compatible with the PCI specification and can be accessed from the host via the RC1000-PP PCI-PCI bridge or from the FPGA via the PCI9080. The power supply to each slot includes +5V, +3V3, +12V and -12V. The 5V, +12V and 12V are drawn from the host PCI connector. The 3V3 is generated on the RC1000-PP from the +5V supply. Appropriate interrupt signal combining is performed in a CPLD on the RC1000-PP to allow each PMC to have host interrupt support. See Table 4 on page 4-2.
8-2
PMC Sites
8-3
8-4
9. LEDs
The RC1000-PP has 8 LED indicators available for status and debugging mounted on the upper board edge, as shown in Figure 12. These can be viewed only with the PC cover removed. Each LED has a separate drive pin on the FPGA. To turn an LED on, the pin must be driven low. The diagram below illustrates the LED numbering.
1 3 5 7
0 2 4 6
RC1000-PP PCB (viewed from above)
Figure 12 LEDs
9-2
LEDs
9-3
9-4
10. Power Consumption
Using the component data sheets, the approximate maximum power consumption excluding the dynamic power consumption of the FPGA has been calculated to be 12W. The calculation is shown in Table 10. If typical current consumption for a component is not given in a data book then it is taken to be half the maximum current consumption. These figures include 33mW for quiescent power consumption of the FPGA. Dynamic power consumption of the FPGA varies enormously according to the applications clock rate and amount of logic used. This is explained in ref [5], [6] and [7].
Device 21152 PCI9080 SRAM 95144 9536 QuickSwitch ICD2061 FCT244 4000XV Power (mW) 600 325 7800 1600 250 1080 200 50 33 Qty 1 1 16 2 1 48 1 1 1 Icc typ (mA) 180 @3V3 65 97.5 160 50 4.5 40 10 10 @ 3V3
Table 10. Calculation of Power Consumption
10-2
Power Consumption
10-3
10-4
11. Jumpers
11.1 FPGA Configuration Mode (JP1)

This jumper sets the default configuration mode for the FPGA. 1-2 2-3 Slave Serial Mode Master Serial Mode
The FPGA configuration mode can be set by this link to enable a serial download from the host or external download cable (slave serial). Alternatively, the FPGA can be configured to load from onboard serial ROM (master serial). The mode can be overridden by the SLV bit in the F_CFG register. For Virtex devices the mode then becomes SelectMAP, for other devices the mode becomes Slave Serial.
11-2
Jumpers
11.2 Clock Source (JP2)

1-2 2-3 FPGA GCK2 provided by external clock on SMB connector J10 IN FPGA GCK2 provided by ICD2061 MCLK
11-3
11.3 Clock Source (JP3)

1-2 2-3 FPGA GCK3 provided by ICD2061 VCLK, which can be set up to be a single step clock from the host FPGA GCK3 provided by PCI9080 local clock (LCLK)
11-4
Jumpers
11.4 XChecker Voltage Selector (Revision 4 PCB Only)

1-2 2-3 +5V +3V3
This jumper routes either 3.3V or 5 Volts to the XChecker header. For programming the CPLDs either supply can be used but for downloading to VirtexE parts, 3.3 Volts should be used. This link can also be used to allow daughter cards to work of either voltage. For both voltages, a 1 Amp fuse will protect the card from damage
11-5
11-6
12. FPGA Pin Connections
12.1 Functional Pin Groupings
Auxiliary I/O
SRAM Bank 2 FPGA (BOTTOM VIEW OF DIE)
SRAM Bank 3
SRAM Bank 0
SRAM Bank 1
LEDs
User I/O
Control & Status Ports
Figure 13. Functional Pin Groupings The FPGA pins are grouped as shown in Figure 13. The following sections show the actual pin numbers. The above diagram can be used to plan the data flow in a design.
12-2
FPGA Pin Connections
12.2 VDD Core Pins on 4000XV/Virtex

The core logic on the 4000XV/Virtex operates at VCCINT=2.5V on the RC1000-PP. However, some versions of the RC1000-PP are fitted with 4000XL devices which do not use 2.5V and which have I/O pins instead of VCCINT pins.
These pins should NOT be used AT ALL in 4000XL designs and are listed below.
4000XL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin AD2 AD32 AK11 AK31 AK5 AM17 AN25 C17 C24 D6 E12 E30 J1 K32 T3 U32
4000XV/ Virtex VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
12-3
12.3 Clocks
These signals come from the dual programmable clock ICD2061, with GCK2 also selectable using JP2 for input from an external clock source on J10 IN, and GCK3 also selectable using JP3 for input from the PCI9080 local bus clock.
Global Clocks GCK2 GCK3
Pin XV AH29 AJ28
Pin Virtex D17 A17
Type I (BUFG) I (BUFG) Primary Clock Secondary Clock
12-4
12.4 PLX User I/O

These pins are available for general signaling requirements. See ref [3]. Library functions for accessing them are provided with the board. User Pins PLX_USERI PLX_USERO AJ10 AL9 Type O I
12-5
12.5 Configuration and Readback

The FPGA can be configured from a standard XChecker header or from the host PCI bus via on-board logic. The host only drives the configuration pins during download and tri-states them otherwise. The Mode1 and Mode0 pins are tied together and connected to signal F_MODE. This allows modes slave serial (111) or master serial (000) to be selected. The F_MODE signal is controlled by JP1 for slave or master mode. The state of JP1 can always be overridden by the host to enable slave serial download, or SelectMAP mode (110) in the case of Virtex devices. Configuration Mode2 Mode1 Mode0 F_DIN F_CCLK F_PROG_L F_RST_L F_INIT_L F_DONE AN32 AK30 AJ29 E4 C4 AM1 AL4 AJ17 AJ5 Type I O I I I/O I I I/O O from host Comment F_MODE, can be driven by CPLD F_MODE, can be driven by CPLD Driven by CPLD Also FPD0 (serial ROM) Depends on mode
The following pins are routed to the XChecker header J7 and can be used with the Xilinx hardware debugger readback for verification purposes. Readback F_TRIG F_RT F_RD AJ9 AN6 AL7 Type O I O - shared with XC95xx TDO
12-6
12.6 Auxiliary I/O

These pins drive JP8 via 27R series terminating resistors. The use of these pins is application dependent. Header pins that are not listed are connected to GND. These GND pins are numbered 1, 6, 11, 16, 21, 26, 31, 36, 41, 46, 51, 56, 61 and 64. PCB Revision 4 100R series terminating resistor are used instead of 27R The header is 64-way 2-row 0.1 pitch. The pin numbering zigzags along the header from pin 1, as described in the Installation section.
The drive capabilities and protection levels of these signals are in the care of the user.
Interboard I/O AUXIO0 AUXIO1 AUXIO2 AUXIO3 AUXIO4 AUXIO5 AUXIO6 AUXIO7 AUXIO8 AUXIO9 AUXIO10 AUXIO11 AUXIO12 AUXIO13 AUXIO14 AUXIO15 AUXIO16 AUXIO17 AUXIO18 C27 E25 A28 A27 D25 C26 E24 B26 C25 D24 B25 E23 A25 D23 B24 E22 C23 A23 D22
Header Pin (J8) 2 3 4 5 7 8 9 10 12 13 14 15 17 18 19 20 22 23 24
12-7
AUXIO19 AUXIO20 AUXIO21 AUXIO22 AUXIO23 AUXIO24 AUXIO25 AUXIO26 AUXIO27 AUXIO28 AUXIO29 AUXIO30 AUXIO31 AUXIO32 AUXIO33 AUXIO34 AUXIO35 AUXIO36 AUXIO37 AUXIO38 AUXIO39 AUXIO40 AUXIO41 AUXIO42 AUXIO43 AUXIO44 AUXIO45 AUXIO46 AUXIO47 AUXIO48 AUXIO49
D20 E21 B22 D21 C21 B21 E20 C20 B17 B16 D16 A15 C15 E15 C14 D14 A13 E14 C13 D13 D15 C12 E13 A11 D12 B11 B10 D11 C10 A9 E11
25 27 28 29 30 32 33 34 35 37 38 39 40 42 43 44 45 47 48 49 50 52 53 54 55 57 58 59 60 62 63
12-8
12.7 Control and Status

The host and FPGA can communicate with each other over unidirectional 8 bit ports, the Control and Status Ports. Each port has a VLD signal that is asserted when written with valid data. The acknowledgement of the control or status word is accomplished by pulsing the ACK signal in each case with the trailing edge being effective. The VLD and ACK signals are active low. FPGA Status Byte to Host FSTAT0 FSTAT1 FSTAT2 FSTAT3 FSTAT4 FSTAT5 FSTAT6 FSTAT7 FSTAT_VLD_L FSTAT_ACK_L Host Control Byte to FPGA FCTRL0 FCTRL1 FCTRL2 FCTRL3 FCTRL4 FCTRL5 FCTRL6 FCTRL7 FCTRL_VLD_L FCTRL_ACK_L AJ19 AM20 AK19 AL19 AN19 AJ18 AK18 AL18 AM18 AL20 AN17 AK16 AJ16 AL16 AM16 AL15 AK15 AJ15 AN15 AM14 Type O O O O O O O O O I Type I I I I I I I I I O
12-9
12.8 LED Pins

The 8 LEDs on the RC1000-PP are driven directly by the FPGA and require a low level on the FPGA pin to turn them on. LED LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 AN28 AK25 AL26 AJ24 AM27 AM26 AK24 AL25 Type O O O O O O O O D1.K1 D1.K2 D2.K1 D2.K2 D3.K1 D3.K2 D4.K1 D4.K2
12-10
12.9 SRAM Arbitration

Each SRAM bank can be owned by either the host or the FPGA. Initially, after reset, all banks are owned by the host. Ownership is requested for each bank by asserting REQn_L and waiting for GNTn_L to be returned. The ownership of a bank stays with the FPGA until relinquished by releasing REQn_L. All signals are active-low. SRAM Arbitration REQ0_L REQ1_L REQ2_L REQ3_L GNT0_L GNT1_L GNT2_L GNT3_L AM30 AM4 C29 C8 AM29 AJ7 B30 D9 Type O O O O I I I I
12-11
12.10 SRAM Interfaces

The four SRAM interfaces are identical in operation. Each has four chip select pins that can be used to break the read or write cycle into byte width operations. An output enable and write enable complete the interface along with 21 address pins and 32 data pins. CEn_L0 controls bits 0-7, CEn_L1 controls bits 8-15, and so on. All the control signals are active-low. 21 address lines are provided to allow for future 16Mbit SRAM devices. Current 4Mbit devices use only 19 address bits. The FPGA may drive all four SRAM buses simultaneously, including the time when an SRAM bank is owned by the host. QuickSwitch isolation buffers permit this to occur irrespective of bank ownership. No access to the actual SRAM will be enabled until ownership of the SRAM is with the FPGA. The SRAMs fitted to all banks are 17ns access, to permit zero waitstate operation through the PLX bridge.
12-12
SRAM Enables CE0_L0 CE0_L1 CE0_L2 CE0_L3 CE1_L0 CE1_L1 CE1_L2 CE1_L3 CE2_L0 CE2_L1 CE2_L2 CE2_L3 CE3_L0 CE3_L1 CE3_L2 CE3_L3 SRAM Control OE0_L OE1_L OE2_L OE3_L WE0_L WE1_L WE2_L WE3_L AK26 AL5 D27 B7 AJ25 AK6 C28 A6 AN31 AL29 AK27 AL28 AM6 AJ8 AL6 AK7 D29 C30 D28 A31 C9 D10 A8 B8
Type O O O O O O O O O O O O O O O O Type O O O O O O O O
12-13
SRAM 0 Address FA0_2 FA0_3 FA0_4 FA0_5 FA0_6 FA0_7 FA0_8 FA0_9 FA0_10 FA0_11 FA0_12 FA0_13 FA0_14 FA0_15 FA0_16 FA0_17 FA0_18 FA0_19 FA0_20 FA0_21 FA0_22 AJ30 AH30 AL33 AG29 AJ31 AK32 AG30 AH31 AF29 AJ32 AH32 AF30 AJ26 AE29 AH33 AG33 AE30 AF31 AD29 AM31 AN29
Type O O O O O O O O O O O O O O O O O O O O O
12-14
SRAM 1 Address FA1_2 FA1_3 FA1_4 FA1_5 FA1_6 FA1_7 FA1_8 FA1_9 FA1_10 FA1_11 FA1_12 FA1_13 FA1_14 FA1_15 FA1_16 FA1_17 FA1_18 FA1_19 FA1_20 FA1_21 FA1_22 AN7 AA4 AA3 Y5 AA1 Y4 Y3 AL8 W5 AK9 W3 W1 V3 V5 V4 V2 U2 U1 U4 AM9 AK10
12-15
SRAM 2 Address FA2_2 FA2_3 FA2_4 FA2_5 FA2_6 FA2_7 FA2_8 FA2_9 FA2_10 FA2_11 FA2_12 FA2_13 FA2_14 FA2_15 FA2_16 FA2_17 FA2_18 FA2_19 FA2_20 FA2_21 FA2_22 U31 T32 T30 T29 T31 R33 R31 R30 R29 P32 P31 D30 P30 P29 M32 N31 N30 L33 F29 E26 B29
12-16
SRAM 3 Address FA3_2 FA3_3 FA3_4 FA3_5 FA3_6 FA3_7 FA3_8 FA3_9 FA3_10 FA3_11 FA3_12 FA3_13 FA3_14 FA3_15 FA3_16 FA3_17 FA3_18 FA3_19 FA3_20 FA3_21 FA3_22 G1 F1 J5 G3 H4 F3 E2 H5 G4 D2 E3 G5 C1 F4 D3 B3 F5 E7 C5 B5 A5
12-17
SRAM 0 DATA FD0_0 FD0_1 FD0_2 FD0_3 FD0_4 FD0_5 FD0_6 FD0_7 FD0_8 FD0_9 FD0_10 FD0_11 FD0_12 FD0_13 FD0_14 FD0_15 FD0_16 FD0_17 FD0_18 FD0_19 FD0_20 FD0_21 FD0_22 FD0_23 FD0_24 FD0_25 FD0_26 FD0_27 FD0_28 FD0_29 FD0_30 FD0_31 AE31 AD30 AE32 AC29 AE33 AD31 AC30 AB29 AC31 AC33 AB30 AB31 AA29 AK28 AA30 AA31 AA32 Y29 AA33 Y30 AF32 Y32 W29 W30 W33 W31 V30 V29 V31 V32 U33 U29
Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
12-18
SRAM 1 DATA FD1_0 FD1_1 FD1_2 FD1_3 FD1_4 FD1_5 FD1_6 FD1_7 FD1_8 FD1_9 FD1_10 FD1_11 FD1_12 FD1_13 FD1_14 FD1_15 FD1_16 FD1_17 FD1_18 FD1_19 FD1_20 FD1_21 FD1_22 FD1_23 FD1_24 FD1_25 FD1_26 FD1_27 FD1_28 FD1_29 FD1_30 FD1_31 AN3 AK3 AH4 AL1 AG5 AJ3 AK2 AG4 AH3 AF5 AJ2 AF4 AJ1 AE5 AH1 AF3 AE4 AG2 AD5 AF2 AF1 AD4 AE3 AC5 AE1 AD3 AJ6 AA5 AC3 AB4 AC1 AB3
12-19
SRAM 2 DATA FD2_0 FD2_1 FD2_2 FD2_3 FD2_4 FD2_5 FD2_6 FD2_7 FD2_8 FD2_9 FD2_10 FD2_11 FD2_12 FD2_13 FD2_14 FD2_15 FD2_16 FD2_17 FD2_18 FD2_19 FD2_20 FD2_21 FD2_22 FD2_23 FD2_24 FD2_25 FD2_26 FD2_27 FD2_28 FD2_29 FD2_30 FD2_31 M31 L32 M30 L31 M29 J33 L30 K31 L29 H33 K30 J31 H32 K29 H31 J30 G32 F33 J29 G31 E28 E33 E32 H29 F31 G30 D32 E31 G29 C33 F30 D31
12-20
SRAM 3 DATA FD3_0 FD3_1 FD3_2 FD3_3 FD3_4 FD3_5 FD3_6 FD3_7 FD3_8 FD3_9 FD3_10 FD3_11 FD3_12 FD3_13 FD3_14 FD3_15 FD3_16 FD3_17 FD3_18 FD3_19 FD3_20 FD3_21 FD3_22 FD3_23 FD3_24 FD3_25 FD3_26 FD3_27 FD3_28 FD3_29 FD3_30 FD3_31 T2 T5 T4 R1 R3 R4 R5 P2 D7 P4 U3 P5 N2 N3 N4 M2 N5 M4 L1 L3 M5 K2 C6 E8 L5 J2 K4 J3 H2 K5 H3 J4
12-21

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RC1000-PP Hardware Reference Manual

RC1000-PP Hardware Reference Manual

Celoxica Limited. All rights reserved Version 2.22

5. FPGA CONTROL & STATUS.................................................................. 5-1

6. MEMORY BANKS & ARBITRATION ...................................................... 6-1

7. FPGA ....................................................................................................... 7-1

8. PMC SITES.............................................................................................. 8-1

RC1000-PP Hardware Reference Manual

12. FPGA PIN CONNECTIONS................................................................. 12-1

RC1000-PP Hardware Reference Manual

RC1000-PP Hardware Reference Manual

1.1 About This Manual

[1] [2] [3] [4]

[5] [6] [7]

RC1000-PP Hardware Reference Manual

RC1000-PP Hardware Reference Manual

J7 JTAG J6 FPGA LED Bank

J8 User I/O Clock Out Clock In JP2 JP3

JP4 SROM sockets

PMC #1 SIMM - SRAM Bank 3

RC1000-PP Hardware Reference Manual

Table 3. GCK3 Clock Source

RC1000-PP Hardware Reference Manual

RC1000-PP Hardware Reference Manual

Host Primary PCI

Auxiliary I/O Header

Figure 3. RC1000-PP Block Diagram

RC1000-PP Hardware Reference Manual

RC1000-PP Hardware Reference Manual

4.1 Board Configuration

PCI-PCI bridge Secondary PCI Bus

PMC Slot 1 PMC Slot 2 PLX PCI9080

IDSEL=AD17 Device=1 IDSEL=AD18 Device=2 IDSEL=AD19 Device=3

Table 4. Routing of Interrupts

RC1000-PP Hardware Reference Manual

4.2 PLX PCI9080 Resources

RC1000-PP Hardware Reference Manual

4.3.1 H_ARB Register Host Arbitration

IA CON INT CON 0

IE_ARB IE_CON IE_ST INT_ARB INT_CON INT_ST IA_ARB IA_CON

RC1000-PP Hardware Reference Manual

4.3.2 F_ARB Register FPGA Arbitration

State of arbitration for FPGA access to the memory banks.

4.3.3 F_CON Register FPGA Control

Host to FPGA control data

RC1000-PP Hardware Reference Manual

4.3.4 F_STAT Register FPGA Status

FPGA to host status data. Control & status registers semaphores

Status Byte Determined by FPGA 0xFF

4.3.5 F_CFG Register FPGA Configuration

FPGA configuration control bits PMC cards present Card ID

PRG INI DNE SLV

RC1000-PP Hardware Reference Manual

4.3.6 F_DAT Register FPGA Configuration Data

FPGA configuration data serial bitstream.

RC1000-PP Hardware Reference Manual

4.3.7 F_CLK Register FPGA Programmable Clock

Control of programmable clock generator Single-step clock

4.3.8 F_FCD Register FPGA Fast Configuration

16-bit configuration data Readback

FPGA Configuration Data Bits 15:0 FPGA Readback Data 15:0

RC1000-PP Hardware Reference Manual

4.4 Reset Control