CHAPTER 4 -

BIPOLAR JUNCTION TRANSISTOR

1980

1. Give reasons for the following (a) In a high junction transistor, the collector region has the highest resistivity and the emitter region has the lowest resistivity, the base region resistivity being in between. 2. Sketch the output V-I characteristics of an NPN transistor in common-emitter operation and indicate there on the different regions of importance. Explain how you would use these characteristics to determine hFE, ICBO and BVCBO of the transistor. 3. A silicon junction transistor operating at IE = 1 mA, VCE = 3V, has base-collector capacitory of 2 pf and base- emitter capacitance of 18pf. Determine the current gain bandwidth kT/q = 26mV at normal room temperature]

1981
1. Explain the following, with neat sketches wherever necessary: (a) Input and output V-I characteristics of a junction transistor. 2. Define the following terms relating to a bipolar transistor: (i) B VCEO (ii) fr (iii) Fmax (iv) Risc time (v) Storage time 3. A silicon n-p-n transistor with, hFE = 100 ICBO = 0.1 A. Calculate the IC for this transistor under following base circuit conditions: (i) IB = 0 (ii) IB = 20 A (iii) VBE = 0 (iv) VCB = 0. 4. Draw the Ebers Moll model for a bipolar transistor. And using this, show that the collector- emitter voltage drop of a saturated transistor is higher in the normal mode of operation than in the inverted mode of operation of the transistor. What is the practical use of this result?

1983
1. PROVE/ELABRATE the following: (i) Cut-off voltages of a silicon transistor and a germanium transistor.

2. For a small signal low frequency operation, write down v, I equations in terms of h parameters for common emitter (CE) configuration of a transistor. There from find out expressions for h parameters. 3. Draw an approximate h parameter model of a CE transistor configuration driven by voltage source R0 = 0, Ignore hre and hoe. Consider RL and RE as resistances in collector and emitter respectively.

4. The stability factor S for a transistor is defined as rate of change of collector current with respect to reverse saturation current. A CE configuration of a transistor utilizes self or emitter bias. Draw the circuit and derive the expression for the stability factor.

1984
1. The silicon transistor as connected in figure below has a minimum value of hFB of 30. +12V Ze E VA Is Z0 Q
100K

2K V0

12V

(a) If input voltage vi= 12 volts, show that the transistor is in Saturation. (b) If input voltage vi = 0.4 volt, show that the transistor is in cut-off. (c) For the case (b) find the maximum temperature at which the transistor remain just cut-off. Assume ICBO of 10 nano-amperes at 25 degrees Centigrade and doubles for every 10 degrees Centigrade rise in temperature.

1985
1. Draw the complete hybrid-vs equivalent circuit of a transistor and find an expression for the short-circuit current gain

1986
1. Sketch five different connections in which a bipolar junction transistor can be used as a diode. Determine the series resistance in each case, if the given transistor can be represented by the equivalent circuit shown in Fig. Q.2 (b). Which of these five connection has the lowest series resistance? Colloctor

rc Ic =Ib Ideal Transistor Actual Transistor

rb Base

Ib 2. The circuit shown in fig. 3(a) is known as a VBE multiplier, justify this by deriving an Emitter

expression for VA. Draw a sketch of VA versus I0. Identify clearly the regions in which Q is ON and Q is OFF. Q + VCC I

Ic = Ib R1 Q R2 Ib + VA -

3. In the circuit of Fig. 4(c), Q1 and Q2 are identical. Find I2 in the term of I0

+ Vcc R I0 I2 = 1b Q2 Ib

Q1

1987

1. Define the terms f , f and f as applied to a transistor and establish the relations between them 2. What do you mean by saturation of a transistor? In the circuit show in Fig. Q.2a, determine VDB to saturate the transistor. Assume VCE sat =0.1, Vgsat = 0.6V and hFE = 50 + 12 1 K 10 K

VBB

Fig. 2(a) 3. State and prove Millers theorem, Apply it to unilaterlize the hybrid equivalent circuit of a common emitter amplifier with a resistive load. State clearly the assumptions involved.

1988
1. Both emitter and collector junctions of a transistor are reverse biased by about 2 volts. Assume ICO (reverse saturation current of the collector-base diode) = 6 A, IEO(reverse saturation current of the emitter base diode) = 2 A, and (Emitter and collector currents). Note that I ICO = N IEO , where N and respectively, the common-base current gain under normal and reverse operations.

= 0.96 . Find IE and IC

are,

1989
1. You are given a transistor whose terminals are unmarked. State how you will determine if it is a pnp or npn transistor and identify all three terminals using only a multimeter. 2. An npn transistor with aN =0.98, ICO=2 a and IEO=1.6 a is used in a common emitter configuration with VCC = 12 and RC=4k. Find minimum base current required to saturate the transistor and the voltage across each junction. Neglect VVE(sat). 3. In the circuit shown, Q1 and Q2 are identical transistors with current gain and Q2 has current gain . Determine the relation between I2 and Io. ( IES-EC-89)(17Marks)

I0

R O3 Iz 1991

1. A transistor exhibits a change of 0.99 mA in its collector current for a change of 1.0mA O2 O in its emitter current.1 Calculate its common-base and common-emitter short-circuit

current gains.

1993
1. .A transistor used in the amplifier circuit show in Fig. 3(a) has the following hparameters: hie = 800 , hoe = 50 x 106 1 and hfe = 55. Calculate the voltage and power gains of circuit. Find also percentage error in the values obtained if hoe is neglected. -12v RL 20000 C1 R1 100K C2 R2 10K RZ

100K CE

1.

The parameters of a certain transistor are = 0.99 and ICBO = 100nA. while IB = 20 A. The transistor, connected in CE configuration, is in amplifying mode. Find ICEO, IC and IE. All symbols carry their usual meanings. For the circuit shown in fig 3(a), 1 = 0.98, 2 = 0.96 VCC = 24, RC = 120 and IE=100 mA. Calculate the current ICI IB1, IE1, IB2, IC2, IC the voltage VCE and the ratios IC/IB and IC/IE. Neglect reverse satuaration currents. VCC C IC RC

1995

1998

1.

IB = Q1 Q2

I C1
VCE

IE 1. Elucidate three consequences of the Early effect in bipolar junction transistors

2001

I C2

I E1

1.

Consider silicon n- -n transistors for the following circuit +12V 2K Vin

2004

IC1 100 1K

Vouty

2005
1. A bipolar transistor has two junctions either one of which may be forward or reverse biased, we have four mods of operations-normal, cut-off, saturation and iverse region. With the help of Ebers-moll equations model the transistor circuit with a single set of equations describing there four regions

1. Indicate whether the - value of a BJT increases or decreases with increase in the values of the following parameters: (i) base width. (ii) minority carrier lifetime in the base region. (iii) temperature. (iv) collector current. (v) collector voltage. 2. In the circuit shown in Fig. 2(c), what would be the minimum value of such that the transistor is in saturation? Assume VCE Sat = 0.2 V.

2007

+5V 1k + VBB Fig.2(c) 1. For the circuit shown in Fig. 1, assume = hFE = 100. Find if the transistor is in cutoff, saturation or in the active region. 0.1 mA 10 k

2009

-10 V 3K 7K 3V + Re V0

500

Fig.1

2010
1. Obtain Ebers-Moll equations for a p-n-p bipolar junction transistor. Show that these equations are true for any arbitrary geometry of the device.