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Advances in Bipolar Junction Transistor Modeling

Tianbing Chen and James Ma ProPlus Design Solutions Inc., San Jose, California, USA E-mail: tbchen@ProPlusSolution.com ABSTRACT This paper gives a brief overview on recent advances in bipolar junction transistor (BJT) modeling and related simulation applications in circuit design. This work starts with a review of existing BJT compact model formulations, and covers a broad range of advanced topics such as precision temperature modeling, sub-circuit design, mismatch and corner modeling, and BJT scalable model. 1. INTRODUCTION The Zig-zag development history of BJT in the past 60+ years was enriched with the enthusiastic research efforts by generations of the pioneer scientists and engineers. In the mean time, every revolutionary progress in processing technology has led to a leap of BJT performance. Figure 1 shows an example of the performance evolution of the Silicon-Germanium Hetero Junction Bipolar Transistor (SiGe HBT) of IBM BiCMOS technology in the last 20 years [1]. areas, e.g. device engineers, SPICE modeling engineers, foundry interfaces and circuit designers, to understand the key aspects of bipolar models, including the model selection choices, model performance and limitations, the model extraction strategy, and future direction in BJT modeling, etc. 2. OVERVIEW OF BJT MODELING 2.1 Model Formulation There are four active BJT models in the public domain now: Standard Gummel Poon (SGP) model, Vertical Bipolar Inter Company (VBIC) model, Most

Exquisite Transistor Model (Mextram), and High Current Model (HiCUM), with the last two models selected as the industrial standard BJT models.
SGP model was proposed by Gummel and Poon in 1970[2]. By introducing Integrated Charge Control Relations(ICCR), SGP model gives a very clear and standardized description of many effects such as early effect, high currentroll-off, and carrier transit time concept. Due to its simple yet physical model formulation, SGP model remained as the most popular BJT model until the middle 1990s. With the continued scaling of modern transistors, some second order effects that are not covered by SGP model, such as substrate network, self-heating effects and avalanche effects, become more and more important. Other advanced BJT models were introduced to cover these effects and provide more precise simulation results. In 1995, an US industry consortium proposed VBIC95 (now called VBIC) model. Compared to SGP model, VBIC model has a better implementation of early effect and also an improved capacitance model. It includes almost all the secondary effects such as quasi-saturation, weak avalanche effect, and self-heating etc. An additional substrate PNP is also included to simulate the dc/ac impact from substrate network. However, there have been scattered reports of the convergence issue with VBIC model when simulating large circuit. Mextram model was first developed internally in Philips by Graaff, Klostermann, and Jansen in 1986. It was put in public domain in 1994. Mextram includes the second effects such as self-heating, avalanche, and also a substrate network. Further more, Mextram model offers a physical description of collector epi-layer model, and also provides a good mathematic solution for dc/ac current crowding. Mextram introduces additional

Fig.1 SiGe HBT performance evolution of IBM BiCMOS technology

As BJT performance improves continuously with both vertical and lateral scaling, modern RF analogue design relies more and more heavily on accurate BJT model and its proper usage. For BJT SPICE modeling engineers, the model parametric extraction has to be kept as physical as possible, and sometimes sub-circuit in BJT model is needed to cover certain physics that are not covered by selected BJT model. For design engineers, a healthy balance between compute accuracy and efficiency has to be maintained during model selection to save design iterations and meet the stringent time-to-market need of company products. This paper is intended to help the end users in the BJT

978-1-4244-5798-4/10/$26.00 2010 IEEE

parameters to cover bandgap narrowing effect for HBTs. HiCUM model was developed by professor Schroter from University of Technology Dresden, Germany in late 1990s, targeting at RF analog applications. Unlike all the other BJT models that use artificial parameters such as VAF and VAR to descript ICCR, HiCUM model implements base charge directly into transfer current formulation. Hence it makes the parameter extraction more efficient yet more physical. Its low current transit time includes both early effect and extra transit time through junction space charge region. HiCUM provides a very good parameters extraction flow, with a matlab program TRADICA to help build bipolar scalable model. On top of all this, HiCUM provides an option for simplified level 0 model that offers fast simulation time yet more accurate simulation results than SGP model. 2.2 General Model Parameters Extraction Strategy Before the start of the actual model extraction, the spice modeling engineer needs to acquire sufficient process-specific information such as doping profile, epi thickness, junction overlap capacitance etc. First order calculation can offer a physical range of many model parameters and serves as a reasonable initial guess when direct parametric extraction is not available. Some cross sectional pictures of BJT will also help define the critical dimensions such as effective emitter area. This is even more important when defining a scaling rule. Then a Golden Die needs to be selected for on-wafer measurement for model extraction. The Si should represent the POR process of this processing technology. The actual parameters extraction starts with CV data and low-bias IV curves where BJT operate in the ideal region. Typically a direct calculation in commercial model extraction tools will give accurate simulation results. Then the terminal serial resistances need to be extracted. There are several special test methods such as RE flyback test have been designed to help the extraction. However, one needs to be aware of the test limitation, eg. resistance may see significant conductance modulation at large bias. Some special test structure can help the resistance extraction [3]. Then the high current parameters need to be extracted to simulate roll off at large current, self-heating effect, and emitter current crowding etc. This is one of the most difficult parts of the extraction in that at large bias a lot of second effects are coupling to each other. For example at a large VBE/VCE output curve, the RE voltage drop, self-heating effect, and avalanche effect are changing the curve shape simultaneously. When a simultaneous optimization of several parameters is inevitable, each parameter range need to be set within its physical meaning. For AC parameters, CV curve fitting will result in good ft fitting at low bias where the capacitance effect dominates. The low current transit time can be easily

decided from the peak ft value assuming the parametric resistance and capacitance parameters have been extracted. AC parameters that simulate RF performance at large current are more difficult to extract because all the BJT models have to use some empirical smoothing function to ensure good curve fitting at large bias. In general a good understanding of the model formulation is needed to calculate a reasonable initial guess value before further optimization. . For temperature modeling, the activation energy for junction saturation current, temperature coefficient (TC) of serial resistance etc need to be extracted. Typically curve fitting at three different temperatures at -50C, 27C, and 150C are required as the minimum. After all the model parameters have been extracted, the model needs to be simulated in actual SPICE environment to validate model and ensure high model qualities. This is so-called model quality assurance (QA) step. For some foundries, simulation on bench mark circuit performance versus on-Si data is also required for model QA. 3. SELECTED MODELING TOPICS During the past few years there have been several new BJT model developments to meet emerging application needs. The authors feel that the development efforts were mostly scattered, and this work tends to bring most of the advanced topics together and initiate future unified industrial collaborations. 3.1 Precision Temperature Modeling The Bandgap voltage reference (BGR) is an essential building block for many circuits, such as analogue-to-digital and digital-to-analogue converters, phase-locked loops, voltage regulators and so forth. BGR typically utilizes the linear dependence of BJT junction voltage on temperature at fixed current drive to realize a zero TC reference voltage. For a high precision BGR , the TC in the range of 1-5 ppm/C is often required. Thus any small error in the temperature modeling on BJT is not acceptable for a high precision BGR design. Obviously the regular three-temperature model parameter extraction will be insufficient for this purpose. Finer temperature steps need to be inserted to ensure better accuracy. Further more, BJT is biased at constant current drive in BGR, while for traditional model extraction setup BJT is swept at different voltages across temperature. This gap in bias setup adds to the simulation error. The last, but not the least important, is that the TC of BGR is decided by Vbe change over temperature. Not only the Vbe dependence at fixed current drive need to be simulated, the first derivative of Vbe over temperature should also be fitted.

3.2 Sub-circuit Implementation There are certain non-optimized BJT devices, such as lateral pnp transistors and some 3-terminal diodes (eg. ESD diode), cannot be well modeled by any BJT model due to the inherent parasitic effects. A sub-circuit is imperative in this case to ensure modeling accuracy. For example, for many CMOS technology a free lateral pnp transistor (means no additional mask cost) is available, typically used for BGR design. Fig. 2a) shows a typical cross sectional view of the lateral pnp transistors. Q1 and Q2 represent the main lateral pnp, while Q3 and Q5 are the parasitic vertical pnp from collector, and Q4 is the parasitic vertical pnp from emitter. A subcircuit was proposed by MacSweeney et. al. [4] to simulate the parasitic effect. The subcircuit is slightly changed and shown in Fig. 2b). Q4 shares base-emitter junction with the main transistor. So it is always turned on together with the main transistor. While Q3 and Q5 are always active when the main lateral pnp is biased at reverse mode or deep saturation. Given the fact that most cmos process do not have a buried layer, the parasitic effect from the vertical pnp are often quite significant and should be simulated. An improper design with an inaccurate lpnp model could easily trigger latch up issue.

both IC and IB variations can lead to variation. Either the IC or IB parameters can be adjusted in a corner model to simulate the same variation. Electrical test correlation study is therefore essential to ensure physics-based corner modeling. For example, for a certain process, we have the /IC/IB correlation in the following figure.

Figure 3 /IC/IB correlation for a BiCMOS process

Fig.2 Cross section and sub-circuit for a lateral pnp

3.3 Corner Modeling Process variation is unavoidable due to the variation of process parameters such as etching rate, photolithography misalignment, dopant fluctuation, and day-to-day operation status of foundry equipments etc. These process variations lead to device parameters variations. Device corner models are frequently used to simulate worst-case circuit performance in term of process variations. Typically several key bipolar parameters, such as , VA, fT, BVceo, are varied for bipolar corner models. Some of the parameters share the same physical background such that one cannot use arbitrary high/low combinations for corner modeling. For example, both and VA link to total base charge and a high + high VA corner model is meaningless, and vice versa. Another example is that both fT and BVceo link to collector epi doping and a high fT + high BVceo corner model is very unlikely. Different process parameter variations may induce very similar device parameter fluctuation. For example,

As we can see that IB varies by more than 0.5 orders of magnitude when varies from 100 to 300 while IC has a narrower variation of 0.15 orders of magnitude for the same data set. From the correlation study we conclude that variation is due to IB fluctuation. We need to adjust Ib parameters in the corner model. We cannot, however, assume for all process variation is caused by Ib variation. The correlation study needs to be performed for every corner model. 3.4 Mismatch Modeling The global process variation leads to BJT performance change from Lot to Lot, wafer to wafer, and die to die. It can be circumvented by certain circuit techniques such as the differentiated input of a current mirror where only intra-die parameter variation, which is often called mismatch, matters. Mismatch data are commonly measured by placing two devices of a particular geometry next to each other on a test chip [5]. Both devices are electrically probed and the mismatch is given as the differential performance measured either in absolute or in relative terms. The dispersion is estimated by the standard deviation. In order to minimize the mismatch induced by layout difference, typical BJT layout structure uses two closely spaced BJT surrounded by equally spaced BJT dummy devices and the metal routing is kept as symmetric as possible. The accuracy of a mismatch model will be seriously degraded without a well defined layout structure. Mismatch is also geometry-dependent, in general BJT mismatch improves for larger device. In order to improve BJT mismatch performance, most of the attention has been paid to BJT layout and geometry optimization in design. However, there has been limited discussion on the bias dependent mismatch

performance of BJT. Fig. 4 shows a symbolic mismatch performance for a BJT. In the ideal operation range (Vbe 0.4~0.8) IC/IB shows excellent matching since the terminal currents are mainly affected by emitter/base doping profile, which can be well controlled. In the low bias region the generation-recombination part of IB leads to large variation. At large bias the resistance and other secondary effects make the mismatch worse. It is very important that the circuit designer understand this and bias BJT in the right current level when mismatch matters most.
Figure 5 IIP3, noise figure, and gain as a function of emitter length and collector current

IS = ISS (W + W ) ( L + L)
where ISS is a constant and:/ are a function of W and L. It can be clearly seen from Fig. 6 that the scaling rule fits the target data quite well, which is well expected since the saturation current is physically proportional to effective emitter area.

Fig.4 Mismatch for a BJT device (not to scale)

3.5 Scalable Model Todays RF analogue product has very challenging performance requirements such as low power, low noise, and high linearity etc. The circuit output can be very sensitive to device selection. For example, in a low noise amplifier design the right emitter length and bias current have to be selected to balance IIP3, gain, and noise figure [6]. The actual design space is shown in Fig. 5. A BJT scalable model in this case can help a designer to locate the sweet spot of his or her design. For a model that is inherently scalable, for example BSIM3/4 model, it needs to have both W/L and : / as parameters. Furthermore, many other parameters such as resistance and capacitance are coded as a function of W and L. However, all the existing BJT model formulations do not support any geometric information, not to mention the geometry dependence of other parameters. In order to make a BJT model scalable, a scaling rule has to be defined [7-8]. The scaling rule consists of a full set of scaling equations for each of the BJT model parameters. Once the component definition format (CDF) parameters are identified from a circuit schematic inside the analysis command environment (ACE), all BJT model parameters are calculated based on the scaling rule. The model parameters can be directly passed to the netlist to enable the circuit simulation. For HiCUM model a commercial tool, TRADICA, is available to facilitate bipolar scaling. As an example of bipolar scaling, Fig. 6 shows the targeted IS parameter for BJT with different emitter geometries. A simple scaling rule for IS is defined as

Figure 6 Scaling rule for saturation current IS

4. SUMMARY The BJT model formulations and the general BJT model parameter extraction strategy are overviewed first. Then selected BJT modeling topics such as precision temperature modeling, sub-circuit design, corner and mismatch modeling, and scalable modeling are discussed. REFERENCES: [1] John Cressler, unpublished report [2] H,K.Gummel et.al. Bell Syst. Tech. J. p.827 1970. [3] M. Schroter, CEDIC Report, Oct. 2000 [4] D. MacSweeney et. al. IEEE TED p.1978 1998 [5] A. Hasting, The art of analog layout, Prentice Hall [6] Q. Liang, Ph.D Thesis, Georgia Tech. [7] TY Lee et.al, BCTM, 2001 p.171 [8] D.C. Sheridan et.al, BCTM 2004 p.132

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