Altera FLEX 8000 Block Diagram (Review)

Altera FLEX 10K Block Diagram (Review)

Figure from Altera technical literature

Figure from Altera technical literature

FLEX 8000 chip contains 26162 LABs

FLEX 10K chip contains 721520 LABs

Each LAB contains 8 Logic Elements (LEs), so a chip contains 2081296 LEs, totaling 2,50016,000 usable gates LABs arranged in rows and columns, connected by FastTrack Interconnect, with I/O elements (IOEs) at the edges
Spring 2002, Lecture 22 2

Each LAB contains 8 Logic Elements (LEs), so a chip contains 57612,160 LEs, totaling 10,000250,000 usable gates

Each chip also contains 320 Embedded Array Blocks (EABs), which can provide 6,16440,960 bits of RAM
Spring 2002, Lecture 22

Altera APEX 20K Overview

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APEX LABs and Interconnect

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APEX 20K chip contains:

Logic Array Block (LAB)

2563,456 LABs, each of which contains 10 Logic Elements (LEs), so a chip contains 2,56051,840 Les, 162,0002,391,552 usable gates 16216 Embedded System Blocks (EABs), each of which can provide 32,768442,368 bits of memory
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10 LEs Interleaved local interconnect (each LE connects to 2 local interconnect, each local interconnect connects to 10 LEs)
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Each LE can connect to 29 other Les through local interconnect

Can implement CAM, RAM, dual-port RAM, ROM, and FIFO

Logic Element (LE)

Organization:

4-input LUT, carry chain, cascade chain, same as FLEX devices Synchronous and asynchronous load and clear logic

MultiCore architecture, combining LUT, product-terms, & memory in one structure

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Designed for system on a chip

Interconnect

MegaLAB structures,each of which contains 16 LABs, one ESB, and a MegaLAB interconnect (for routing within the MegaLAB)
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MegaLAB interconnect between 16 LABs, etc. inside each MegaLAB FastTrack row and column interconnect between MegaLABs
Spring 2002, Lecture 22

ESB provides product terms or memory

Spring 2002, Lecture 22 4

APEX Embedded System Blocks (ESBs)

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Xilinx XC4000

Each ESB can act as a macrocell and provide product terms

Each ESB gets 32 inputs from local interconnect, from adjacent LAB or MegaLAB interconnect In this mode, each ESB contains 16 macrocells, and each macrocell contains 2 product terms and a programmable register (parallel expanders also provided)
Figure from Field-Programmable Gate Array Technology, Trimberger, Kluwer, 1994

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Based on LUTs and SRAM programming Xilinx XC4000 chip contains a matrix of Combinational Logic Blocks (CLBs)

Each ESB can also act as a memory block (dual-port RAM, ROM, FIFO, or CAM memory) configured in various sizes

Chips range from 10x10 to 56x56 CLBs Each CLB can be used for logic or RAM
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Inputs from adjacent local interconnect, which can be driven from MegaLAB or FastTrack interconnect Outputs to MegaLAB and FastTrack, some outputs to local interconnect

Used entirely as logic, a chip provides 3,00085,000 gates Used entirely as RAM,a chip provides 3,200100,352 bits of RAM With typical usage of 2030% RAM, a chip provides 2,00055,000 gates
Spring 2002, Lecture 22

Spring 2002, Lecture 22

Xilinx XC4000 Combinational Logic Block

Xilinx XC4000 CLB Carry Logic

Figure from Xilinx technical literature

Figure from Xilinx technical literature

Each Combinational Logic Block (CLB):

Fast carry logic provides carry and borrow signals

Two 4-input LUTs (called function generators F and G)

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Not shown on previous slide, this computation occurs between CLB inputs and F & G LUTs Results are propagated between CLBs Flexibility is limited in high-capacity XC4000X series to improve speed Allows high-speed address calculation, high-speed addition for DSP, etc.
Spring 2002, Lecture 22

A 3-input LUT, which has 13 of its inputs coming from outside the CLB CLB can implement two 4-variable functions, one 5-variable function, or some functions of up to 9 variables

Two edge-triggered D flip-flops

Spring 2002, Lecture 22 8

RAM
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Xilinx XC4000 I/O Block

LUTs can be treated as RAM cells Single-port operation

Configure as either one 16x2 or 32x1 bit array (both LUTs), two 16x1 bit arrays (both LUTs), or one 16x1 bit array (one LUT; use the other as logic) Each has a common read / write port Synchronous (edge-triggered) operation Asynchronous (level-triggered) operation
Figure from Xilinx technical literature

Dual-port operation

Configure as one 16x1 bit array, using both LUTs One write port, two read ports
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Two I/O Blocks (IOBs) are at the end of each row and column

Each IOB contains an input register / latch and an output register / latch Two inputs (to chip): direct & register The associated I/O pin can be used as either an input, output, or bidirectional pin
Spring 2002, Lecture 22

Supports simultaneous read and write operations to same or different addresses

Synchronous (edge-triggered) operation

Spring 2002, Lecture 22 10

Xilinx XC4000 Routing

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Xilinx XC4000 Routing (cont.) CLB inputs and outputs connect to channels on all four sides, to provide maximum routing flexibility Switch matrix connects rows and columns

Six transistors per switch point

CLBs connect to lines of various lengths:

Single-length lines enter a switch matrix every row / column Double-length lines enter a switch matrix every two rows / columns Longlines for high fanout, time-critical nets, or nets that need to be distributed over much of the chip XC4000X only:
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Figure from Xilinx technical literature

Three kinds of interconnect:

Row and column routing IOB routing, which forms a ring around the outside of the CLB array Dedicated networks, primarily intended for clocks, but usable for other signals
Spring 2002, Lecture 22 12

Quad- and octal-length lines Direct connections between adjacent CLBs

Spring 2002, Lecture 22

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Xilinx FPGAs
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XCS00/XL (Spartan)

High volume ASIC replacement 5v, 3v, 2,00040,000 typical gates

XC2S00 (Spartan-II)

High volume ASIC/ASSP replacement 2.5v, 6,000150,000 typical gates

XC4000XLA, XC4000XL, XC4000XV

High density 3v, 1,500500,000 typical gates

XCV00 (Virtex)

High density / performance 2.5v, 34,0001,124,000 typical gates

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Spring 2002, Lecture 22