12-Latches and Flip Flops 2

Latches and Flip-Flops
Introduction to sequential logic Latches

SR Latch Gated SR Latch Gated D Latch
Flip-Flops

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JK Flip-flop D Flip-flop T Flip-flop JK Master-Slave Flip-flop Preset and Clear functions 7474 and 7476 devices
A.A.H Ab-Rahman, Z.Md-Yusof 1
Flip-Flop
Mostly used sequential circuit blocks for temporary storage (memory) For Flip-flops, output changes state only at a specified triggering input called clock (clk) For a latch, output changes state at a specified trigger level (high or low)
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A.A.H Ab-Rahman, Z.Md-Yusof
Flip-Flop (cont.)
D Latch vs D Flip Flop
Positive level triggered D Latch/ Gated D Latch
D En Q Q
Positive edge triggered D Flip-flop

D Q Q
Positive edge triggered D clk Q 1 0 0 1 x x 0

Symbol for clk Q 0 1 Q Q Q Q 1 0 Q Q Q

3
D En 0 1 1 1
Q 0 1
x 0
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x 1
Flip-Flop (cont.)
Negative level triggered D Latch
D En Q Q
Negative edge triggered D Flip-flop

D Q Q
Negative edge triggered D En Q Q
D clk
0 1
Q
0 1
Q
1 0
0 0
1 0 x 1
0
1 Q
1
0 Q
x
x 0 x 1
Q
Q Q
Q
Q Q
4
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Flip-flop (cont.)
Draw the output waveform for the positive and negative edge triggered D flip-flops
clk
D Q (+ve Flip-flop)
Q (-ve Flip-flop)
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Flip-Flop (cont.)
How to design flip-flops? Recall the Gated D Latch
D Q
For Gated D Latch, Q <= D when En = 1
En Q
For D Flip-flop, Q <= D when En =
We need a pulse transition detector for a D Flip-flop, in order To detect

2/18/2012 A.A.H Ab-Rahman, Z.Md-Yusof 6
Flip-Flop (cont.)
Pulse transition detector
clk pulse
Circuit diagram
clk
Waveform
pulse
Pulse transition detector Block diagram

clk PTD pulse
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D Flip-flop
D Q
clk
PTD Q
A positive edge of clk results in a short pulse at output of PTD, therefore, causes Q <= D only at that instant (pulse duration) Q is maintained until the next positive edge of clk
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SR Flip-flop
Recall the problem with SR Flip-flop
S
Sx
clk
PTD Q
Rx
When S = 1 and R = 1, the outputs are invalid (both Q and Q equal to 1) To overcome this problem, Q and Q is fed back to the Gated NANDs which now becomes the JK Flip-flop Sx and Rx can never be equal to 0 at same time
JK Flip-flop
J Q
J K clk 0 0
Q Q
Q Q
clk
PTD Q K
0 1
1 0 1 1 x x -
0
1 Q Q
1
0 Q Q
When J = 1 and K = 1, Q and Q toggles When J = 0 and K = 0, Q and Q maintains When J = 0 and K = 1, Q = 0 (Reset) When J = 1 and K = 0, Q = 1 (Set)
D Flip-flop
We can also construct a D Flip-flop from JK Flip-flop by shorting J and K with an inverter
D Q
D clk
clk PTD Q
Q 0 1 Q
Q 1 0 Q
0 1 x -
Q <= D when clk = Else Q <= Q

T Flip-flop
Another type of flip-flop, the T Flip-flop can be constructed from the JK flip flop by shorting J and K inputs
T Q
T clk 0 1
Q Q Q Q
Q Q Q Q
clk
PTD Q
x -
Q <= Q when T = 1 and clk = Else Q <= Q

T Flip-flop (cont.)
Draw the output waveform for the positive edge triggered T Flip-flop
clk
T Q
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13
JK Master Slave Flip-Flop

Jms
J Q Q K
Qn
Q Q
Qms
Qn
Qms
K
Kms
Master
Slave
Master latches data at positive edge of clk Slave latches data at negative edge of clk Qms is therefore valid on the negative edge of clk
JK Master Slave Flip-flop (cont.)

Draw the output for JK Flip-flop and the JK Master Slave Flip-flop (MS-JK)
clk
J K
Q (JK Flip-flop) Q (MS-JK Flip-flop)
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Flip-flop Extra Features

Positive edge triggered D Flip-flop with active high Input Enable
2x1 Mux
D1 F D0 S
Q Q
Q Q
En clk If En = 1 Q <= D when clk = Else Q <= Q

En
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Flip-flop Extra Features (cont.)

Positive Edge Triggered D Flip-flop with active low clear and active low preset functions
4x1 Mux
D clk
When 0, Q <= 1
Q
Q Q
1 0 1
F D3 D2 D1 D0 S1 S0
CLR PRE
PRE D Q Q CLR
When 0, Q <= 0 CLR PRE clk

Q
The D Flip-flop only functions when CLR = 1 and PRE = 1
4x1 Mux
0 1
F D3 D2 D1 D0 S1 S0
0
0 1
0
1 0
x
x x
1
0 1
1
1 0
D
17
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PRE CLR A.A.H Ab-Rahman, Z.Md-Yusof
Flip-flop Extra Features (cont.)

Putting all together Positive Edge Triggered D Flip-flop with active high enable, active low preset and active low clear
PRE D Q Q En CLR
How to force Q <= 0? En = x, clk = x, CLR = 0, PRE = 1 How to set Q <= Q at positive edge of clk? En = 0, clk = , CLR = 1, PRE = 1
A.A.H Ab-Rahman, Z.Md-Yusof 18
What is the input condition that Q <= D? En = 1, clk = , CLR = 1, PRE = 1 How to force Q <= 1? En = x, clk = x, CLR = 1, PRE = 0
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Flip-flop IC
The 7474 Dual Positive Edge Triggered D Flipflop with preset, clear, and complementary outputs The 7476 Dual Master-Slave JK Flip-flops with clear, preset and complementary outputs
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12-Latches and Flip Flops 2

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Latches and Flip-Flops

Introduction to sequential logic Latches

A.A.H Ab-Rahman, Z.Md-Yusof

Positive edge triggered D Flip-flop

Positive edge triggered D clk Q 1 0 0 1 x x 0

Symbol for clk Q 0 1 Q Q Q Q 1 0 Q Q Q

Negative edge triggered D Flip-flop

Negative edge triggered D En Q Q

A.A.H Ab-Rahman, Z.Md-Yusof

A.A.H Ab-Rahman, Z.Md-Yusof

For Gated D Latch, Q <= D when En = 1

For D Flip-flop, Q <= D when En =

We need a pulse transition detector for a D Flip-flop, in order To detect

Pulse transition detector Block diagram

A.A.H Ab-Rahman, Z.Md-Yusof

A.A.H Ab-Rahman, Z.Md-Yusof

Q <= D when clk = Else Q <= Q

Q <= Q when T = 1 and clk = Else Q <= Q

A.A.H Ab-Rahman, Z.Md-Yusof

JK Master Slave Flip-Flop

JK Master Slave Flip-flop (cont.)

Q (JK Flip-flop) Q (MS-JK Flip-flop)

A.A.H Ab-Rahman, Z.Md-Yusof

Flip-flop Extra Features

En clk If En = 1 Q <= D when clk = Else Q <= Q

Flip-flop Extra Features (cont.)

When 0, Q <= 0 CLR PRE clk

The D Flip-flop only functions when CLR = 1 and PRE = 1

PRE CLR A.A.H Ab-Rahman, Z.Md-Yusof

Flip-flop Extra Features (cont.)

A.A.H Ab-Rahman, Z.Md-Yusof

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