White Paper on Silicon Nanowire Transistors (SNWT)

ABSTRACT
Recently, silicon (Si) nanowire transistors (SNWTs) have attracted increasing interests as one of the most promising structures to extend the device scaling down to the end of technology roadmap due to its excellent gate control capability, improved transport property, and device design flexibility. This new method of fabricating high-performance gate-all around silicon (Si) nanowire transistors (SNWTs) based on fully Si bulk (FSB) substrate is proposed and demonstrated by both simulation and experiments in this paper. Due to the large fan-out and deep junction of Si source/drain (S/D) region connecting with the bulk substrate, the FSB SNWTs can effectively alleviate the self-heating effects with technology scaling. Thermal behavior of multi-wire SNWTs is investigated and FSB SNWTs show superior self-heating immunity to SNWTs based on Si-on-insulator (SOI) substrate (SOI SNWTs). In addition, the bottom parasitic transistor can be well suppressed in this structure. Although FSB SNWTs have larger gate parasitic capacitance, the CV/I is found to be comparable to the SOI SNWTs. With self-aligned, fully epi-free compatible CMOS processes, this new architecture was successfully fabricated, which exhibit high ONOFF current ratio of 2.6 108 due to better heat dissipation and low S/D resistance realized in this structure.

INTRODUCTION

Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated (VLSI) circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite sub-threshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness (tox) must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin. Also the various considerations like a large fan-out to reduce the self-heating effects associated with the current drivability of the micro devices has posed a tight constraint on the scalability and high packing density of transistors on a single wafer die. All such constraints have limited the number of transistors that can be accommodated on a single wafer die and thus have caused the technology development to lag the Moores Law and thus the Moores law had to be modified to make it more realistic with respect to the current technological progress. Alternative device structures based on Nanowire technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications. Partially depleted (PD) SOI was the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (UTBFD) SOI and the SNWT (Silicon Nanowire Transistor) device structures promise to bridge the gap in the technological progress for a few more years until we develop carbon based semiconductor devices.

Fig 1.1 Typical SiNW-FET The proposed technology is shown to overcome almost all the demerits of the current CMOS process technology and help in reducing the size of the circuit on a single silicon wafer die thus increasing the packing density and at the same time prevent other malicious and parasitic effects from affecting the performance of the transistor. This report will focus on the briefing of the entire paper and a few of the reference papers. The brief report will include the identification of the problems currently being faced by the existing CMOS technology, then each problem will be dealt with and a solution for solving the same will be decided; this later will be followed by integrating all these solution to a single SNWT device and the working and other parametric capabilities will be discovered through the various simulations and at the end the report will have the detailed fabrication method of the proposed SNWT model. This report will also include a short introduction of the Nanowire Theory and its applications in modern day technology and also it is to be noted that this report (paper) is dealing with the 45nm process technology and lesser.

CURRENT TECHNOLOGY

In the modern days, the technologies like TTL, CMOS, BiCMOS, GaAs, InP and HEMT dominate the world in different areas of the engineering. The 32nm process of transistor fabrication is the smallest implemented and various companies like Intel and AMD have patented and theoretically realized 22nm and 15nm processes for future fabrication; the further decrease in size has a lot considerations that need to be taken into account and reducing the width of the gate of a MOS transistor has its own detrimental effects on the performance of the device.

Fig 2.1 32nm MOSFET The different detrimental effects and parasitic effects that affect the device due to the reduction in the gate width along with other considerations are listed and explained below: 1. Self-Heating As the size of the transistor goes on reducing, the dimensions of the channel also drastically reduce, since the resistance in the channel is inversely proportional to the cross sectional area of the channel itself, the resistance increases to a level that the current flowing in the channel causes
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I2RT (heat) to build up in the channel, this heat must be removed from the channel efficiently by providing a sufficiently large heat sink (substrate), if heat sink is not sufficient then it leads to the self-heating phenomenon which causes a thermal runaway since it is a chain reaction.

Fig 2.2 Self Heating Phenomenon 2. Limited Current Drivability In small sized transistors have a small heat sink or the ones that have almost no path for the removal of the built up heat in the channel; in such cases to avoid a thermal runaway caused by Self-Heating, the drain to source current (Ids) is limited up to a certain value such that the heat generated is less than the heat dissipated in the device.

3. Increased Leakage Current Reducing the dimension of the transistors also results in the down scaling of the Gate and SiO2 (Silicon Dioxide) Thick Oxide layer thickness, this leads to a lack of control over the drift currents flowing in the channel which contribute to the leakage current (Ioff) between the drain and source giving rise to random noise in many of the electronic applications. This cannot be suppressed by any external means and totally depends up on the device fabrication technique.

4. Ion / Ioff Ratio Decrease The Increase in the leakage current (Ioff) on one side due to scenario no. 3 and decrease in the (Ids) on the other side due to scenario no. 2 causes the Ion/Ioff ratio to reduce considerably causing severe device performance degeneration. For an ideal device the ratio of Ion/Ioff should be infinity, for practical cases the higher the ratio the better is the device performance. Typically this ratio is very large and is in the order of 1x107.

5. Threshold Voltage Fault As the size of the Thick oxide layer decreases along with the size of the gate, the threshold voltage will also have to be less so as to prevent the polysilicon on top of the thickox layer from fusing due to the excessive electric field across the gate caused by applying the threshold voltage VT. Hence the flexibility of setting the application specific threshold voltage is not available and also the value of the VT is not compatible with CMOS or TTL logic families.

Fig 2.3 Various Gate Junctions

SILICON NANOWIRE TECHNOLOGY

Basics of Nanowires A nanowire is a nanostructure, with the diameter of the order of a nanometer (109 meters). Alternatively, nanowires can be defined as structures that have a thickness or diameter constrained to tens of nanometers or less and an unconstrained length. At these scales, quantum mechanical effects are important which coined the term "quantum wires". Many different types of nanowires exist, including metallic (e.g., Ni, Pt, Au), semiconducting (e.g., Si, InP, GaN, etc.), and insulating (e.g., SiO2, TiO2).Molecular nanowires are composed of repeating molecular units either organic. Typical nanowires exhibit aspect ratios (length-to-width ratio) of 1000 or more. As such they are often referred to as one-dimensional (1-D) materials. Nanowires have many interesting properties that are not seen in bulk or 3-D materials. This is because electrons in nanowires are quantum confined laterally and thus occupy energy levels that are different from the traditional continuum of energy levels or bands found in bulk materials.

Nanowire Fabrication Techniques There are two main techniques used to synthesize nanowires: chemical vapor deposition and patterned chemical etching. In chemical vapor deposition, nanowires are synthesized by flowing chemical precursor vapors into the hot zone of a furnace to react on a substrate, often with the assistance of a metal catalyst nanoparticle. The precursor vapors are then transported to the substrate with an inert carrier gas often combined with other reactant gases along the way. The substrate is placed in the deposition of the furnace, where chemical decomposition is favorable. Multiple mechanisms then promote nanowire growth instead of thin-film deposition. The most common mechanism for this is the vapor-liquid-solid mechanism. This mechanism uses a metal catalyst that forms a liquid-solid hybrid with the desired nanowire material. Upon chemical decomposition and dissolution into the liquid eutectic droplet, the solution becomes supersaturated and overcomes the nucleation barrier to begin precipitation.
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Patterned chemical etching is a top-down or hybrid top-down/bottom-up approach. First n-type silicon is dipped into a silica bead solution to form the patterned substrate. Then patterned substrate is dissolved with a directional, substrate-selective etch such as deep reactive-ion etching or metal-assisted chemical etching to begin to form nanowires. Then the silica beads are removed in hydrofluoric acid and diffusion dope to form radial p-n junctions.

Fig 3.1 SiNW Fabrication Technique 1

Fig 3.2 SiNW Fabrication Technique 2

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Application of Nanowires To create active electronic elements, the first key step was to chemically dope a semiconductor nanowire. This has already been done to individual nanowires to create p-type and n-type semiconductors. The next step was to find a way to create a p-n junction, one of the simplest electronic devices. This was achieved in two ways. The first way was to physically cross a p-type wire over an n-type wire. The second method involved chemically doping a single wire with different dopants along the length. This method created a p-n junction with only one wire. After p-n junctions were built with nanowires, the next logical step was to build logic gates. By connecting several p-n junctions together, researchers have been able to create the basis of all logic circuits: the AND, OR, and NOT gates have all been built from semiconductor nanowire crossings. In August 2012, researchers reported constructing the first NAND gate from undoped silicon nanowires. This avoids the problem of how to achieve precision doping of complementary Nano circuits, which is unsolved. They were able to control the Schottky barrier to achieve low-resistance contacts by placing a silicide layer in the metal-silicon interface. It is possible that semiconductor nanowire crossings will be important to the future of digital computing. Though there are other uses for nanowires beyond these, the only ones that actually take advantage of physics in the nanometer regime are electronic. Conducting nanowires offer the possibility of connecting molecular-scale entities in a molecular computer. Dispersions of conducting nanowires in different polymers are being investigated for use as transparent electrodes for flexible flat-screen displays.

PROPOSED MODEL
Fig 4.1(a) shows the schematic view of FSB SNWT proposed in this study from the birds eye, and Fig 4.1(b) & (c) shows the cross-sectional views of the FSB SNWTs and the SOI SNWTs, respectively. It can be seen that comparing with SOI SNWTs, the large fan-out and deep junction of S/D connecting with the bulk substrate can be achieved in FSB SNWTs without epitaxial process, which are beneficial to improve the carrier transport characteristics of SNWTs, since the self-heating effects can be greatly deceased.

Fig 4.1 Cross Section and Top View of the SiNWFET

Extensive 3-D device simulation is performed using Sentaurus Device simulation tools. Hydrodynamic model and density gradient quantum correction are used and carefully calibrated, as suggested. This method has been verified by full quantum mechanical models and Monte Carlo simulations, and thus can well qualitatively predict the main trend in SNWTs. The
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calibrated result is presented in Fig. 4.2, with the nonequilibrium Greens function (NEGF) result as a comparison. Fig 4.3(a) & (b) shows the electron density distribution in the cross section of Si nanowires at bias VgsVth = 0.1 V and VgsVth = 0.4 V, respectively. It is shown that the calibrated model can reproduce the volume inversion in thin body devices as well as the terminal current properties.

Fig 4.2 Drain Characteristics of SiNWFET

Fig 4.3 Electron Density in the SiNW In order to simulate the electrothermal effects in SNWTs, heat flow equations are calculated and coupled with the electrical equations to account for the temperature distribution
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and the heat transport. It is known that the thermal conductivity in thin-film Si severely degrades; leading to increased self-heating effects in ultrathin-body (UTB) SOI devices. It is expected that the self-heating effects may be more distinct in nanowire transistors due to the ultra-narrow channel surrounded by the oxide dielectrics. Due to the lack of experimental data of 1-D thermal conductivity in Si nanowires, the values of 2-D thermal conductivity in thin-film Si are adopted in the simulator. The heat generated in the channel transport along the Si nanowire and through the surroundings ultimately dissipates into the substrate heat sink. Other terminals such as the gate and source/drain contacts can also act as the heat dissipation paths, whose thermal behavior can be treated as layout-dependent lumped thermal resistances. Considering that these terminals are buried under thick interconnects and dielectrics in real applications and the silicide have lower thermal conductivity than bulk Si, for simplicity, they are assumed to be adiabatic, and the main heat dissipation path is the substrate heat sink in the simulation. It is worth mentioning that the metal gate surrounding the Si nanowire acts as an additional path for the heat generated in the channel to transport towards the substrate heat sink. This heat conduction path is taken into account for both in the FSB SNWTs and SOI SNWTs in the simulation. It is also worth noting that nonequilibrium phonon population and nondiffusive heat transport occur in ultra-scaled SNWTs. However, accurate calculations are much more complicated and time consuming. In this paper, the simplified method based on the classical heat flow equations with modified parameters is computationally efficient and can qualitatively simulate the heat dissipation and temperature distribution in SNWTs. In this report, simulations are focused on 45-nm technology node and beyond. Metal gate with adjustable work function is used in the simulation. The device parameters and bias conditions are chosen according to the high-performance logic technology requirements.

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FABRICATION & PERFORMANCE OF SiNW-FET

Fig. 5.1 shows the fabrication process flow, which is compatible with CMOS technology and does not need Epitaxy process.

Fig 5.1 Fabrication Steps of SiNW-FET After local oxidation of silicon (LOCOS) isolation, 100 nm Si3N4 is deposited and defined by e-beam lithography as the hard mask, which is used to protect the underlying Si fin from following S/D doping and gate trench etching [inductively coupled plasma (ICP)]. Then, high-dose arsenic S/D implantation is performed at 00 tilt angle, as shown in Fig. 5.1(a). After SiO2 deposition and e-beam lithography to define the gate trench region, the oxide over the fin region is removed, but the oxide on the S/D regions still remains. After that, ICP etching is
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carried out using Si3N4 hard-mask to form the Si fin and simultaneously the wide fan-out S/D regions as shown in Fig. 5.1(b). Then, the nitride spacer was formed to protect the fin channel from the following isotropic Si etching in the bottom gate region. The Si fin in Fig. 5.1(c) is hidden behind the nitride spacer and invisible as a consequence. ICP etching is carried out to expose the region beneath the channel and the subsequent isotropic Si etching is used to remove this Si region under the channel. Then, the bridge-like channel is formed connected with the S/D region, as shown in Fig. 5.1(c). The highdose boron (5x1014 cm2) implantation was performed to suppress the BPT. It is noted that the channel region is protected by Si3N4 hard-mask, and thus remained undoped during the substrate implantation. In addition, better isolation of bottom gate can be achieved owing to the thicker oxide film grown in the high doping concentration region in the following oxidation. After the Si3N4 hard-mask removal, as shown in Fig. 5.1(d), wet oxidation at 9500 C and following BHF etching are used to thin the Si channel, as shown in Fig. 5.1(e). Then, 5-nm gate oxide is grown and poly-Si is deposited to fill the gate trench in self-aligned manner. High-dose arsenic implantation is performed followed by poly-Si gate patterning and 10500 C rapid thermal processing (RTP), as shown in Fig. 5.1(f). Finally, back-end steps including contact etching, metal deposition, and metal patterning are performed to complete the process.

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Fig 5.2 Scanning Electron Microscope (SEM) Images of the Channel Fig. 5.2(a) and (b) shows the tilted top view and the cross-sectional SEM images of the 130-nm-long SNWT with 10 nm diameter after poly-Si deposition without the sacrificial oxide removal, respectively. High-resolution TEM image of the cross section is shown in Fig. 5.2(c). The cross-sectional images show that the 10-nm SNWT is completely surrounded by oxide and poly-Si that can offer better gate-control capability and more device design flexibility. The large fan-out and deep junction of source/drain region can be achieved to decrease the parasitic resistance in our work. Since the source/drain regions connect with the bulk substrate, the heat can be spread quickly throughout the substrate and self-heating effects can be effectively suppressed. In addition, multiwire transistors for high-performance applications can also be obtained in this study, as shown in the insert of Fig. 5.2(a).

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Fig 5.3 Transfer Characteristics of SiNW-FET

Fig 5.4 Output Characteristics of SiNW-FET Figs. 5.3 and 5.4 show the measured IdsVgs and IdsVds characteristics of n+ polygate SNW n-MOSFET with single wire, respectively. Despite of the 5-nm gate oxide, 1.04 mA/m driving currents and 12 fA/m leakage current of n-SNWT are achieved. The measured draininduced barrier lowering (DIBL) effect and sub threshold swing are 4 mV/V and 74 mV/dec, respectively, mainly resulting from the excellent gate control capability and immunity of parasitic transistor.

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Although the SNWTs are fabricated with relatively thick gate oxide, the measured results show the excellent short channel effects (SCEs) immunity and the highest ION/IOFF ratio of 2.6 108.

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ADVANTAGES OF SiNW-FET
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Negligible Leakage Current (Ioff) Large On Current Capability No Self-Heating Effect through proper fabrication method Compatible with conventional CMOS and TTL logics Very Large Ion/Ioff Ratio Huge Transconductance and Amplification Factor Small Size (up to 4nm has been theoretically implemented) Faster Switching No short channel effect No Bulk Effect No Pinch off Large Packing Density One Transistor NAND Gate Implementation:

Fig 6.1 Typical Dual Gate SiNW-FET The model shown above in fig 6.1 can be used as a single transistor AND gate, which otherwise requires 3 to 4 transistors in the conventional CMOS logic, this AND gate model can be transformed into a universal NAND gate by reversing the dopants from N-type to P-type. Thus any circuit can be implemented from these NAND gates which utilize only a single FET

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therefore reducing the size of the circuit by almost 75% while also achieving better operational parameters.

CONCLUSION

In this paper, new structure of SNWTs on fully Si bulk substrate (FSB SNWT) is proposed, computationally studied, and successfully demonstrated by epi-free compatible CMOS processes. The FSB SNWTs exhibit superior self-heating immunity with technology downscaling due to their large fan-out S/D regions connecting with bulk Si substrate. Selfheating effects in multiwire SNWTs are investigated and found to be greatly alleviated in FSB SNWTs compared to those fabricated on SOI wafers. With an additional optimized substrate implantation, the BPT can be well suppressed. It is indicated that the speed characteristics are not severely degraded in spite of larger gate parasitic capacitance in bulk-based SNWTs. With epifree fully compatible CMOS technology, high-performance FSB SNWTs have been realized. The measured results show the highest ION/IOFF ratio of 2.6 108, mainly resulting from better heat dissipation and low S/D resistance in this structure. Due to the excellent gate-control capability and immunity of BPT, a sub-threshold swing of 74 mV/dec and a DIBL of 4 mV/V are achieved.

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REFERENCES

1. Jing Zhuge, Yu Tian, Runsheng Wang, Ru Huang, Yiqun Wang, Baoqin Chen, Jia Liu, Xing Zhang and Yangyuan Wang. High-Performance Si Nanowire Transistors on Fully Si Bulk Substrate From Top-Down Approach: Simulation and Fabrication, IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 9, NO. 1, JANUARY 2010. 2. C.H.Wann, H. Noda, T. Tanaka, M.Yoshida and C. Hu, A comparative study of advanced MOSFET concepts , IEEE Trans. Electron Devices, vol. 43, no. 10, pp 17421753, Oct. 1996. 3. www.wikipedia.org/Nanowires 4. www.berkeley.edu NAND gate. 5. www.stanford.edu - For Articles related to FETs and SiNW-FET - For Nanowires

- For Articles related to Silicon Nanowires and Single Transistor

6. Scott Waterson Silicon Nanowires in Solar Cells, Pennsylvania State University, White Paper, 2012. 7. http://www.southalabama.edu/engineering/ece/faculty/akhan/Courses/Nanotechnology%20summer05/nanowires_presentation.pdf

8. N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance, in IEDM Tech. Dig., 2006, pp. 547550.

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