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Conten ts
1. Introduction 2. Fabrication Process Flow - Basic Steps 2.3. The CMOS n-Well Process 4. Advanced CMOS Fabrication Technologies Twin-Tub (Twin-Well) CMOS Process Silicon-on-Insulator (SOI) CMOS Process
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Figure-1: Simplified process sequence for fabrication of the n-well CMOS integrated circuit with a single polysilicon layer, showing only major fabrication steps. The simplified process sequence for the fabrication of CMOS integrated circuits on a p - type silicon substrate is shown in Fig.1. The process starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate. Then, a thick oxide is grown in the regions surrounding the nMOS and pMOS active regions. The thin gate oxide is subsequently grown on the surface through thermal oxidation. These steps are followed by the creation of n+ and p+ regions (source, drain and channel-stop interconnects). implants) and by final metallization (creation of metal
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2. Fabrication Process Flow - Basic Steps Note that each processing step requires that certain areas are polysilicon,
defined on chip by appropriate masks. Consequently, the integrated circuit may be viewed as a set of patterned layers of doped silicon, metal and insulating silicon dioxide. In general, a layer must be patterned before the next layer of material is applied on chip. The process used to transfer a pattern to a layer on the chip is called lithography. Since each layer has its own distinct patterning requirements, the lithographic sequence must be repeated for every layer, using a different mask.
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thickness, for example, is created on the substrate (Fig. 2(b)). The entire oxide surface is then covered with a layer of photoresist, which is essentially a light -sensitive, acid- resistant developing solution (Fig. organic polymer, initially insoluble in the 2(c)). If the photoresist material is exposed to
ultraviolet (UV) light, the exposed areas become soluble so that they are no longer resistant to etching solvents. To selectively expose the photoresist, we have to cover some of the areas on the surface with a mask during exposure. Thus, when the structure with the mask on top is exposed to UV light, areas which are covered by the opaque features on the mask are shielded. In the areas where the UV light can pass through, on the other hand, the photoresist is exposed and becomes soluble (Fig. 2(d)).
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Figure-2: Process steps required for patterning of silicon dioxide. The type of photoresist which is initially insoluble and becomes soluble after exposure to UV light is called positive photoresist. The process sequence shown in Fig. 2 uses positive photoresist. after exposure to UV light, called There is another If type of photoresist which is initially soluble and becomes insoluble (hardened) negative photoresist. negative photoresist is used in the photolithography process, the areas which are not shielded from the UV light by the opaque mask features become insoluble, whereas the shielded areas can subsequently be etched away by a developing solution. Negative photoresists are more sensitive to light, but their photolithographic resolution is not as high as that of the positive photoresists. Therefore, negative photoresists are used less commonly in the manufacturing of high-density integrated circuits.
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the interconnects and the MOS transistor gates (Fig. 4(f)). The
thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed (Fig. 4(g)). The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implantation (in this case with donor atoms to produce n-type doping). Figure 4(h) shows that the doping penetrates the exposed areas on the silicon surface, ultimately creating two n-type regions (source and drain junctions) in the p-type substrate. The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity. Note that the polysilicon gate, which is patterned before doping actually defines the precise location of the channel region and, hence, the location of the source and the drain regions. Since this procedure allows very precise positioning of the two regions relative to the gate, it is also called the selfaligned process.
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doped (with
cm-3) p-type silicon substrate. Then, an initial oxide layer is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. Once the n-well is created, the active areas of the nMOS and pMOS transistors can be defined. Figures 5 through 10 illustrate the significant milestones that occur during the fabrication process of a CMOS inverter.
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Figure-5: Following the creation of the n-well region, a thick field oxide is grown in the areas surrounding the transistor active regions, and a thin gate oxide is grown on top of the active regions. The thickness and the quality of the gate oxide are two of the most critical fabrication parameters, since they strongly affect the operational characteristics of the MOS transistor, as well as its long-term reliability.
Figure-6:
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The
polysilicon
layer
is
deposited
using
chemical
vapor
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Figure-7: Using a set of two masks, the n+ and p+ regions are implanted into the substrate and into the n- well, respectively. Also, the ohmic contacts to the substrate and to the n-well are implanted in this process step.
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Figure-9: surface
Metal using
(aluminum)
is
deposited
over
the
entire
chip
through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability.
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metal interconnections. The final step is to deposit the passivation layer (for protection) over the chip, except for wire-bonding pad areas.
CMOS
Fabrication
two
examples
will
be
given
for
advanced
CMOS
processes which offer additional benefits in terms of device performance and integration density. These processes, namely, the twin-tub CMOS process and the silicon-on-insulator (SOI) process, are becoming especially more popular for sub-micron geometries where device performance and density must be pushed beyond the limits of the conventional n-well CMOS process.
Twin-Tub Process
(Twin-Well)
CMOS
This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the pwell are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant optimized to produce the desired concentrations can be carefully device characteristics.
In the conventional n-well CMOS process, the doping density of the well region is typically about one order of magnitude higher than the
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Figure-11: Cross-section of nMOS and pMOS transistors in twin-tub CMOS process. Silicon-on-Insulator (SOI) CMOS Process Rather than using silicon as the substrate material, technologists have sought to use an insulating such as speed and substrate to improve process characteristics latch-up susceptibility. The SOI CMOS technology
allows the creation of independent, completely isolated nMOS and pMOS transistors sapphire). virtually side-by-side on an insulating substrate (for example: The main advantages of this technology are the higher
integration density (because of the absence of well regions), complete avoidance of the latch -up problem, and lower parasitic capacitances compared to the conventional n-well or twin-tub CMOS processes. A crosssection of nMOS and pMOS devices in created using SOI process is shown in Fig. 12. The SOI CMOS process is considerably more costly than the standard nwell CMOS process. Yet the improvements of device performance and the absence of latch-up problems can justify its use, especially for deep-sub-micron devices.
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