SAN JOSE STATE UNIVERSITY College of Engineering

DEPARTMENT OF ELECTRICAL ENGINEERING

EE271

Synopsys Synthesis Tutorial

Introduction
Design Compiler is the core synthesis engine of Synopsys synthesis product family. It has 2 user interfaces: Design Vision - a GUI (Graphical User Interface) dc_shell - a command line interface The dc_shell interface supports two scripting languages: the dcsh mode that uses the original Synopsys language and the dctcl mode that uses the Tool Command Language (Tcl). This tutorial introduces the Synopsys Design Vision to the UNIX users. After you become more familiar with the commands, you can migrate to dc_shell. More information is available through the online tutorial and help.

Preparation
The design_vision and dc_shell are installed at /apps/synopsys/SYNTH/bin/design_vision and /apps/synopsys/SYNTH/bin/dc_shell. And the default libraries for synopsys are listed below and are at directory: /apps/synopsys/SYNTH/libraries/syn Libraries for implementation and link
lsi_7k.db lsi_9k.db lsi_10k.db lsi_lsc15.db nonlinear.db power_sample.db power2_sample.db class.db and_or.db gtech.db jtag.db tc6a_cbacore.db tc6a_cbamc.db

Libraries for link and synthetic

dft_jtag.sldb dft_mbist.sldb dft_lbist.sldb dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb dw06.sldb dw07.sldb dw_foundation.sldb standard.sldb

Libraries for schematic symbols

class.sdb generic.sdb lsi_10k.sdb tc6a_cbacore.sdb tc6a_cbamc.sdb

You can also use toshiba library at /apps/toshiba/sjsu/synopsys/tc240c, which includes: tc240c.db_BCCOM25 tc240c.db_WCCOM25 tc240c_wire_load.db tc240c.db_NOMIN25 tc240ct_io_macro.db tc240c.workview.sdb or OSC standard cell libraries at /apps/cadence/OSU_LIB/osu_stdcells/lib, which includes: ami035 and ami05 libraries tsmc018 and tsmc025 libraries For convenience, you can copy file ".cshrc" at "/tmp/EE271" into your home directory by command: cp /tmp/EE271/.cshrc . or make sure to set the following environment variables in your current ".cshrc" file
setenv setenv setenv setenv setenv setenv setenv setenv MYPATH $PATH SYNOPSYS /apps/synopsys SNPSLMD $SYNOPSYS/SYNTH VCS_ARCH_OVERRIDE linux SYNOPSYS_SIM $SYNOPSYS/SYNTH CLS_CSD_COMPATIBILITY_LOCKING NO SKIP_CDS_DIALOG VCS_HOME $SYNOPSYS_SIM

set path=($path $SNPSLMD/linux/bin ) set path=($path $SYNOPSYS ) set path=($path $SYNOPSYS/SYNTH/linux/syn/bin ) source $SYNOPSYS_SIM/bin/environ.csh

You then create a file named ".synopsys_dc.setup" (use exactly the same name). This is the Design Compiler setup file which is read and executed in the following location and order of priority: 1st: /apps/synopsys/SYNTH/admin/setup directory 2nd: user's home directory and then 3rd: user's current working directory A sample ".synopsys_dc.setup" file looks like the following. You can also copy this file by issuing command: cp /tmp/EE271/.synopsys_dc.setup .
designer="EE271 student" company="San Jose State University, EE Dept." search_path="/apps/synopsys/SYNTH/libraries/syn" search_path=search_path + "/apps/synopsys/SYNTH/libraries/syn" search_path=search_path + "./src" + "./db" link_library={"*","class.db","and_or.db","dw_foundation.sldb"} target_library={"class.db","and_or.db"} symbol_library={"class.sdb","generic.sdb"} synthetic_library={"dw_foundation.sldb","standard.sldb"} define_design_lib WORK -path ./work

Where: The default search_path tells the Design Compiler to search for files or db at the current directory and at the libraries/syn directory where all the vendor libraries sources and db are placed. Instead of using class.db as your library, you can navigate to any library in libraries/syn directory or 1 of libraries listed above, choose your preferred technology library and replace the above library assignment. The link_library is used to define any technology input to the synthesis process, the "*" is necessary as it tells the Design Compiler to search for the existing databases in the Design Compiler memory first. Link library is necessary only when the Verilog source code itself has instantiations from a library. The link library can be with extention .db or .sldb The target_library is the technology library to which you map your design during optimization. The symbol_library contains graphical data used to draw the symbols for the cells of the target or link libraries. Symbol library is necessary only when schematics from source codes will be generated by the synthesizer. The synthetic_library is the data base of compiled parts. It is used by the synthesizer for combinational operator inference. The define_design_lib is logical name referring to a UNIX directory which will store the intermediate files (the .mra .sim ... files) produced by

analyze so that it will not clutter up your present directory. You can choose other descriptive name besides work. When you do a design with HDL, it is better to partition the design to speed up optimization run times so that each block contains about 250 to 5000 gates. As an example, suppose you begin to work on your first project, say tutorial, you then design the structure of your work directory as below: /home/kr/kris9112> mkdir test /home/kr/kris9112> cd test /home/kr/kris9112/test> mkdir work /home/kr/kris9112/test> mkdir src /home/kr/kris9112/test> mkdir db /home/kr/kris9112/test> mkdir scripts Where the /src directory will contain your HDL source files. The /db directory will contain files in database format. The /scripts directory will contain script files used with dc_shell command mode if needed. The /work directory will be used by the compiler to store files created by it.

Simulate
You can use VCS as described in the VCS Tutorial handout or use the Analyze and Elaborate functions of the Design Vision to simulate your source codes. You first invoke the Design Vision by entering the following command at the parent working directory (/Synopsys_tut) /home/kr/kris9112/sanjay/EE271_Demo> design_vision & The tool will do the initialization (as displayed text below) and then the "Synopsys Design Vision" (main) window will pop up as shown in Figure 1 below

DC Professional (TM) DC Expert (TM) DC Ultra (TM) FloorPlan Manager (TM) HDL Compiler (TM) VHDL Compiler (TM) Library Compiler (TM) DesignWare Developer (TM)

DFT Compiler (TM) BSD Compiler Power Compiler (TM) Version C-2009.06-SP5 for linux -- Jan 15, 2010 Copyright (c) 1988-2009 by Synopsys, Inc. ALL RIGHTS RESERVED This software and the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software is subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. The above trademark notice does not imply that you are licensed to use all of the listed products. You are licensed to use only those products for which you have lawfully obtained a valid license key.

Figure 1: Synopsys Design Vision (main) window The directory where you invoke design_vision would contain the command.log file which lists the commands executed. You can verify if your .synopsys_dc.setup file

was executed by selecting File | Setup | Defaults and the "Defaults" window will pop up as shown in Figure 2 below. Close the "Defaults" menu window by selecting Cancel. DO NOT close any windows in the Design Vision by using the "close" window command of the native windowing environment but always use the Cancel buttons provided.

Figure 2: Defaults window Select View | Toolbar | Console Window to bring up the Command Window that gives you access to dc_shell and also immediate feedback on the progress of your synthesis session. All commands entered via the menus of the Design Vision are echoed and so you can learn how to write dc_shell scripts later on by observing the commands from the Command Window shown in Figure 3 below:

Figure 3: Command Window Before using Design Vision or Design Compiler to work on a design, it needs to read the design from disk into its active memory. This procedure is called reading in a design. As the design is read in, it is translated to a binary format (called .db format). The commands for reading files include the Analyze & Elaborate commands and the read command. The Analyze & Elaborate commands (always go together) read a HDL file, checks for proper syntax and synthesizable logic, and stores the design in an

intermediate format. The Analyze command can be used to read in each sub-design as well as the top level of the design hierarchy. The read command can be used to read in files that are in HDL and other formats such as the db, pla, etc. Although read command supports HDL formats, it does not do the language checking as accomplished by the Analyze and Elaborate commands. Now you can define your input source files for the Design Vision to work on. Select File | Analyze from the main window and the Analyze File window will pop up (Figure 4). Double click on the src/ under Directory: to see the appropriate files. Select the appropriate file(s) and the format of the file at the File Format selection button. To analyze more than one HDL file, click on the first file with the left mouse button and select the other files using the middle mouse button, or simply type them all in the "File Name(s)" box, separating the files with spaces (not commas). Click on WORK in the Library box, and click OK.

Figure 4: Analyze File window

The log window will appear as shown in Figure 5 when the analyze command doing syntax checking for your source(s). The command will create intermediate .syn files that will be stored in the directory work. The elaborate command goes to the work directory to pick up the .syn files and builds the design up to the Design Compiler memory. You now need to inspect the messages in the Analyze window and correct any syntax errors in your HDL files if needed and then do the "analyze" again. Once everything is fine, cancel the Analyze window and proceed.

Figure 5: Analyze window

From the main window, select File | Elaborate and the Elaborate Design window as shown in Figure 6 will pop up. On the Elaborate Design window, select WORK from the Library box, select your "top level design" from the Design box, and click the OK button. Elaboration brings all the associated lower level blocks into the Design Compiler automatically (by following the dependency of the instantiations within the HDL code) and the Log window will display information about this activity. After the elaboration is done as shown in Figure 7. Cancel the Elaborate window. Your design is now translated to a technology independent RTL model.

Figure 6: Elaborate Design window

Figure 7: Elaborate window

Setting Attributes
Attributes are values you set on a design that control or affect the optimization of the design. For example, attributes can specify the operating environment of the design and the constraint goals of optimization, as well as many other design parameters. Attributes

are available in the Attributes menu of Design Vision. Normally, the unit used for strengths/loads is in pF and for timings/delays is in ns. The Attributes menu contains submenus and windows that you can use to: Set input and output delays Set drive strengths Set loads Characterize sub-designs Select operating conditions Choose a wire load model Create or modify a clock The attributes available in the Operating Environment submenu are design properties that describe the internal conditions of a design and the designs interaction with its surroundings. After reading in a design, set attributes to determine design properties such as the drive strengths on ports, when signals arrive on ports, or the load driven by output ports. Attributes can affect the timing of your design. For example, drive strengths of the input ports and loading of output ports are two of the values used for timing calculations. If you dont set these attributes, timing results after optimization are unrealistic. In addition to loads and drive strengths, attributes can also specify information about the operating conditions or about which components optimization selects during gate-level implementation of your design. Now lets get back to our tutorial. Your Synopsys Design Vision (main) window now looks as the Figure 8 shown below. The encircled top buttons on the window are the View buttons. The two right buttons select the type of view: design symbol or schematic left 2 buttons are used to traverse the hierarchy of a design. Select the icon for your top level design block (counter) by clicking on it. The design is now counter as seen in the lower left corner of the main window.

Figure 8: Synopsys Design Vision Symbol window

Setting the attributes on the design object can be done by using the Symbol View.Click on the appropriate port and select from the Attributes menu your desired constraints. Select/highlight the port you want to constrain. Go to attributes->Drive Strength. You should see the port you have highlighted in port name box

Figure 9: Synopsys Design Vision window To set drive strengths, choose Attributes | Operating Environment | Drive Strength to display the Drive Strength window, as shown in Figure 9. Now click on use cell library as in figure 10 and select the appropriate library, and click on OK button.

Figure 10: Cell Library window Now your library must be added Strength window. Type the value 0.08 in the Rise Strength field. Click on Rise only option and specify rise time. Click on Fall only option and specify fall time. Deselect both rise only and fall only options if you want to apply both constrains

For this tutorial, we use drive strength value of 0.08 for all ports and drive strength value of 0.035 for the clock. You can set port drive values equal to the drive strength of library cell output pins. When you do not know the value of the pin you want in the library, you use the drive_of command to find out and set the drive value. You can set the loads on output ports, which are used to model the capacitive load on the output ports of the constrained module. You can set port load values equal to the load values of library cell input pins. When you dont know the library cell value you want, use the load_of command to determine and set a load value.

Figure 11: Load window Design Compiler optimization uses net fanout as a basis for estimating interconnect wire length from the wire load model. Design Compiler uses this information to calculate interconnect wiring and transition delays. The wire load model for a design depends on the estimated die size of the design. Wire load models are defined in the target library. Design Compiler uses area as a basis for automatically selecting the wire load tables if your ASIC libraries support this feature. To set the wire load, choose Attributes > Operating Environment > Wire Load and the Wire Load window will be opened with the listing of the wire load models and the target library. For this tutorial, let's use 10x10 class, which corresponds to a die size of 1mm x 1mm. Click O.K. to select the wire load model and then click Cancel to close the window.

Figure 12: Wire Load window The operating conditions of the design are the temperature, process, and voltage in which the design operates. The target library defines the operating conditions. Library vendors define default operating conditions, which can differ from one vendor to another. The Design Compiler static timing analyzer models the effects of variation in the drive strength, arrival time, and load values on a circuits timing characteristics. In a similar way, you can analyze a design for best-case, nominal-case, and worst-case performance or operating conditions. The setting of the operating conditions can be done by command Attributes | Operating Environment | Operating Conditions. For this tutorial, select the operating conditions as shown in Figure 13, where each set of operating conditions is followed by the name of the target library in parentheses.

Figure 13: Operating Conditions window You should now save your design to preserve your attribute settings. To save the design in .db format, choose File | Save As to open the Save Design window. Navigate to the db/ directory in the Directory menu and name your design as cntr_att.. Make sure that the Save All Designs in Hierarchy option is set to on.

Figure 14: Save File window You also can check for missing files by selecting File| Link Design from the main window. The link command checks to make sure all parts in the current design are available in Design_Vision's memory. If there is a missing part (also known as

unresolved reference), the information will be saved in a .ddc file and this file is read in automatically during the execution of the link command. After selecting the Analysis | Link Design, the Link Design window will pop up as shown in Figure 15. Clicking OK will start the link process link report will be displayed in log window

Figure 15: Link Design window To check your design's netlist description for problems like connectivity, shorts, opens, multiple instantiations, select Design | Check Design. You can also check for potential timing problems (i.e. no clocks specified, outputs unconstrained for time) by clicking on Timing |Check Timing. You may also select Design| Report Ports to generate a report to verify port attributes and delay constraints.

Applying Constraints for Optimization Goals

During optimization of a design, Design Compiler algorithms assess how best to implement the design. You direct Design Compiler decisions by defining optimization goals before you optimize. Your optimization goals are called constraints. Constraints are measurable circuit characteristics for timing, area, and power that you set on a design. Design Compiler checks your constraint goals during optimization and tries to meet them while synthesizing the design to your technology library. Your technology library contains important specifications of timing (ns), area (m2), and power (mw). To get the best results from Design Compiler, set your constraints to values that are close to your design goals. If timing goals are set unrealistically low (for example, 0), optimization adds buffers to critical paths or duplicates logic on heavily loaded nets. Trying to meet an unrealistic timing goal can result in a significant increase in area. If you dont set a timing goal, the Design Compiler default is to apply only design rule constraints to the design during optimization. Design rule constraints are requirements imposed by the technology to which you map your design. Usually, the clock period, timing numbers, and area of the circuit are provided in the design specification and so the goals are clearly defined at the outset. However, if goals might not be available in a design specification, or perhaps only a sub-design needs to be optimized (When optimizing a sub-design, you might know goals for the entire design but not for the sub-design.) When realistic goals are unknown, map the design or subdesign to gates without setting constraints. Mapping without constraints can help determine the current design speed. Use this design speed to determine a starting point value for constraints. As you recompile the design, you can refine your constraints. Note that if a design is currently in netlist format (mapped to gates), you can use the derive_timing_constraints command to extract the constraints. Before setting constraints for your design, it is good practice to remove any existing constraints. To remove existing constraints, enter the following dc_shell command in the Design Vision Window text field or at the dc_shell command prompt: remove_constraint -all After setting the constraints and attributes on your design and run the check_design, the design is ready to be optimized with the compile command. Optimization is the step in the synthesis process that attempts to implement a combination of library cells that meets the functional, area, and speed requirements of the design. The Design Compiler compile command invokes optimization. The compile process modifies and optimizes the design as it attempts to create a circuit that meets the specified constraints. If your design contains hierarchy, it is recommended to use the Bottom-Up Hierarchical Compile approach: Compile sub-blocks independently, but do not compile the top level design.

Now let's set constraints for our design. To set the clock constraint, select Attributes | Clocks | Specify and the Specified Clock window pop up as shown in Figure 16. Type in the value 20 for the clock period and click Apply.

Figure 16: Specify Clock window The Fix Hold option causes Design Compiler to fix violated hold times. Usually you request that Design Compiler first fix setup time violations. Then, after compilation, you check for hold-time violations. If hold-time violations exist after compilation, you recompile the design with Fix Hold selected. The Fix Hold option is not needed in this exercise. Note that a small waveform symbol now attached to the CLK port of the Symbol View showing that the constraint for clock sign is set. The input delays model the external delays arriving at the input ports of the constrained module. Input delays are defined relative to a real or virtual clock. Output delays model the external delays leaving the output ports of the constrained module. Output delays must be defined relative to a real or virtual clock to act as a path constraint. The output

delay corresponds to the time before the next rising edge. The output delay constraints can be set by the selecting the output port from the Symbol View and then use the Attributes | Operating Environment | Output Delay command. Similarly, the input delay can be set by the selecting the input port from the Symbol View and then use the Attributes | Operating Environment | Input Delay command. To set area constraint, select Attributes | Optimization Constraints | Design Constraints and use this dialog box to set design objectives for the toplevel of a design. The name of the top level is displayed in the Design Name field. Note that the units of area, time, capacitance are defined by the vendor. To find out about the contents of a technology library, type the following commands in the command window: read class.db report_lib class There is no menu option for set_driving_cell in Design Vision. Enter the command in the command window. It is in the following format: set_driving_cell -library libname -cell cellname -pin pinname portlist If no -library specified, default is the link library. -pin required only when the driving cell has more than 1 output pin. Below is an example: set_driving_cell -cell "IVA" all_inputs() - CLK The inputs (except for the port CLK) are driven by the "IVA" cell found in the link library. After setting constraints and attributes on the design and run check_design, the design is ready to be optimized with the compiling command Design|Copmile Optimization as shown in Figure 17. In general, the default settings are sufficient to meet defined constraints of most designsThe Allow Boundary Optimization allows for logic optimization across module boundaries of sub-designs. Compilation can run in either the background or the foreground. Compiling in the background has advantages that you can continue to work on the design while compiling it and you can save different versions of a compiled design in separate directories. Saving different versions allows you to select the one with the best results. After reading in the default variables and design for compile, Design Compiler begins the optimization process and reports the results on the Log window.

Figure 17: Design Optimization window

Inspection of Results
Notice the changes in the icon of your design, it is now optimized to gate level, double click on the icon to reach the Symbol View, then click on the Schematic View button to inspect the design. Select Zoom to zoom in zoom out or fit to window. You can select pin(s) or port(s) from the design, then select from Highlight a type of highlighting to see the path to the pin or port. Select a design block (the top level design if your design is hierarchical), do Design | Report Area and Design| Report Timing. Inspect the timing report, each Incr entry indicates the delay from the previous point to the current point, and the Path entry indicates the total delay from the input external delay to the current point. You can detect any suspicious path with exceptional long delay through this inspection. The most important thing is to check the slack, which is the required delay minus the actual delay, if it reports "MET", your design has met the timing constraints, if it reports "VIOLATED", you should go back to your HDL code and re-write it to improve timing. Then go back and re-analyze -elaborate the block and compile the whole design again.

Remember to save your design by selecting File | Save As and navigate to the db/ directory in the Directory menu and choose DB as the File Format, it is recommended to use the Save All Designs in Hierarchy option. Tutorial Example /* downcounter with zero flag */ module counter (clock, in, load, dec, zero); input input [3:0] input input output reg [3:0] wire clock; in; load; dec; zero; value; zero;

assign zero = ~|value; always @ (posedge clock) begin if (load) value <= in; else if (dec && !zero) value <= value - 1'b1; end endmodule

Remote Login
If you want to remote login, you can do that via ssh. You must have Hummingbird software installed on your PC in order for you to view graphical outputs. You can learn how to set-up ssh to view graphical outputs at http://www.uic.edu/depts/accc/software/exceed/sshexceed.html#Security Below is an example of setting up ssh:

Note: After remote login, Hummingbird must be running in background when you start VCS or design_vision in order for you to view the graphical outputs

Updated on Nov 4th 2010 Sanjay Krishnan & Asmita Kulkarni