0 07/19/12 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.

all;

vhdl example.vh

package somePackage is type fsmState is (stateA, stateB, stateC, stateD); function NextState (curState : fsmState) return fsmState; end somePackage; package body somePackage is function NextState(curState : fsmState) return fsmStates is begin if curState = fsmState'right then return fsmState'left; else return fsmState'rightof(curState); end if; end NextState; end somePackage; entity someEntity is generic ( width : natural := port ( Input1xDI Input2xDI ClockxCI, ResetxRB Output1xDO Output2xDO Output3xSO EnablexSI end someEntity;

5); : : : : : : : in in in out out out in std_logic_vector(8-1 downto 0); integer; std_logic; integer; std_logic_vector(width-1 downto 0); std_logic(1 downto 0); std_logic);

architecture behav of someEntity is component someOtherEntity generic ( size : integer range 1 to 15); port ( A, B : in std_logic; C : out std_logic(size-1 downto 0)); end component; type month is (january, february, march); -- go on ... type date is record date_year : integer range 1980 to 2030; date_month : month; date_day : dayOfMonth; end record; subtype dayOfMonth is integer range 1 to 31; type array4by3 is array(0 to 3) of std_logic_vector(0 to 2); signal AddressxS signal IntermSigxS signal SpringxS constant LUT4by3 : : : : natural range 0 to 3; unsigned(Output2xDO'range); boolean; array4by3 := ("111", "110", "101", "100");

begin U2 : someOtherEntity generic map (size => Output2xDO'length) port map (A => ResetxRB, B => ClockxCI, C => Output2xDO); Output3 <= Input1xDI(2 downto 1); -- selected signal assignment with currentMonthxS select currentQuarterxS <= q1st when january | february | march, Page 1

0 07/19/12 q2nd when april | may | june, q3rd when july | august | september, q4th when others;

vhdl example.vh

-- conditional signal assigment SpringxS <= true when (currentMonthxS = march and currentDayxS >= 21) o r currentMonthxS = april or currentMonthxS = may or (currentMonthxS = june and currentDayxS < 20) else false; -- a memless process statement p_memless : process (currentMonthxS, currentDayxS) variable blubbxS : std_logic; begin -- process p_memless SpringxS <= false; if currentMonthxS = march and currentDayxS >= 21 then SpringxS <= true; elsif currentMonthxS = april or currentMonthxS = may then SpringxS <= true; end if; if currentMonthxS = june and currentDayxS < 2 then SpringxS <= true; end if; Output3 <= (others => '0'); blubbxS := '1'; case currentDayxS is when 1 => Output3(0) <= '1'; blubbxS := '0'; when others => null; end case; Output(1) <= blubbxS; end process p_memless; -- a memorizing process statement p_memzing : process (ClockxCI, ResetxRB) begin -- process p_memzing if ResetxRB = '0' then -- asynchronous reset (active low ) IntermSigxS <= to_unsigned(0, IntermSigxS'length); elsif ClockxCI'event and ClockxCI = '1' then -- rising clock edge end if; end process p_memzing; end behav; -- ======= VHDL CONVERSION ======== -- (un)signed & slv : unsigned(some_int) ; signed(some_int) ; std_log ic_vector(some_un_signed) -- (un)signed & int : to_unsigned(arg,size) ; to_signed(arg,size) ; t o_integer(arg) -- int & slv : via (un)signed -- resizing : resize(arg,size) -- real & int : real(some_int) ; integer(some_real) -- ====== list of datatypes ======= -- integer, natural, real, std_logic, std_ulogic, std_logic_vector, std_u logic_vector, -- bit, boolean, signed, unsigned, string, file -- bit: 0 or 1 ; boolean: true or false -- ========== std_logic =========== -- logic state low unknown high -uninitialized U -strong 0 X 1 Page 2

0 07/19/12 -weak L W H -high-impedance Z Z Z -don't care -- for synthesis only 0, 1, Z, - can be used ---l, ---

vhdl example.vh

============= TODO ============= for-generate, custom types & subtypes, packages, procedure, function, process, assert, configurations, constants, examples (behav, structura rtl), component declaration & instantiation, sensitivity list, signal declaration, timing statements

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