KJST 1 (1) pp.

37-43 2011

KIST Journal of Science and Technology Volume 1 Number 1

RANA MUKHERJI* Faculty of Science and Technology, The ICFAI University, Dehradun 248197, Uttarakhand, India AMIT KUMAR CHATTERJEE Arasan Chip Systems, Bangaluru, Karnataka, India MANISHITA DAS Amity University Rajasthan, Jaipur-302006, Rajasthan, India

Implementation of an Efficient Multiplier Architecture Based on Ancient Indian Vedic Mathematics using SystemC
ABSTRACT Multiplication is an important elementary function in arithmetic operations. Multiplication-based operations for example- Multiply and Accumulate (MAC) and inner product are amongst some of the often used Computation- Intensive Arithmetic Functions presently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT), digital filters, etc. Since multiplication is the core computing process of most DSP algorithms, so there is a need of high speed multiplier. This paper proposed efficient multiplier architecture based on Urdhva Tiryagbhyam Sutra of ancient Indian Vedic Mathematics using SystemC. KEYWORDS Vedic mathematics Urdhva Tiryagbhyam Sutra SystemC

*CORRESPONDING AUTHOR

Rana Mukherji, e-mail : rana.mukherji@gmail.com, Tel. Mob: +91-9829669042/ 919359297107

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Rana Mukherji, Amit Kumar Chatterjee, Mahishita Das

INTRODUCTION Vedic mathematics, a bequest given to the humankind by the ancient sages of India. It is the name given to the ancient system of mathematics, which was reconstructed from ancient Vedic texts of Atharva Veda early in the last century by Sri Bharati Krishna Tirthaji (Swami, 1965). It is based on a set of 16 sutras (or aphorisms) dealing with mathematics related to arithmetic, algebra, and geometry. These techniques and ideas can be directly applied to trigonometry, plain and spherical geometry, conics, calculus (both differential and integral), and applied mathematics of various kinds. The elegance of Vedic mathematics lies in the fact that it diminishes otherwise cumbersome looking calculations in conventional mathematics to a very easy ones (Swami, 1965). It is only because the Vedic formulae are claimed to be based on the natural principles on which the human mind works. This is a very exciting field and shows some efficient aphorisms which can be applied to different branches of engineering such as computing and digital signal processing. This paper represents a possible application of Vedic mathematics to digital signal processing in the light of application of Vedic multiplication algorithm to digital multipliers (Mano, 2004) using SystemC. Digital multipliers are the core components of all the digital signal processing (DSP) applications and the speed of the DSP systems is largely determined by the speed of its multipliers. The two most common multiplication algorithms followed in the digital hardware are array multiplication algorithm and Booth multiplication algorithm. Since, in the array multiplier the partial products are calculated separately in parallel, the calculation time taken by is relative. Booth multiplication is another vital multiplication algorithm. Large booth arrays are needed for high speed multiplication and exponential operations which in turn require large partial sum and partial carry registers. If m is the number of Booth recorder adder stages used for multiplication of two n-bit operands using a radix-4 booth recording multiplier then it requires approximately n/(2m) clock cycles to generate the least significant half of the final product, where m is the number of Booth recorder adder stages. Thus, a large propagation delay is involved with this case. Due to the importance of digital multipliers in DSP, it has
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always been an active area of research. This work represents SystemC implementation of a simple digital multiplier architecture based on the ancient Vedic mathematics Sutra (formula) called Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra which was traditionally used for decimal system in ancient India. According to (Leonard, 2010), this Sutra is most efficient Sutra than other Vedic multiplication techniques (Nikhilam and Anurupye), giving minimum delay for multiplication of all types of numbers. The paper is organized as follows. In Section 2, a brief overview of the Vedic Sutras is discussed. Section 3 provides a brief of SystemC language. Section 4 provides the design methodology which includes the Vedic multiplication algorithm and hardware architecture of the proposed Vedic multiplier. Finally, Section 5 draws the conclusion. VEDIC MULTIPLICATION ALGORITHM The Vedic Sutras The Sanskrit (an ancient language of India) word Veda means knowledge and the Vedas are considered the most sacred scripture of Hinduism referred to as sutras, meaning what was heard by or revealed to the seers. Vedas are the most ancient scriptures dealing with all branches of knowledgespiritual and worldly. Vedic mathematics is based on 16 Sutras (or aphorisms) dealing with various branches of mathematics like arithmetic, algebra, geometry etc (Leonard, 2010).These Sutras along with their brief meanings are enlisted below alphabetically. 1) (Anurupye) Shunyamanyat If one is in ratio, the other is zero. 2) Chalana-Kalanabyham Differences and Similarities. 3) Ekadhikina Purvena By one more than the previous one. 4) Ekanyunena Purvena By one less than the previous one. 5) Gunakasamuchyah The factors of the sum is equal to the sum of the factors. 6) Gunitasamuchyah The product of the sum is equal to the sum of the product. 7) Nikhilam Navatashcaramam Dashatah All from 9 and the last from 10. 8) Paraavartya Yojayet Transpose and adjust. 9) Puranapuranabyham By the completion or noncompletion. 10) Sankalana-vyavakalanabhyam By addition and by subtraction.

Implementation of an Efficient Multiplier Architecture Based on Ancient Indian Vedic Mathematics using System C

11) Shesanyankena Charamena The remainders by the last digit. 12) Shunyam Saamyasamuccaye When the sum is the same that sum is zero. 13) Sopaantyadvayamantyam The ultimate and twice the penultimate. 14) Urdhva-Tiryagbyham Vertically and crosswise. 15) Vyashtisamanstih Part and Whole. 16) Yaavadunam Whatever the extent of its deficiency. Urdhva-Tiryagbyham Sutra Urdhva means vertically up-down, Tiryakbhyam means left to right or vice versa. This Sutra has been traditionally used for the multiplication of two numbers in the decimal number system. In this work, same scheme had been applied to the binary number system to make it compatible with the digital hardware. Let us first exemplify this Sutra with an example in which two decimal numbers are multiplied. Line diagram for the multiplication of two numbers (524 X 872) is shown on Figure 1. The digits on the two ends of the line are multiplied and the result is added with the previous carry. When there are more lines in one step, all the results are added to the previous carry. The least significant digit of the number thus obtained acts as one of the result (Chidgupkar et al., 2004; Thapliyal and Srinivas, 2004).

SystemC LANGUAGE EVOLUTION of SystemC On September 1999, Open SystemC Initiative (OSCI) was announced by leading EDA, IP, semiconductor, systems and embedded software companies at the Embedded Systems Conference, San Jose, California. The OSCI steering group includes ARM, CoWare, Inc., Cygnus Solutions, Ericsson, Fujitsu, Infineon, Lucent Technologies, Sony Corporation, STMicroelectronics, Synopsys, Inc. and Texas Instruments (Grtker, et. al 2002; Swan, 2006). SystemC is the first outcome of the initiative, which facilitates, promotes and accelerates system-level intellectual property (IP) model exchange and codesign using single unified C++ modeling environment (Smria and Ghosh, 2000). The initiative provided an Open Community Licensing model through which designers can create, validate and share models with other companies using SystemC and a standard ANSI C++ compiler. In addition, electronic design automation (EDA) vendors have complete access to the SystemC modeling platform required to build interoperable tools. There is no licensing fees associated with the use of SystemC, and any company is free to join and participate. The objective of the Open Community Licensing model is to offer a foundation to assemble a market upon, and the responsibility of the steering group is to deliver an environment of structured innovation ensuring that interoperability is maintained.

SystemC DESIGN ENVIRONMENT SystemC is a C++ class library for modeling system-level design and IP exchange. It has become a new standard in the Electronic Design Assembly (EDA) field and many designers have started to use it to model complex systems. SystemC facilitates the co- verification of hardware and software platforms by providing a single language framework based on C++ with which the designers describes both hardware and software components. Thus, it would be possible to imagine a SystemC based design flow, in which the system description is translated from one abstraction level to the following one by always using SystemC representations. However, unlike traditional HDLs (VHDL/ Verilog), SystemC provides sophisticated mechanisms that offer high abstraction levels on component interfaces. Fig. 1. Multiplication of Two Decimal Numbers by This, in turns facilitates integration of systems Urdhva Tiryakbhyam Sutra.
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Rana Mukherji, Amit Kumar Chatterjee, Mahishita Das

using different abstraction levels. Furthermore, SystemC is not a new language; it is C++, consequently, the existing software IP can be seamlessly linked into a SystemC project. Need of System Level Modeling Language. The traditional design methodology (Figure 2) starts with a system engineer who conceptualize the system design, write a C or C++ model of the system, simulate and verify the functionality at the system level. After satisfaction, the executable specifications are handed over to HDL designers to implement it manually to a HDL (generally VHDL or Verilog) description for actual hardware implementation. This approach has a number of problems. With the methodology, the system designer creates the C++ model, verifies its functionality, and then transfer to HDL designers who translates the design manually into an HDL.The HDL designers then re-verify the design hardware descriptions and assembly software modules and synthesize it to gates. This process is very tedious, time consuming and error prone. Secondly, the written specifications in C++ model are incomplete and inconsistent. More precisely, we can say that something in the C++ model cannot be implemented in the HDL design since there is no common environment between the C++ model and HDL implementations (Mukherji, 2008; Mukherji, 2004).

Fig. 3. SystemC Design Flow

the necessary hardware and timing constructs to produce a good design. Using this method, the HDL designer can more easily implement design changes and moreover, the debugging is comparatively effortless during refinement. SystemC allows modeling from the system level to RTL, if necessary. The conversion time is also saved since the testbenches can be reused from the system level model to the RTL model for verification. The HDL designers will be more convinced using the same testbench since the system level and the RTL model implement the same functionality (Jrme, et.al, 2006). SystemC Language Architecture. Figure 4 summarizes the SystemC language architecture and Figure 5 describes the design environment of SystemC. There are several important concepts to understand from this diagram.

Fig. 2. Non-SystemC design flows

Fig. 4. SystemC Language Architecture

With SystemC Design Environment (Figure 3), both the designers only need to write their models in SystemC. There is no requirement of converting a C++ model description to an HDL. The HDL designer has to do only refine in small sections of the conceptual model to add
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SystemC needs only a C++ compiler to perform system modeling an optimal set of modeling constructs are provided by SystemC core language. Modules: SystemC has a notion of a container class called a module. This is a hierarchical entity

Implementation of an Efficient Multiplier Architecture Based on Ancient Indian Vedic Mathematics using System C

that can have other modules or processes contained in it. Processes: Processes are used to describe functionality. Processes are contained inside modules. SystemC provides three different process abstractions to be used by hardware and software designers: (i) methods, (ii) threads and (iii) clocked threads. Methods are simplest form of a process. After being triggered by an event, it executes until it reaches its end. Threads, on the other hand, can be suspended and activated by the simulation kernel and reactivated again from their current position. Clocked threads are a special case of Threads sensitive only to the clock signal. Ports: Modules have ports through which they connect to other modules. They are similar in function to VHDL and Verilog input/output ports. SystemC supports both single-direction and bidirectional ports.

the implementation details. It also supports RTL design, and this subset is usually called as SystemC RTL. Concurrency: To simulate the concurrent behavior of the digital hardware, the simulation kernel is so designed that all the processes are executed concurrently, irrespective of the order in which they are called (Panda, 2001). It is also possible to provide additional libraries to support a particular design methodology. Examples of this are the Master-Slave Communication Library, and the SystemC Verification Library (SCV). SystemC Simulation Kernel (Courtesy Sirpatil, 2002). SystemC design can be compiled using any C++ compiler. It has a built in cycle-based simulation kernel to simulate the designs (Figure 6). The subsequent executable specification realizes the model and the simulation kernel.The simulation kernel is built into the class library and desires no peripheral tools for simulation of the model. The source code for the kernel and the library is existing with the distribution of the SystemC platform. Each one of the userdefined processes is executed independently of the others and also the kernel. Simulation commences with a call to the function sc_start(). At the start of the simulation all the processes are initialized and scheduled for implementation. All of the processes acquire a chance to execute in each simulation cycle. The order of execution is not distinct. Any changes in the signal values are not instantaneously updated. Signals are allotted new values only in the next simulation cycle. This builds the simulation cycle precise. A process that is executing or is scheduled to be executed is in an active state. An active process goes into a suspended state after it completes its operation or reaches a wait statement. Once all

Fig. 5. SystemC in a C++ Development

SystemC provides a rich set of data types to support multiple design paradigms and abstraction levels. SystemC also provides a set of predefined primitive channels such as signals, shared variables and FIFOs which strengthen the ability to connect modules of different abstraction levels into a system model. It comes with a strong simulation kernel to enable the designers to write good test benches easily, and to simulate it. This is important because the functional verification at the system level saves a lot of labour and time. It introduces the notion of time to C++, to simulate synchronous hardware designs. This is common in most of the HDLs. While most of the HDLs support the RTL level of design, SystemC supports the design at a higher abstraction level. This enables large systems to be modeled easily without worrying Fig. 6. SystemC Simulation Cycle

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Rana Mukherji, Amit Kumar Chatterjee, Mahishita Das

the processes are in a suspended state, the kernel then updates the signals, advances simulation time and enters into the next simulation cycle. The simulation flow is illustrated in Figure 7.

Fig. 7. SystemC Simulation Flow

DESIGN METHODOLOGY The Proposed Vedic Multiplier To illustrate the multiplication algorithm, let us consider the multiplication of two binary numbers X3X2X1X0 and Y3Y2Y1Y0. As the result of this multiplication would be more than 4 bits, we express it as... R3R2R1R0. Line diagram for multiplication of two 4-bit numbers is shown in Figure 4 which is nothing but the mapping of the Figure 8 in binary system. For simplicity, each bit is represented by a circle. Least significant bit R0 is obtained by multiplying the least significant bits of the multiplicand and the multiplier. The process is followed according to the steps shown in Figure 8. Firstly, least significant bits are multiplied which gives the least significant bit of the product (vertical). Then, the LSB of the multiplicand is multiplied with the next higher bit of the multiplier and added with the product of LSB of multiplier and next higher bit of the multiplicand (crosswise).

The sum gives second bit of the product and the carry is added in the output of next stage sum obtained by the crosswise and vertical multiplication and addition of three bits of the two numbers from least significant position. Next, all the four bits are processed with crosswise multiplication and addition to give the sum and carry. The sum is the corresponding bit of the product and the carry is again added to the next stage multiplication and addition of three bits except the LSB. The same operation continues until the multiplication of the two MSBs to give the MSB of the product. For example, if in some intermediate step, we get 110, then 0 will act as result bit (referred as Rn) and 11 as the carry (referred as Cn). It should be clearly noted that Cn may be a multi-bit number. Thus we get the following expressions: R0=X0Y0 C1R1=X1Y0+X0Y1 C2R2=C1+X2Y0+X1Y1 + X0Y2 C3R3=C2+X3Y0+X2Y1 + X1Y2 + X0Y3 C4R4=C3+X3Y1+X2Y2 + X1Y3 C5R5=C4+X3Y2+X2Y3 C6R6=C5+X3Y3, The final product will be C6R6R5R4R3R2R1R0. Hence this is the general mathematical formula applicable to all cases of multiplication.

Fig. 8. Line Diagram for Multiplication of Two 4-bit Fig. 9. Hardware Realization of a 4-bit Multiplier Using Numbers Urdhva Tiryakbhyam Sutra
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Implementation of an Efficient Multiplier Architecture Based on Ancient Indian Vedic Mathematics using System C

The hardware realization of a 4-bit multiplier using this Sutra is shown in Figure 9. This hardware design is very similar to that of the famous array multiplier where an array of adders is requited to arrive at the final product. All the partial products are calculated in parallel and the delay associated is mainly the time taken by the carry to propagate through the adders which form the multiplication array (Kumar, et. al., 2010). RESULT The design is implemented using Windows 7 as platform and MS Visual Studio 2008 as simulator for SystemC (version 2.2) whereas the waveforms are seen through BlueHDL VCD Viewer (Figure 10).

DSP algorithm are receiving increased attention among researchers and design engineers. Faster additions and multiplications are the nucleus of these complex applications. By using these ancient Indian Vedic mathematics techniques, the world can reach new heights of performance and excellence for the cutting edge technology devices.
Chidgupkar, P. D. and Karad, M. T., 2004, The Implementation of Vedic Algorithms in Digital Signal Processing, Global J. of Engg. Edu., 8(2), pp 153-157. Grtker, T., et. al , 2002, System Design with SystemC, Kluwer Academic Publishers. Jrme C. et.al, 2006, A SystemC Refinement Methodology for Embedded Software, Proceedings of IEEE Design & Test of Computers , pp 148-158. Kumar, A. et. al., 2010, High Speed Reconfigurable FFT Design by Vedic Mathematics, Journal of Computer Science And Engineering, 1(1), pp 5963. Mano, M. M., 2004, Computer System Architecture, Pearson Education, Delhi, India. Mukherji, R., 2004. Behavior Modeling of the Application Specific Instruction Set Processor (ASIP) For Text-to-Speech Synthesis Using SystemC, M. Tech. Dissertation, Panjab University, Chandigarh, India. Mukherji, R., 2008, SystemC-based Design Approach for Modeling Reconfigurable Computing Systems, The Icfai University Journal of Science and Technology, 4(3), pp 30-40. Panda, P.R., 2001, SystemC - A Modeling Platform Supporting Multiple Design Abstractions, Proceedings of the 14th ISS S, pp 75 -80. Smria, L. and Ghosh, A., 2000, Methodology for Hardware/Software Co-verification in C/C++, Proc. Asia and South Pacific Design Automation Conference ASP-DAC00, pp 405-408. Sirpatil, B., 2002. Software Synthesis of SystemC Model, M.S. Dissertation, Virginia Polytechnic Institute and State University, Blacksburg,Virginia. Swami Bharati, K. T. ,1965, Vedic Mathematics, Motilal Banarsidass Publishers, Delhi, India. Swan, S., 2006, SystemC Transaction Level Models and RTL Verification. Proc. 43th Design Automation Conf. (DAC 2006), IEEE Press, 1, pp. 90-92. Thapliyal, H. and Srinivas, M. B., 2004, High Speed Efficient NN Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics. Enformatika Trans, 2,pp225 228.

REFERENCES

Fig. 10. Waveform Result

CONCLUSION Vedic mathematics was restructured from the ancient Indian scriptures (Vedas) by Sri Bharati Krishna Tirtha (1884-1960) after his eight years of research on Vedas. As per his research, Vedic mathematics is principally based on sixteen principles or word-formulae which are called as Sutras. The algorithms based on conventional mathematics can be simplified and even optimized by the use of these Sutras. These methods and ideas can be directly applied to trigonometry, plain and spherical geometry, conics, calculus (both differential and integral), and applied mathematics of various kinds. In this paper, general technique for 4X4 multiplier architecture based on the Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra of Vedic mathematics is proposed and implemented on SystemC platform. Due to a growing demand for complex DSP application, high speed, low cost system-on-a-chip (SOC) implementation of

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