EN315 VLSI

Safwat Mansi E305 safwat.mansi@unn.ac.uk

VLSI Design (EN315)

Outline Syllabus IC Manufacturing Processes and Technologies (SM) Processing Steps, Layout Geometrical Rules, Yield and Economics MOS/BJT Transistors and Basic (Bi)CMOS circuits (SM) Device structures, equations and parameters, SPICE models Device sizing and scaling, noise margin, power dissipation Inverters, transmission gates, simple and compound logic gates, latches and flipflops Propagation Delays and Clocking strategies Sub-systems and Architectures Memories, PLAs and FSMs, Floorplanning (SM) Arithmetic Circuits, Data-paths and Controllers (IDE & SM) Design Strategies and Implementation (IDE) Hierarchy, Modularity, Regularity and Locality CPLD, FPGA, MPGA, SoC, Std Cell and Full Custom ASIC

VLSI Design (EN315)

Outline Syllabus

Design Capture and Verification Verilog-HDL : behavioural, data-flow, gate and switch levels. Physical Layout level (IDE) HDL-based Simulation and Synthesis (IDE) Full-custom ASIC tools : DRC, ERC, Extraction etc. (SM)

IC Test and Design for Test (IE) Physical faults, the Fault Cycle, Reliability Test Pattern Generation and Fault Simulation DfT Strategies and Techniques (Scan, BILBO, BIST)

VLSI Design (EN315)

Assessment Assessment Formal Exam (80%) , Lab (20%)

Useful sources of information Baker, Li and Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, ISBN 0-7803-3416-7 Weste and Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley Pucknell and Eshraghian, Basic VLSI Design, Prentice-Hall

Outline Course Syllabus

Understand and overview of
FET Technology Bipolar Technology

MOSFET and Bipolar devices and subsystem IC Production Process Basic design, architectures and design rules

Lecture 1&2: Introductory Topics

g

IC Brief History MOS Transistors N-Type (NMOS) Transistor P-Type (PMOS) Transistor Logic gates

IC History -- Brief
1925 J Lilienfeld proposed basic principle behind the MOS FET 1935 O Heil proposed a structure similar to modern MOS Tr. 1925 to 1960s problems with materials foiled early attempts Invention of the Bipolar Tr. led to decline of interest in MOS Trs

IC History -- Brief Continue

1959 Independent invention of the silicon planar process by Robert Noyce and Jack Kelby 1960s P K Weimer of RCA patent (May 62 issued 65) the use of both polarity devices on the same substrate featuring the elements of modern CMOS flip-flop, demonstrating possible implementation in thin-film-Tr technology

IC History -- Brief Continue

Frank Wanlass of Fairchild Semiconductor Research and Development (filed a patent 1963 - granted 1967) cover the CMOS concept and three circuits: the Inverter, NOR gate and NAND gate implemented as MOS devices. He used discrete MOS TRs. and built his own nMOS Trs.

IC History -- Brief Continue

1965 Introduction of MOS first calculator using single polarity p-type transistors 1971 Emergence of the nMOS-silicon gate technology

IC Transistor Count
Since 1961 the number of Trs that can be successfully fabricated on single chip has doubled almost every year (Moors Law)

Number of Trs in an IC chip

100,000,000 10,000,000 1,000,000 100,000 10,000 1,000 100 1 1960 1970 1980 1990

Transistors/IC

Moors Paper

Year
2000

IC Feature Size: Classification

Typical minimum feature size is the minimum
gate length or polysilicon width or metal width.

Min feature size = Min Width of the given layer

IC Feature Size: Classification

The pitch
is the minimum of the sum of
the min. width of a feature and the min. spacing between similar features

the pitch is approx. twice the min. feature size

The Pitch

Tr Feature Size
Tr Feature size in microns
30

10

1 0.5 0.1 1960 1970 1980 1990 2000

Year

Transistor Layout/Size
Polysilicon
FET MOS

Diffusion
SiO2 Insulator

Advantages of device shrinking

Decrease of device sizes Increase in device count Increase of circuit speed
speed increases approx.. linearly with feature size reduction

Improve in yield (=% of chips that are good)

Feature size shrinking limitation

Increase of processing equipment cost More complex software design aid Deterioration in matching characteristics Increase impact of interconnection delays Increase power dissipation density Processing complication due to heat cycling limitations during fabrication

Benefits of smaller Die size

More chips (dies) per wafer
reduction in the effective cost per chip

Yield decreases rapidly with increasing die size The amount of wafer wastage around the periphery is reduced with smaller chips

Monolithic Integrated Circuit

An IC whose elements are
formed in place upon or within a semiconductor substrate with at least one of the elements formed within the substrate

Substrate

IC Classifications: Device Count

SSI Gates , Opamps, Many linear applications MSI 102 - 103 Registers, Filters, etc LSI 103 - 105 Microprocessors, ADC, DAC etc VLSI 105 - 108 Memories, Computers, Signal Processors ULSI&GLSI > 108 DSP 1 - 102

Transistor Count per Die

For a 2 cm square die calculate the number of transistors for
2 micron Technology

0.2 micron Technology

Transistor Count per Die

For a 2 cm square die calculate the number of transistors for
2 micron Technology No of Squares = (2x10-2)2 / (2x10-6)2 =108 If each Tr require 50 squares 2 cm then no of transistors = 2 x 106 2 cm

2um

Transistor Count per Die

For a 2 cm square die calculate the number of transistors for

0.2 micron Technology No of Tr = (2x10-2)2 / [(0.2x10-6)2 x 50] = 2 x 108

Transistor Count per Die

For a 2 cm square die calculate the number of transistors for

2 micron Technology No of Squares = (2x10-2)2 / (2x10-6)2 =108 If each Tr require 50 squares then no of transistors = 2 x 106 0.2 micron Technology No of Tr = (2x10-2)2 / [(0.2x10-6)2 x 50] = 2 x 108 (ie 100* )

Directions in Process Technology

30 Contact Printing Projection Printing Wafer Steppers E-Beam 1 0.5 0.1 1960 1970 1980 1990 2000 X-Ray

Microns
10

Year

Independent Study 1
Use the library (books, journals, Internet) to investigate the trends and directions in ASIC manufacturing Process Technology
Methods used Technology features & design rules Yield issues Costs

Factors for Transistor Count Growth

Reduction in line width due to
development of high-resolution lithographic techniques improved processing capabilities

Increase in the size of the silicon wafer due to improved

reliability of processing growth of the accumulated circuit layout design experience

Factors for Transistor Count Growth

Better understanding of system level design issues leading to improved architectures that can exploit the technology The availability of better automated design tools for circuit design, layout, simulation, verification and testing.

MOS Transistors

Doping of wafers
Silicon has 4 electrons in the valence band Wafer is doped with
donor (with 5 valence electrons) atoms, e.g. Phosphorus for n-type wafer acceptor atoms, e.g. Boron for p-type wafer

P-type and n-type wafers can be used to design circuits. Commonly, p-type wafers are used.

Transistors and wafers

P-type wafer
n-channel NMOS transistors (MOSFETs) are fabricated directly in the p-type wafer (substrate) p-channel PMOS transistors are fabricated in an n-well

N-type wafer
PMOS transistors are fabricated directly in the ntype wafer (substrate) NMOS transistors are fabricated in an p-well

NMOS FET Device

P-doped semiconductor Substrate

NMOS FET Device

Insulator

P-doped semiconductor Substrate

NMOS FET Device

Polysilicon

P-doped semiconductor Substrate

NMOS FET Device

Highly doped diffused regions

n+

n+

P-doped semiconductor Substrate

NMOS FET Device Enhancement Mode Transistor

Polysilicon GATE Source Drain n+ Transistor Channel P-doped semiconductor Substrate n+

n-Type
Enhancement Mode Transistor

Start with P- Doped Substrate

No need for N-well in N-Type Transistor

Thin-oxide Growth in all N+ & P+ Areas

Polysilicon Deposit for Gates and Interconnects

Polysilicon Gate

Etch this to allow implanting the Source & Drain areas

N+ Implant for n-Channel MOS and tie toPolydd V Gate

Source N+ N+

Drain

P+ Implant for p-Channel MOS and tie to Vss

This process step is not required here

N+

N+

Metal Deposit for Contact to Diffusion

Source Contact

Drain Metal Contact

First Metal Layer Interconnections

Gate - If connected to Vdd switches the transistor on

Enhancement mode operation n-Type Transistor

FET nMOS Depletion mode Transistor

Polysilicon GATE Source Drain n+ Transistor Channel P-doped semiconductor Substrate n+

n implanted channel

Depletion mode operation n-Type Transistor

FET pMOS Enhancement mode Transistor

Polysilicon GATE Source p+ Transistor Channel N-doped semiconductor Substrate p+ Drain

p-Type
Enhancement Mode Transistor

Start with P- Doped Substrate

N- Implant in all well zones

N-Well

Thin-oxide Growth in all N+ & P+ Zones

Polysilicon Deposit for Gates and Interconnects

Etch this area to diffuse N+ for contact

N+ Implant for n-Channel MOS Etch this area and tie to V dd +

to implant P N+

This is to be tied to Vdd

P+ Implant for p-Channel MOS and tie to Vss

Drain Source P+ P+ N+

Metal deposit for contact to diffusion

First metal layer interconnections

Enhancement mode operation p-Type Transistor

FET pMOS Depletion mode Transistor

Polysilicon GATE Source p+ Transistor Channel N-doped semiconductor Substrate Drain p+

p implanted channel

Depletion mode operation p-Type Transistor

NMOS Transistor Switch

NMOS Transistor GATE acts as the switch control If G = 0 the Transistor is open OFF If G = 1 the Transistor is closed ON

b g

a g=0 a

b g=1

FET nMOS Transistor

nMOS Tr is off
n+ Transistor Channel without active Carriers (electrons) n+

P-Substrate

NMOS FET Device

Positive side of the battery

NMOS Tr is on
n+ Transistor Channel with inverted layer (electrons)
electrons

n+

P-Substrate

PMOS Transistor Switch

PMOS Transistor GATE acts as the switch control If G = 1 the Transistor is open OFF If G = 0 the Transistor is closed ON

b g

a g=1 a

b g=0

PMOS FET Device

PMOS Tr is off
p+ p+

Transistor Channel without active Carriers (holes)

N-Substrate

PMOS FET Device

Negative side of the battery

PMOS Tr is on
p+
holes

p+

Transistor Channel with inverted layer (holes)

N-Substrate

MOS Transmission Characteristics

NMOS Transistors Transmit
perfect 0 poor 1

PMOS Transistors Transmit

perfect 1 poor 0

FET n-Type Pass Transistor

G=5v n-Type is fully ON

Vgs is constant

Vgs = 5v a=0

Id ON OFF 0 V th

Discharge to 0v

Parasitic Capacitance

Vgs

FET n-Type Pass Transistor

Assume Cparasitic is initially at 0v

G=5v
Vgs

n-Type initially ON It will switch off when Vgs < Vth

Id ON OFF 0 V th

a=5v Charges to (5-Vth) v

Parasitic Capacitance

x Vgs

Vgs decreases as Vc increases

FET p-Type Pass Transistor

Assume Cparasitic is initially charged p-Type initially ON It will switch off when Vgs > Vth

G=0 v

Vgs =ve

a=0v
Id O N

x
Vth 0

OFF

Discharges to (~Vth) v
Vgs

Parasitic Capacitance

Vgs increases from -5v to -Vth

FET p-Type Pass Transistor

Vgs is always -5v
Vgs = -5v

G=0v

p-Type is fully ON Cparasitic will charge to 5 v

a=5v
Id O N

x
Vth 0

OFF

Charges to 5 v
Vgs

Parasitic Capacitance

Exercise
x y z

What are the out values (B1, B2 & B3) when inputs A, x, y & z assumes all possible logic combinations of 0 and Vdd?

A
x y z

B1 B2
x y z

A A

B3

Transmission Gate
Combine a p- and ntype transistors to build a perfect switch p-gate must be connected to the complement of n-type. The switch is
ON when C=1 OFF when C=0

C a

P-Type b

N-Type

The Well
N-well P-type epitaxial layer (p-)

P-type Substrate (p+) N-well

Many processes dont use the epitaxial (epi) layer

P-type Substrate

Patterning Sequence of Events

Sequence Events of Device Processing

This is part of the directed study
Students are encouraged to investigate / understand the different processes used in the development of
CMOS devices Bipolar Devices Bi-CMOS Devices

General Processing Sequence

Insulator
Top of wafer before oxidation Top of wafer after oxidation

P-type substrate 1

P-type substrate 2

1- Clean , bare wafer 2- 1st step is to grow oxide on the surface of the wafer Si + O2 SiO2 (dry) or Si + 2H2O SiO2 + 2H2 (wet) Reaction with steam, H2O, results in wet oxide, or with O2 alone resulting in dry oxide. Both The oxide growth consumes silicon Consumed silicon 0.45 Total insulator thickness

Wet and Dry Oxide Growth (thermal oxidation)

Both wet and dry oxides are called thermal oxides due to the increased temperature (over 900oC) used during oxide growth.
Oxide growth rate is directly proportional to the temperature Wet oxide growth is faster than dry oxide. (advantage) Hydrogen is a by-product of wet oxide process (disadvantage). Ie wet method is not pure as dry method Dry oxide growth is slow (disadvantage) Oxide thickness increases with time.

Processing Sequence - Continued

Photo-resist Insulator - Oxide P-type substrate 3

3 Deposit photosensitive resist (photoresist) layer across the wafer. Bake the resist

Processing Sequence - Continued

Mask (reticle) Photo-resist Insulator - Oxide P-type substrate 4 4 Preparation and placement of the mask over the wafer. The mask is developed from the circuit layout. The mask is used to project the patterns required to create multiple copies of a single chip.

Processing Sequence - Continued

Ultraviolet light Mask (reticle) Photo-resist Insulator - Oxide P-type substrate 5 The light passing through the opening illuminate the unmasked areas of the photo-resist.

Processing Sequence - Continued

Ultraviolet light Ultraviolet light

Hardened resist

P-type substrate 6 6 Positive resist when illuminated area is removed

P-type substrate 7

7 Negative resist when un-illuminated area is removed.

Processing Sequence - Continued

P-type substrate 8 8 Develop exposed photoresist

P-type substrate 9

P-type substrate 10

9 Etch the exposed oxide. The etchant etches under the resist 10 Remove the resist

Now N-type or P-type can be implanted

N-Well Process Sequence

Photo-resist Mask (reticle)

P-type substrate 1 Ultraviolet light

P-type substrate 2

P-type substrate 3

P-type substrate 4

N Well Processing Sequence

Donor atoms diffusion P-type substrate 5 P-type substrate 6

P-type substrate 7

N-Well

P-type substrate 8

Electrical Properties of Layers

A typical 2-metal N-Well CMOS Process

Resistance
Layer can be used as resistor
A B

N-well P-substrate

Layers Resistance
N-Type Diffusion P-Type Diffusion Polysilicon Metal1 Metal2 N-Well 60 ohm/sq 80 ohm/sq 25 ohm/sq 0.04 ohm/sq 0.03 ohm/sq 1500 ohm/sq

Capacitance
Parasitic capacitance
Bottom capacitance

N+ SideSide-wall capacitance P-substrate

Layer to Layer Capacitance

Gate to Substrate Polysilicon to Substrate N+ to Substrate P+ to substrate Metal1 to Substrate Metal1 to N+ / P+ Metal2 to N+ / P+ 1400 X 10-6 pF/u2 50 X 10-6 pF/u2 130 X 10-6 pF/u2 130 X 10-6 pF/u2 25X 10-6 pF/u2 50 X 10-6 pF/u2 15 X 10-6 pF/u2

Layers Capacitance
Metal1 to Polysilicon Metal2 to Polysilicon Metal2 to Substrate Metal2 to Metal1 50 X 10-6 pF/u2 20 X 10-6 pF/u2 11 X 10-6 pF/u2 45 X 10-6 pF/u2

Diode effect in an n-well process

The n-well and the p-substrate form a diode In CMOS circuits, the substrate is usually tied to the lowest voltage to keep this diode from forward biasing
N-well

P-substrate

N-well
Can be used for
fabrication of p-channel transistors as a resistor, with large enough voltages at either resistors sides to keep the substrate / well diode from forward biasing.