Automatic Device Sizing in Analog Circuit Design

Robert Hgglund, Emil Hjalmarson, and Lars Wanhammar

Department of Electrical Engineering SE-581 83 Linkping, Sweden E-mail: roberth@isy.liu.se, emilh@isy.liu.se, larsw@isy.liu.se

ABSTRACT
In this paper we describe an optimization-based method for sizing the devices in an analog circuit to meet a set of given constraints. The current optimization method does not guarantee to nd an optimal solution but nds a set of good solutions within a short time. To decrease the computation time no external simulators are used, instead the transistor model, BSIM3v3, has been integrated into the program. The motivation to use an optimization-based device sizing program for analog circuit design are to increase the design efciency and use more complex cost functions.

1. INTRODUCTION
It is well known that a considerably amount of time is spent on the iterative process of device sizing using simulations of analog circuits. During this process it is difcult to obtain optimal performance since many of the performance metrics are nonlinear functions of the design parameters, i.e., transistor sizes and bias currents. Optimization-based methods can in this case be used to achieve good trade-offs between several performance metrics. Furthermore optimization-based device sizing can be used to improve the design efciency for analog circuit design since the designer can work at a higher level of abstraction. There are a multitude of optimizing techniques that can be used for designing analog circuits [1], for example knowledge-based methods, global optimization methods, geometric programming, and gradient-based optimization methods. A knowledge-based system incorporate the know-how of an experienced analog designer. The advantage of this approach is the short computation time. Its drawback is the long set-up time for optimizing new structures since all circuits requires their own design rules. Further there is no guarantee that a global optimum is obtained. An example of a knowledge-based system is the IDAC program [2]. Global optimization methods on the other hand use optimization algorithms such as simulating annealing, genetic evolution, branch-and-bound, or exhaustive search. However, in practice non of these methods are guaranteed to nd the global optimum since the optimization time is limited [3]. In most cases, however, a good

solution is found within a short time. In our case we do not consider the computation time as a major problem. An optimization method that has become popular during the last few years is geometric programming [3], [4]. All design equations are formulated as posynomials, transforming the problem into a convex problem for which a global optimum is easily found. The drawback is that accurate design equations cannot be formulated as posynomials, thus, the use of posynomials restricts the transistor model to be of low accuracy. Furthermore, it is difcult to incorporate certain types of constraints and the use of simplied models does not ensure that all transistors operate in the proper region. Most classical optimization methods rely on gradient methods to nd a local optimum. These can also be used for optimizing the performance metrics of an analog circuit. In [6], [7] simplied models together with a minimax formulation of the problem were used to nd the DC operating points. Complete SPICE simulations can also be used in the iteration loop at a cost of very long simulation times [8]. Here we present on-going work to incorporate high accuracy transistor models in order to ensure accurate results. A minimax formulation of the optimization problem is currently used. The optimization scheme does not guarantee to nd the optimal solution, but a set of good solutions are found. Future work involves the implementation of more sophisticated optimization methods.

2. THE OPTIMIZATION PROCEDURE

A ow chart of the optimization algorithm is shown in Figure 1. The optimization procedure is divided into two steps: rst DC operating points meeting the DC constraint are found. Second, using the sizes generated by the rst step, the AC performance metrics are optimized. Both the optimization steps are currently formulated as minimax problems. These problems can be solved using gradient based methods to minimize the objective function. Since this formulation does not result in a convex problem we cannot guarantee to nd the global optimum. However, by initializing the optimization algorithm with several different starting points a set of good solution can be found.

Start

VS1

ID1

Generate initial values for transistor widths, node voltages, and bias currents Optimization

VG1

M1

W1,L VB1

VD1 VD2 I D2 VG2 W2,L M2 VB2

no

DC operating point found? yes Generate initial value for the ac optimization ac optimization

VS2

no

ac specification met? yes Save solution

no

Figure 2. An example circuit ble bias currents. Applying these equations together with constraints on the operation region of the transistors will result in a DC solution where all transistors are operating in their desired operation region.

2.2 The AC optimization procedure

When the DC operation points are found a second optimization step is used to assure that the AC constraints is met. The optimization parameters are the unity-gain frequency, the values of the components in compensation network. A simplied model for the small signal characteristics is currently used to limit the number of parameters and thereby the computation time in the AC optimization step. The drawback of this is naturally some loss in accuracy. The errors introduced by using a simplied model can be decreased by applying a model where more capacitors are included and that their capacitance are more accurately modelled [10]. However, as will be shown later, the errors introduced by using a simple model will not have a major impact on the ability to determine whether a solution meet the specication or not. When choosing what parasitics to include in the small signal model the size of the errors introduced in the cost function have been taken into consideration. For example a capacitor like C ds can be ignored since it is very small compared to the other capacitors and, thus, have small impact on the performance metrics. The transistors small signal parameters g m , g mbs , and g ds have been computed by taking the numerical derivative of the drain current modelled by the DC equations in the BSIM3 model. This model is used for an accurate computation of the performance metrics. The small signal parasitic capacitances used here are the C gs and the C gd . They have been modelled using a low-order approximation [11] adjusted to the characteristics of the capacitances from simulations. The capacitor models are expressed as 2 C gs = -- C ox WLk gs + a gs 3 C gd V db = k gd 1 + -------- s
(1)

Figure 1. A ow chart of the optimization procedure.

2.1 Finding the DC operating point

To nd suitable DC operation points an optimization technique are used to solve a non-linear system of equations. Each transistor are modelled as a black box. Given the node voltages V G , V S , V D , and V B along with the width and length of the transistor we can compute the drain source current, I D , the threshold voltage, V TH , and the saturation voltage, V DSAT . These parameters are in this case computed using the BSIM3v3 transistor model [9]. The transistor models are implemented directly into the program to avoid the time consuming task of calling an external simulator program like for example SpectreTM. Further, using the complete BSIM model for DC signals also provide high accuracy during the optimization process, ensuring that all transistors are biased in the proper operation region. Using a too simplied model results in large deviations in performance compared to simulations with high accuracy models. This phenomena can be encountered in programs using simple, but computational efcient, models used in for example [3]. The circuit topology itself introduces constraints on the node voltages and branch currents. For example, in Figure 2 the voltage at the drain of transistor M1 and M2 must be equal. Furthermore, in every node Kirchhoffs current law must be met. Starting from an initial guess of node voltages, transistor widths, and bias currents a minimax optimization routine is used to determine the currents in all branches. For example, in the circuit shown in Figure 2 the current going out of M1 must be the same as the current going into M2. The objective function is therefore to minimize the difference between those currents by adjusting the width of the transistors, the node voltages and the availa-

V M M

dd

bias network can be neglected. The output range is computed by the following expression. OR max V dd V DSAT 7
C

bias

OR min V DSAT 6
L

(4)

The minimum and maximum voltage at the input of the amplier is given by CMR max V dd V DSAT 5 V TH 1 CMR min V TH 3 + V DSAT 1 V TH 1
(5)

M M
3

ss

Figure 3. Single-ended two-stage operational amplier. where the factors k gs , a gs and k gd are used as tting parameters. Based on these AC parameters the frequency dependent properties of the circuit is computed. A large number of starting points can be evaluated in the optimization process. At the end the solution that best ts the design objectives is chosen.

In order to minimize the input offset voltage of the circuit the following relationship must be met. 2W 4 W 7 ------------------ = 1 W 5W 6
(6)

The common-mode rejection ratio at low frequencies is approximated by g m1 g m3 CMRR min 2 --------------------------------------( g ds1 + g ds3 )g ds5
(7)

3. DESIGN EXAMPLE
The differential input single-ended output two-stage operational transconductance amplier, OTA, used in this example is shown in Figure 3. This OTA is chosen in this design example since it is a commonly used all-purpose OTA. It has also a large output swing, high open loop voltage gain, and large common-mode input swing. The non-dominating pole, originating from the parasitic capacitance at the gate of transistor M6, is its main drawback. The load capacitor C L is set to be 5 pF and the power supply voltage is 3.3 V. Symmetry is obtain by setting the widths to be equal for transistors M1, M2 and M3, M4 respectively. The channel length, L, is set to 0.7 m for all transistors. Currently all constraints used in this design example are derived using simplied transistor models.

The power supply rejection ratio from the negative supply can approximately be expressed as g m1 g m6 negPSRR min --------------------------------------( g ds1 + g ds4 )g ds6
(8)

which is the PSRR at low frequencies. Constraints on the CMRR and PSRR for higher frequencies can easily be introduced if required, as for example in mixed-signal circuits where high frequency clock noise, etc., is injected into the power supplies. These high frequency constraints must be implemented in the AC optimization since they depend on the poles and zeros of the OTA.

3.2 AC Constraints
In the design of an amplier it is common to have a specication on for example DC gain, unity-gain frequency, phase margin and so on. To meet the specication, constraint must be set during the AC optimization phase. A simplied model for the transfer function of a twostage operational amplier is given by A0 N ( s ) A0 ( 1 + s z1 ) A ( s ) = ----------------------------------------------------------------------------------- = ----------------(9) D(s) s s s s 1 + ---- 1 + ---- 1 + ---- 1 + ---- p 1 p 2 p 3 p 4 where A0 is the DC gain, z1 is the zero, pi are the poles, N(s) is the numerator and D(s) is the denominator. The DC gain can be expressed as g m2 g m6 A 0 = ------------------------- ------------------------g ds2 + g ds4 g ds6 + g ds7
(10)

3.1 DC Constraints
To meet different types of performance measures a set of constraints must be specied. A short description of the constraints that where used in this example is given below. A constraint is that all transistors must operate in the saturation region. To guarantee this the following wellknown relationship must be met for each transistor V GS > V T V DS V DSAT
(2)

where V DSAT , is the minimum drain source voltage for each transistor. The quiescent power dissipation of the circuit is given by P max ( V dd V ss ) ( I D5 + I D7 + I D8 )
(3)

if transistor M5 is assumed to have zero output conductance. Furthermore, the dominant pole is given by g m2 p 1 = -----------A0 C c
(11)

In, for example, analog lters where a single bias network are used for several OTAs the power dissipation in the

The pole originating from the output stage is g m6 p 2 = ------------------------------------------------------C c ( C 1 + C TL ) + C 1 C TL

(12)

4. PERFORMANCE OF THE OPTIMIZATION

All simulations and optimizations where carried out with parameters from a 0.35 m CMOS process. The simulations were performed in the Cadence SpectreTM simulator. The two-stage amplier have been optimized to meet one specication. Several solutions were found and simulated in the SpectreTM simulator to evaluate the performance of the optimization program. At the end the best solution, i.e., the solution with the best value of the objective function is chosen.

where C1, the parasitic capacitance at the gate of transistor M6, can be expressed as C 1 = C gs6 + C db2 + C db4 + C gd 2 + C gd 4
(13)

and CTL, the total capacitance at the output node, is given by C TL = C L + C db6 + C db7 + C dg6 + C dg7
(14)

Only Cgs and Cdb are implemented in the optimization program and therefore the AC properties will not have the same accuracy as for example in the SpectreTM simulator. The third pole is introduced in the current mirror and it is given by g m3 p 3 = ------(15) C2 where the capacitance C2 at the gate of transistor M3 is given by C 2 = C gs3 + C gs4 + C db1 + C db3 + C db4 The compensation pole is given by 1 p 4 = ----------C 1 Rc and the compensation zero is 1 z 1 = -------------------------------1 ------- R C c c g m6
(18) (17) (16)

4.1 Specication
The specication together with the simulation results is shown in Table 1. In this case a low-power specication was chosen. The objective function was to maximize the unity-gain frequency. The sizes of the transistors in the OTA is shown in Table 2.
Table 1. Specication of the two-stage OTA. Performance measure DC gain Unity-gain frequency Phase margin Slew rate negative PSRR Power dissipation Output range Common-mode range Specication Optimized circuit > 80 dB >100 MHz > 60 83.6 dB 105.5 MHz

61.3 >100 V s 126 V s

84.6 dB 92.2 dB 1.9mW 0.15 - 3.15 V 0.0 - 2.4 V > 80 dB < 2 mW 0.4 - 2.8 V 0.0 - 2.0 V

Common-mode rejection ratio > 60 dB

The zero can be placed at different locations. For example far away in the right hand plane, at innity, or in the left hand plane at z 1 = 1.2 u , depending of the value of Rc. In this design example the zero is chosen to be in the left hand plane about 1.2 times the unity-gain frequency of the amplier. This position of the zero will increase the phase margin and the unity-gain frequency [11]. At the unity-gain frequency the magnitude of the gain equals unity. This can be reformulated as A 0 N ( jw u ) D ( j u ) = 0 The phase margin can be found according to M u u u u u = + atan ----- atan ----- atan ----- atan ----- atan ----(20) p1 z1 p2 p3 p4
(19)

4.2 Device sizes

The sizes of the transistors, compensation capacitor and resistor, and the bias current are shown in the Table 2 for the best solution.
Table 2. The device sizes of the OTA. Variable W1=W2 W3=W4 W5 W6 W7 Circuit Variable Circuit 178.5 m 1.98 pF 918.2 104.7 A 0.7 m 252.9 m W8 79.6 m Cc 373.1 m Rc 187.4 m Ibias 409.5 m L

Another performance measures of interest is the slew rate which can be approximated as I D5 I D7 SR = min ------- , --------------------- C c C c + C TL
(21)

One problem with the approach given above is to nd the poles and zeros of the circuit. Usually it is easier to derive the transfer function than factorizing the numerator and denominator into accurate expressions for the poles and the zeros. In our case it is possible to compute the unitygain frequency and the phase margin directly from the transfer function [10].

5. COMPARISON WITH SPECTRETM SIMULATIONS

Due to the use of simplied the small signal model some differences between the resulting performance of the optimization program and the SpectreTM simulator is

10 8

relative error in per cent

6 4 2 0 2 4 6 8

implementation of a corresponding layout generator will allow back annotation of parasitic properties introduced in the layout phase and improve the design efciency signicantly.

7. CONCLUSION
A rst version of an optimization-based device sizing program has been implemented. The program is capable to size the transistors of analog circuits, such as operational ampliers, to meet certain performance metrics. We can not guarantee that the optimizer nds the global optimum since the problem is not convex, but it can generate a set of good solutions. Recongurating the optimization program for a new circuit can be done in a reasonable short time. The program uses the complete BSIM3v3 transistor model for the DC operation points to ensure that each transistor are biased to operate in the desired operation region. Simplied small signal model for the transistors are used to decrease the AC optimization time. The designed circuits have been veried in a SpectreTM simulation to evaluate its performance.

10

20

40

60

80

100

120

solution number

Figure 4. Deviation of the unity-gain frequency between

10 8

relative error in per cent

6 4 2 0 2 4 6 8

REFERENCES
0 20 40 60 80 100 120

10

solution number

Figure 5. DC gain deviations between optimized and obtained. The discrepancy for the unity-gain frequency and the DC gain have been evaluated for about 100 different solutions. The results are shown in Figure 4 and Figure 5, respectively. The deviation in the unity-gain frequency can be explained by three causes. The rst one is the simplied models used for the poles and zeros of the circuit. Second, all parasitic capacitances in the small signal model for the transistor are not incorporated in the optimization program. The last cause is the simplied modelling of the capacitors used in the current version of the optimization program. The deviation in the DC gain can be explained by the use of the simplied model for the DC gain. Furthermore, the computation of the g m , g mbs , and g ds values differs a little with the one used in the simulator. These parameters are derived by taking the numerical derivative of the current with respect to V GS , V BS , and V DS respectively in the operation point.

6. FUTURE WORK
The optimization procedure used in this paper is divided into two different steps. On-going work is to integrated both optimization steps into a single step. A single optimization step makes it possible to minimize the power dissipation for the specication. Future work will include optimization of more complex performance metrics. The

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