IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

3, MARCH 2012

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A DSTATCOM Topology With Reduced DC-Link Voltage Rating for Load Compensation With Nonstiff Source
Srinivas Bhaskar Karanki, Nagesh Geddada, Student Member, IEEE, Mahesh K. Mishra, Senior Member, IEEE, and B. Kalyan Kumar, Member, IEEE

AbstractThe distribution static compensator (DSTATCOM) is used for load compensation in power distribution network. In this paper, a new topology for DSTATCOM applications with nonstiff source is proposed. The proposed topology enables DSTATCOM to have a reduced dc-link voltage without compromising the compensation capability. It uses a series capacitor along with the interfacing inductor and a shunt lter capacitor. With the reduction in dc-link voltage, the average switching frequency of the insulated gate bipolar transistor switches of the DSTATCOM is also reduced. Consequently, the switching losses in the inverter are reduced. Detailed design aspects of the series and shunt capacitors are discussed in this paper. A simulation study of the proposed topology has been carried out using power systems computer-aided design simulator and the results are presented. Experimental studies are carried out to verify the proposed topology. Index TermsAverage switching frequency, dc-link voltage, distribution static compensator (DSTATCOM), hybrid topology, nonstiff source.

I. INTRODUCTION

HE proliferation of power electronics devices, nonlinear loads, and unbalanced loads has degraded the power quality in the power distribution network [1]. To improve the quality of power, active power lters have been proposed [2][4]. The distribution static compensator (DSTATCOM) is a shunt active lter, which injects currents into the point of common coupling (PCC) (the common point where load, source, and DSTATCOM are connected) such that the harmonic ltering, power factor correction, and load balancing can be achieved. In practice, the load is remote from the distribution substation and is associated with feeder impedance. In the presence of feeder impedance, the inverter switchings distort both the PCC voltage and the source currents. In this situation, the source is termed as nonstiff. If the same control algorithm for the stiff sources is used for the nonstiff sources, the reference currents generated will be erroneous; the load compensation using state feedback control of

Manuscript received March 18, 2011; revised July 11, 2011; accepted July 22, 2011. Date of current version February 7, 2012. This work was supported by the Department of Science and Technology, India, under Project Grant SR/S3/EECE/048/2008. Recommended for publication by Associate Editor J. H. R. Enslin. The authors are with the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600036, India (e-mail: balu.karanki@gmail.com; nagesh.mselectrical@gmail.com; mahesh@ee.iitm. ac.in; bkalyan@ee.iitm.ac.in). Digital Object Identier 10.1109/TPEL.2011.2163946

DSTATCOM with shunt lter capacitor gives, however, better results [5], [6]. The state feedback control of the shunt lter capacitor eliminates the switching frequency components in the terminal voltages and source currents. The compensation performance of any active lter depends on the voltage rating of dc-link capacitor [7]. In general, the dc-link voltage has much higher value than the peak value of the line-to-neutral voltages. This is done in order to ensure a proper compensation at the peak of the source voltage. In [8], the authors discuss the current distortion limit and loss of control limit, which states that the dc-link voltage should be greater than or equal to 6 times the phase voltage of the system for distortion-free compensation. When the dc-link voltage is less than this limit, there is insufcient resultant voltage to drive the currents through the inductances so as to track the reference currents. Reference value of the dc-bus capacitor voltage mainly depends upon the requirement of reactive power compensation of the active power lter [9], [10]. The primary condition for reactive power compensation is that the magnitude of reference dc-bus capacitor voltage should be higher than the peak of source voltage at the PCC [11]. Due to these criteria, many researchers have used a higher value of dc capacitor voltage based on their applications [12][17]. With the high value of dc-link capacitor, the voltage source inverter (VSI) becomes bulky and the switches used in the VSI also need to be rated for higher value of voltage and current. This, in turn, increases the entire cost and size of the VSI. A few attempts have been made in the literature to reduce the dclink voltage storage capacity. In [18] and [19], a hybrid lter has been discussed for motor drive applications. The lter is connected in parallel with diode rectier and tuned at seventh harmonic frequency. Although an elegant work, the design is specic to the motor drive application and the reactive power compensation is not considered, which is an important aspect in DSTATCOM applications. In this paper, a new DSTATCOM topology with reduced dclink voltage is proposed. The topology consists of two capacitors: one is in series with the interfacing inductor of the active lter and the other is in shunt with the active lter. The series capacitor enables reduction in dc-link voltage while simultaneously compensating the reactive power required by the load, so as to maintain unity power factor without compromising DSTATCOM performance. The shunt capacitor, along with the state feedback control algorithm, maintains the terminal voltage to the desired value in the presence of feeder impedance.

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Fig. 1. Equivalent circuit of the neutral clamped VSI topology-based DSTATCOM.

Fig. 2. Equivalent circuit of the proposed neutral clamped VSI topology-based DSTATCOM (hybrid lter).

The simulation studies are carried out using a power systems computer-aided design (PSCAD) simulator, and detailed results are presented in this paper. A prototype of a three-phase DSTATCOM is developed in the laboratory to verify the proposed concept, and the detailed results are presented. II. CONVENTIONAL AND PROPOSED TOPOLOGIES OF DSTATCOM In this section, the conventional and proposed topologies of the DSTATCOM are discussed in detail. Fig. 1 shows the power circuit of the neutral clamped VSI topology-based DSTATCOM which is considered the conventional topology in this study. Even though this topology requires two dc storage devices, each leg of the VSI can be controlled independently and tracking is smooth with less number of switches when compared to other VSI topologies [20]. In this gure, vsa , vsb , and vsc are source voltages of phases a, b, and c, respectively. Similarly, vta , vtb , and vtc are the terminal voltages at the PCC. The source currents in three phases are represented by isa , isb , and isc and load currents are represented by ila , ilb , and ilc . The shunt active lter currents are denoted by if a , if b , if c , and io represents the current in the neutral leg. Ls and Rs represent the feeder inductance and resistance, respectively. The interfacing inductance and resistance are represented by Lf and Rf , respectively. The load constituted of both linear and nonlinear loads are as shown in this gure. The dc-link capacitors and voltages across them are represented by Cdc1 = Cdc2 = Cdc and Vdc1 = Vdc2 = Vdc , respectively. The current through the dc link is represented by the idc . In this topology, the voltage across each dc-link capacitance is chosen as 1.6 times the peak value of the source voltages as given in [20]. Fig. 2 shows the equivalent circuit of the proposed neutral clamped VSI topology-based DSTATCOM. It is a combination of the conventional DSTATCOM topology with a capacitor Cf in series with the interfacing shunt branch of the active lter and a capacitor Csh in shunt with the active lter. This topology is referred to as hybrid topology. The passive capacitor Cf has the capability to supply a part of the reactive power required by the load, and the active lter will compensate the balance reactive power and the harmonics present in the load. The addition of capacitor in series with the interfacing inductor of the conventional

topology will signicantly reduce the dc-link voltage requirement and consequently reduces the average switching frequency of the switches. This concept will be illustrated with analytic description in the following section. The shunt capacitor Csh largely eliminates the switching frequency components of the VSI in the terminal voltages and source currents using state feedback control. The design of the series capacitor Cf and the shunt capacitor Csh have signicant effect on the performance of the compensator. These are given in the next section. III. DESIGN OF VSI PARAMETERS The parameters of the VSI need to be designed carefully for better tracking performance. The most important parameters that need to be taken into consideration while designing conventional VSI are dc-link voltage Vdc , dc storage capacitor Cdc , interfacing inductance Lf , and switching frequency fsw . A detailed design procedure of VSI parameters is given in [21]; based on the following equations, the parameters of the conventional VSI topology are chosen. The dc-link capacitor value is given by Cdc = (2X X/2)nT (1.8Vm )2 (1.4Vm )2 (1)

where Vm is the peak value of the source voltage, X is the kVA rating of the system, n is the number of cycles, and T is the time period of each cycle. The interfacing inductance is given by Lf = where h= k1 (2m2 1) fswm ax k2 4m2 (3) 1.6Vm 4hfswm ax (2)

where k1 and k2 are proportionality constants, fswm ax is the maximum switching frequency of the switch, fswm in is minimum switching frequency of the switch, and m is given by m= 1 1 fswm in /fswm ax . (4)

As mentioned earlier, the dc-link voltage reference (Vdcref ) of the conventional VSI topology has been taken as 1.6 Vm for

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TABLE I SYSTEM PARAMETERS

problem, which is explained in the next section to simultaneously force the terminal voltage and the source current to be sinusoidal [23]. B. Design of Series Capacitor Cf for the Proposed VSI Topology The fundamental lter current drawn by the shunt lter capacitor is neglected while designing the series capacitor value. This is because the impedance between the PCC and ground becomes very high when Csh is chosen much smaller than Csho at fundamental frequency, and thus, the fundamental current drawn by the shunt capacitor is negligible. The design of the Cf depends upon the value to which the dc-link voltage is reduced. In general, loads with only nonlinear components of currents are very rare, and most of the electrical loads are combination of the linear inductive and nonlinear loads. Under these conditions, the proposed hybrid topology will work efciently. The design of the value of Cf is carried out at the maximum load current, i.e., with the minimum load impedance to ensure that the designed Cf will perform satisfactorily at all other loading conditions. If Sm ax is the maximum kVA rating of a system and Vbase is the base voltage of the system, then the minimum impedance in the system is given as Zm in =
2 Vbase = |Rl + jXl | (say). Sm ax

each capacitor [20], [21]. Consider a three-phase system with 230-V line-to-neutral voltage. The hysteresis band h is taken as 0.5 A. From (2), the interfacing inductance Lf is computed to be 26 mH. The base kVA rating of the system is taken as 15 kVA. Using (1), Cdc is computed and found to be 3300 F. The system parameters are given in Table I for the conventional VSI topology. A. Design of Shunt Capacitor Csh for the Proposed VSI Topology In the presence of the feeder impedance, i.e., nonstiff source in the system, the terminal voltages are distorted due to unbalance and nonlinear load currents. Thus, these voltages as such can no longer be used to generate the reference quantities. In order to improve the performance, positive-sequence voltages at the terminal are extracted using the power-invariant instantaneous symmetrical transformation and are used for generating the reference currents [5], [22]. However, the terminal voltages are still contaminated with the inverter switching frequency components. These switching frequency components can be eliminated by providing a low impedance path using a lter capacitor Csh , connected in shunt at the PCC in each phase as shown in Fig. 2. While designing the shunt capacitor, it should be ensured that the feeder reactance Ls and the shunt capacitor Csh do not resonate at the fundamental frequency. If the lter capacitor resonate with the feeder reactance at a frequency r , then we get Cshr = 1
2 r Ls

(6)

In order to achieve the unity power factor, the shunt lter current needs to supply the required load reactive current, i.e., the imaginary part of the lter current should be equal to the imaginary part of the load current. The lter current and load current in a particular phase are given as follows: I lter = I load = Vinv1 Vt1 Rf + j(Xlf Xcf ) Vt1 Rl + jXl (7) (8)

where Xlf = 2f Lf , Xl = 2f Ll , Xcf = 1/2f Cf , and f is the supply frequency of fundamental voltage. Neglecting the interfacing resistance and equating the imaginary parts of the aforementioned equations gives Vt1 Xl Vinv1 Vt1 2 + X 2 = (X X )2 (Xlf Xcf ) Rl lf cf l (9)

(5)

When r is equal to fundamental frequency 0 , the aforementioned capacitance is denoted as Csho . Since resonance between the feeder reactance and shunt lter capacitor should be avoided at fundamental frequency, Csh should not be chosen near to Csho . If Csh is very large, the impedance between the PCC and ground becomes very small and results in high lter currents, Csho which will, in turn, increase the source currents, so Csh is not valid. Thus, Csh is chosen as 50 F at 50 Hz as fundamental frequency for feeder impedance Ls = 0.01 H [5]. A straightforward insertion of the shunt passive capacitor at the PCC may lead to stability issues and also with the increase in the capacitance value, the source currents and terminal voltages increase. The use of state feedback is one option to solve the

where Vinv1 and Vt1 are the line-to-neutral rms voltage of the inverter and the PCC voltage at the fundamental frequency, respectively. The fundamental component of inverter voltage in terms of dc-link voltage is given as follows [24]: Vinv1 = 0.612Vdc . 3 (10)

In general, if the lter current if needs to ow from the inverter terminal to the PCC, the voltage at the inverter terminal should be at a higher potential. Due to this reason, in conventional VSI topologies, the dc-link voltage is maintained higher than the voltage at the PCC. Equations (11) and (12) give the Kirchhoffs voltage law along the lter branch for conventional

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Fig. 3.

Frequency response of passive lter components of the DSTATCOM.

Fig. 4.

Single-line diagram of the proposed DSTATCOM.

topology and the proposed hybrid topology, respectively, dif + Rf if dt dif + Rf if if dt vt = Lf dt uVdc vt = Lf dif + Rf if dt (11)

x = [i1

i2

i3

vt

vcf ]t .

(13)

uVdc

1 Cf

The circuit shown in Fig. 4 contains three forcing functions: the source voltage vs , the nonlinear load current Ih , and switching variable u. The u is replaced by the continuous time variables uc and the control vector is dened as u = [uc ]. The state-space equation of the circuit can be written as x = Ax + B1 vs + B2 u + B3 Ih where (15) (14)

(uVdc vcf ) vt = Lf

(12)

where u attains values of 1 or 1 depending on the switching of the inverter. In (12), the fundamental voltage across the capacitor (vcf 1 ) adds to the inverter terminal voltage (uVdc ) when the load is inductive in nature. This is because, when the load is inductive in nature, the fundamental of the lter current lags the voltage at the PCC by 90 for reactive power compensation, and thus, the fundamental voltage across the capacitor again lags the fundamental lter current by 90 . Finally, the fundamental voltage across the capacitor will be in phase opposition to the voltage at the PCC. Thus, the fundamental voltage across the capacitor adds to the inverter terminal voltage. This allows us to rate the dc-link voltage at lower value than conventional design. The designer may choose the value of dc-link voltage to be reduced, such that the LC lter in the active lter leg of each phase offers minimum impedance to the fundamental frequency component and higher impedance for switching frequency components. From the system parameters mentioned in Table I, phase-a load impedance is chosen as Zm in and the dc-link voltage is chosen to be 300 V. Using (9), the value of the capacitor Cf is obtained to be 65 F. The dc-link voltage is chosen to be 300 V, such that the resultant capacitance along with the inductor forms an LC lter in the active lter branch, which provides a minimum impedance at the lower order frequencies as shown in Fig. 3. IV. STATE FEEDBACK CONTROL The single-line diagram of the proposed DSTATCOM is shown in Fig. 4. To derive the state-space model of the system in Fig. 4, we choose ve local variables (i.e., three loop currents and two capacitor voltages). Now, the state vector is dened as follows:

0 A= 0 1/Csh 0

Rs /Ls

0 Rf /Lf 0 1/Csh 1/Cf

0 0 Rl /Ll 1/Csh 0 0 ,

1/Ls 1/Lf 1/Lf 0 0

1/Lf 0 0 0 .

1/Ls 0 B1 = 0 , 0 0

Vdc /Lf B2 = 0 0 0

0 0 B3 = 0 1/Cf 0

The state variables can be written as network parameters as follows: is = i1 ; ish = i1 i2 i3 ; vcf = vcf ; il = i3 ; (16)

if = i3 i1 ;

vshf = vt .

A transformed state vector z, which relates the state vector x with the network parameters using (16), can be written as 1 0 1 0 0 if ish 1 1 1 0 0 (17) 0 1 0 0 x = P x. z = il = 0 vt 0 0 0 1 0 vcf 0 0 0 0 1

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The state-space representation of the system given in (15) is transformed by using (17) as z = P AP 1 z + P B1 vs + P B2 u + P B3 Ih = z + 1 vs + 2 u + 3 Ih . (18)

where =
j =a,b,c

2 vtj , = tan / 3.

Assuming that we have full control over u, a particle swarm optimization (PSO)-based state feedback controller is designed to ensure robustness under parametric variations [25], [26]. The control law is dened as uc = K(z zref ) (19)

where zref is the desired state vector. An optimization function can be developed to nd the optimal feedback gains to maximize the left shift and increase the damping ratio of the eigenvalues of the state matrix given in (18). The optimization function is given as
N

minf =
i=1

[Re[i (i 1i K)] i (i 1i K)]

(20)

Here, Plavg is the average load power, Ploss denotes the switching losses and ohmic losses in actual compensator and it is generated using a capacitor voltage PI controller. The term Plavg is obtained using a moving average lter of one cycle window of time T in seconds. The term is the desired phase angle between the source voltage and current. In this paper, the load currents are unbalanced and distorted; these currents ow through the feeder impedance and make the voltage at PCC unbalanced and distorted. However, if the voltages are unbalanced and distorted, it is not possible to get balanced and sinusoidal currents after compensation using (21). To remove this limitation of the algorithm, fundamental positive+ + + sequence voltages vta1 (t), vtb1 (t) and vtc1 (t) of the distorted terminal voltages are extracted [22]. Now, the voltages vta (t), + + vtb (t), and vtc (t) in (21) are replaced by vta1 (t), vtb1 (t), and + vtc1 (t), respectively. Therefore, the expressions for reference compensator currents become i a = ila i = ila f sa i b = ilb i = ilb f sb i c = ilc i = ila f sc
+ + + vta1 + (vtb1 vtc1 ) (Plavg + Ploss ) + 1 + + + vtb1 + (vtc1 vta1 ) (Plavg + Ploss ) + 1 + + + vtc1 + (vta1 vtb1 ) (Plavg + Ploss ) + 1

subject to Km in1 < K1 < Km ax1 , Km in2 < K2 < Km ax2 .

Here K = [K1 K2 0 0 0] and N is the number of possible operating conditions. K is the feedback controller gain vector having two nonzero elements. It is not possible to nd the reference of the load current, so partial feedback is considered. Similarly, the feedback for the terminal voltage vt and series capacitor voltage vcf are considered to be zero, as they are dependent on the other network parameters (if and ish ). Hence, only two feedback gains have been used. The terms i and i in (19) are the critical eigenvalue and damping ratio of the state transition matrix (i 1i K) for ith operating condition. The optimization function (19) is formulated to nd an optimal value of K, subjected to lower and upper bounds, to maximize the left shift of the real part of the critical eigenvalues and its damping ratio for each and every possible operating condition. PSO has been used to solve the optimization problem given in (19). The parameters for the PSO implementation are given in [27] and [28]. In this PSO implementation, 50 particles and 100 iterations are considered. The feedback gains are found to be K = [13.6759 6.5009 0 0 0]. V. GENERATION OF REFERENCE COMPENSATOR CURRENTS UNDER UNBALANCED AND DISTORTED VOLTAGES In this paper, the reference currents are generated using instantaneous symmetrical component theory [29] and are given as i a = ila i = ila f sa i b = ilb i f sb i c = ilc i f sc vta + (vtb vtc ) (Plavg + Ploss ) vtb + (vtc vta ) (Plavg + Ploss ) = ilb vtc + (vta vtb ) (Plavg + Ploss ) (21) = ila

(22) where =
j =a,b,c

+ (vtj 1 )2 , = tan / 3.

The aforementioned algorithm gives balanced source currents after compensation irrespective of unbalanced and distorted supply. The positive-sequence voltages that are extracted from the terminal voltages vta , vtb , and vtc are the reference lter ca pacitor voltages and are denoted by vsha , vshb , and vshc . The reference lter capacitor currents are computed using these reference voltages and are given as follows: isha vsha i = Csh ej 90 vshb . (23) shb ishc vshc Once the reference quantities zref and the actual state vectors z are obtained from the measurements, the control signal for each phase is then computed using the reference and actual state vectors in the respective phases with the appropriate control gain K. The switching commands for the VSI switches are generated using the hysteresis band current control method [30]. Hysteresis current controller schemes are based on a feedback loop, generally with two-level comparators. The switching commands (Sa , Sa , Sb , Sb , Sc , Sc ) are issued whenever the limit

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Fig. 5. Simulation results. (a) Load currents before compensation. (b) Terminal voltages before compensation.

(lim) exceeds a specied tolerance band h. Unlike the predictive controllers, the hysteresis controller has the advantage of peak-current-limiting capacity apart from in addition to other merits such as extremely good dynamic performance, simplicity in implementation, and independence from load parameter variations. The disadvantage with this hysteresis method is that the converter switching frequency is highly dependent on the ac voltage and varies with it. The switching signals generated for the VSI are as follows: uc = K(z zref ) u = hys(K(z zref )). (24)

If h lim then hys(h) = 1, bottom switch is turned ON, whereas top switch is turned OFF (Sa = 0, Sa = 1). If h lim then hys(h) = 1, top switch is turned ON, whereas bottom switch is turned OFF (Sa = 1, Sa = 0). The control circuitry is simple for both topologies because only three switching commands are to be generated. These three signals along with the complementary signals will control all the switches of the inverter. VI. SIMULATION RESULTS In order to validate the proposed topology, simulation is carried out using graphic-driven simulation software PSCAD. The PSO-based feedback controller gains are computed ofine. These gains are used to generate switching commands to the gates of the inverter as given in (24). The same system parameters that are given Table I with Csh = 50 F and Cf = 65 F are used in PSCAD simulation. The simulation results for both the conventional topology and the proposed topology are presented in this section for better understanding and comparison between both the topologies. The load currents and terminal (PCC) voltages before compensation are shown in Fig. 5. The load currents are unbalanced
Fig. 6. Simulation results using conventional topology. (a) Source currents after compensation. (b) Filter currents. (c) DC capacitor voltages (top and bottom). (d) Voltage across the interfacing inductor in phase-a. (e) Terminal voltages after compensation.

and distorted; the terminal voltages are also unbalanced and distorted because these load currents ow through the feeder impedance in the system. Fig. 6 gives the simulation results of the DSTATCOM using the conventional VSI topology. The source currents after compensation are balanced and sinusoidal as shown in Fig. 6(a). These currents still contain the switching frequency of the inverter. The three-phase compensator currents are depicted in Fig. 6(b). The dc-link voltages across the top

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and bottom dc-link capacitors are shown in Fig. 6(c); using PI controller, the voltage across both capacitors are maintained constant to the reference value of 520 V as shown in the gure. The voltage across the interfacing inductor in phase-a is shown in Fig. 6(d). The peak-to-peak voltage across the inductor is 820 V. The terminal voltages contains the switching frequency components of the inverter and are shown in Fig. 6(e). Fig. 7 gives the simulation results with the proposed hybrid topology. The value of the capacitor Cf in the active lter branch is chosen to be 65 F and the reference dc-link voltage is 300 V for each capacitor as discussed earlier. The shunt capacitor Csh is taken as 50 F. The voltage across the capacitor in phase-a (vcf a ) is shown in Fig. 8. This gure also shows the phase-a terminal voltage vta and the voltage across the top dc storage capacitor Vdc1 . From the gure, it is clear that the voltage across the capacitor is in phase opposition to the terminal voltage. According to (12), the voltage across the capacitor eventually adds to the dc-link voltage and injects the required compensation currents into the PCC. The reason beyond showing phase-a capacitor voltage is that the design of the reference dc-link voltage is based on phase-a lter current, which has the maximum lter current among the three phases. The source currents after compensation using proposed topology are shown in Fig. 7(a). The compensator currents are displayed in Fig. 7(b), which are identical to the currents using the conventional topology. The dc-link voltages across the top and bottom dc-link capacitors are shown in Fig. 7(c). The voltage across the inductor is shown in Fig. 7(d); the peak-to-peak voltage is 630 V, which is far lower than the voltage across the inductor using the conventional topology. As the voltage across the inductor is high in case of the conventional topology, the rate of rise of lter current dif /dt will be higher than that of the proposed topology. This will allow the lter current to hit the hysteresis boundaries at a faster rate and increases the switching, whereas in proposed hybrid topology, the number of switchings will be less. Thus, the average switching frequency of the switches in the proposed topology will be less as compared to the conventional topology. Since the average switching is less, the switching loss will also decrease in the proposed topology. One more advantage of having less voltage across the inductor is that the hysteresis band violation will be less. This will improve the quality of compensation and total harmonic distortion (THD) will be less in the proposed topology. The terminal voltages after compensations are shown in Fig. 7(e), which are free from the switching frequency components of the inverter. These switching frequency components are absorbed by the shunt capacitor by using state feedback control as discussed in Section III. The shunt capacitor provides a low impedance path at the high switching frequency. The THD of the source currents and terminal voltages before and after compensation in all the three phases are given in Table II. Table III gives the average switching frequency in each leg of the inverter. This clearly shows the proposed hybrid topology performance is better than the conventional topology with a less dc-link voltage, reduction in switching operation, and regular tracking of reference compensator currents.

Fig. 7. Simulation results using proposed hybrid topology. (a) Source currents after compensation. (b) Filter currents. (c) DC capacitor voltages (top and bottom). (d) Voltage across the interfacing inductor in phase-a. (e) Terminal voltages after compensation.

Fig. 8. Voltage across top dc capacitor, series lter capacitor, and terminal voltage in phase-a.

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TABLE II THD OF SOURCE CURRENTS AND TERMINAL VOLTAGES

TABLE III AVERAGE SWITCHING FREQUENCY OF THE INVERTER SWITCHES

VII. EXPERIMENTAL STUDIES The efcacy of the proposed scheme is veried with experimental studies. A DSP-based prototype of the three-phase DSTATCOM has been developed in the laboratory. The system parameters for the state feedback controller of the DSTATCOM are the same as given in Table I, with the source voltage rms value of 100 V. The same PSO gains that are used in the simulation studies can be used here also, as the matrix (A, B1 , B2 , and B3 ) do not vary. The experimental setup uses the SEMIKRON to build a two-pulse inverter for realizing the shunt lter currents. The feedback gains for the PSO methods are calculated ofine and are used in experimental studies. DSP TMS320F2812 is used to process the data in the digital domain. The signal and logic level consist of Hall effect voltage and current transducers, signal conditioning and protection circuits, along with isolated dc power supplies. A real-time algorithm has been implemented in the Code Composer Studio on the host computer. The DSP acquires the signals and process them to generate the shunt reference currents. The switching commands generated by the DSP are issued through the general-purpose input and output port. In this section, both the conventional and proposed topologies are developed and experiments are performed for comparison. For the conventional topology, the dc-link voltage for each capacitor is maintained to be 225 V (1.6 Vm ). The dc-link voltage for each capacitor is taken as 115 V for the proposed topology, such that the series capacitor value is 65 F same as simulation studies from (9). The shunt capacitor is chosen to be 50 F in the experimental studies. The load currents and the terminal voltages before compensation are shown in Fig. 9(a) and (b), respectively. The source and load currents are the same as before compensation; they are distorted and unbalanced. The terminal voltages are also distorted because of the feeder impedance. The THD comparison of the source currents and terminal voltages before compensation is given in Table IV. The three-phase source currents after compensation using conventional topology DSTATCOM are shown in Fig. 10(a). The source currents are balanced and sinusoidal, though the switching frequency components are still present. The lter currents that are injected into the

Fig. 9. Experimental results. (a) Load currents before compensation. (b) Terminal voltages before compensation. TABLE IV THD OF SOURCE CURRENTS AND TERMINAL VOLTAGES

PCC to make the source currents balanced and sinusoidal are shown in Fig. 10(b). The terminal voltages after compensation are shown in Fig. 10(c) along with the total dc-link voltage (Vdc = Vdc1 + Vdc2 ) across the dc capacitors. The PI controller is used to maintain the dc-link voltage at 225 V across each dc capacitor. The terminal voltages contains the switching frequency components of the inverter. The voltage across the interfacing inductor in phase-a is shown in Fig. 10(d), and the three-phase switching pulses for the top switches of the inverter are shown in Fig. 10(e). The source currents after compensation using the conventional topology DSTATCOM with a reduced dc-link voltage (115 V across each dc capacitor) are shown in Fig. 11. The peak of the source currents are not tracked properly because the dc-link voltage is not sufcient to drive the lter currents at the peak portion of the source voltages. The experimental results with the proposed topology are shown in Fig. 12. The dc-link voltage across each dc capacitor is maintained at 115 V as mentioned earlier. The source currents after compensation are shown in Fig. 12(a); they are balanced and sinusoidal. The switching frequency components

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Fig. 10. Experimental results using conventional topology. (a) Source currents after compensation. (b) Filter currents. (c) Terminal voltages after compensation and dc-link voltage (V d c 1 + V d c 2 ). (d) Voltage across the interfacing inductor in phase-a. (e) Switching in three phases.

Fig. 12. Experimental results using the proposed topology. (a) Source currents after compensation. (b) Filter currents. (c) Terminal voltages after compensation and dc-link voltage (V d c 1 + V d c 2 ). (d) Voltage across the interfacing inductor in phase-a. (e) Switching in three phases.

Fig. 11. Source currents after compensation with reduced dc-link voltage using the conventional topology.

of the inverter are removed with the help of the shunt capacitor using the state feedback controller. The lter currents are shown in Fig. 12(b) and the terminal voltages along with the total dc-link voltage are shown in Fig. 12(c). The total dc-link voltage is maintained at 230 V and the terminal voltages are free from the inverter switching frequency components. The voltage across the interfacing inductor in phase-a is shown in Fig. 12(d); the peak-to-peak voltage across the interfacing inductor in the proposed topology is 140 V, which is less than the conventional topology voltage of 250 V. The three-phase switching pulses

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TABLE V AVERAGE SWITCHING FREQUENCY OF THE INVERTER SWITCHES

for the top switches of the inverter are shown in Fig. 12(e); the average switching frequency is less when compared to the conventional topology-based DSTATCOM. The THD comparison of the source currents and the terminal voltages after compensation is given in Table IV. The average switching frequencies are compared in Table V. From the experimental results, the proposed topology gives a reduced THD both in the source currents and terminal voltages with a reduced dc-link voltage along with reduction in average switching frequencies. VIII. CONCLUSION A new hybrid DSTATCOM topology has been proposed in this paper, which has the capability of compensating the load at a lower dc-link voltage under nonstiff source. Design of the lter parameters is explained in detail. The proposed method is validated through simulation and experimental studies in a 3- distribution system with the neutral clamped DSTATCOM topology. Detailed comparative studies are made for the conventional and proposed hybrid DSTATCOM topologies. From this study, it is found that the proposed topology has less average switching frequency, less THDs in the source currents and terminal voltages with reduced dc-link voltage as compared to the conventional DSTATCOM topology. REFERENCES
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Srinivas Bhaskar Karanki received the B.Tech. degree from Acharya Nagarjuna University, Guntur, India, in 2007. He is currently working toward the Ph.D. degree in the Department of Electrical Engineering, IIT Madras, Chennai, India. His research interests include power quality, power electronic devices, and power electronics applications in power systems.

KARANKI et al.: DSTATCOM TOPOLOGY WITH REDUCED DC-LINK VOLTAGE RATING FOR LOAD COMPENSATION WITH NONSTIFF SOURCE

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Nagesh Geddada (S11) received the B.Tech. degree from J.N.T.U., Kakinada, India, in 2004, and the M.S. degree from the Indian Institute of technology Madras, Chennai, India, in 2009, where he is currently working toward the Ph.D. degree. His research interests include custom power devices and power electronics applications to power systems and control systems.

B. Kalyan Kumar (M07) received the B.Tech. degree from J.N.T.U., Hyderabad, India, and the Masters and Doctoral degrees from the Indian Institute of Technology, Kanpur, India, in 2003 and 2007, respectively. He is currently an Assistant Professor at the Indian Institute of Technology Madras, Chennai, India. His research interests include power quality, power system dynamics, and Flexible AC Transmission Systems.

Mahesh K. Mishra (S00M02SM10) received the B.Tech. degree from the College of Technology, Pantnagar, India, in 1991, the M.E. degree from the University of Roorkee, Roorkee, India, in 1993, and the Ph.D. degree in electrical engineering from the Indian Institute of Technology Kanpur, Kanpur, India, in 2001. He has 20 years of teaching and research experience. He was with the Electrical Engineering Department, Visvesvaraya National Institute of Technology, Nagpur, India, for approximately ten years. He is currently a Professor in the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai, India. His research interests include the areas of power distribution systems, power electronics, and control systems. Dr. Mahesh is Life Member of the Indian Society of Technical Education.