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Vol 03, Issue 03; July 2012 International Journal of Communication Engineering Applications-IJCEA
http://technicaljournals.org
ISSN: 2230-8520; e-ISSN: 2230-8539
PERFORMANCE EVALUATION OF PROPOSED VEDIC MULTIPLIER IN MICROWIND

VARSHARANI V.HAIBATPURE #1, PRABHA S. KASLIWAL, B.P. PATIL
PG Student, Department of Electronics, Maharashtra Academy of Engineering, Alandi, Pune, India. yannevarsha6@gmail.com, prabha.kasliwal@gmail.com, bp_patil@rediffmail.com ABSTRACT In this paper, we have designed 4* 4 bit multipliers, Braun array multiplier, CSA multiplier, and proposed, Vedic multiplier. The multiplier circuits are designed using DSCH2 VLSI CAD tools and their layouts are generated by Microwind 3 VLSI CAD tools. The output parameters such as propagation delay, total chip area, throughtput, Latency and power dissipation are calculated by using BSIM4 model in Microwind. The simulated results of the three multipliers are compared. From the analysis of these simulated results, it was found that the proposed Vedic multiplier circuit gives better performance. Keywords: Proposed Vedic Multiplier, BSIM4, Area, Delay, Power. [1] INTRODUCTION As the scale of integration keeps growing, more and more sophisticated signal processing systems are being implemented on a VLSI chip. These signal processing applications not only demand great computation capacity but also consume considerable amounts of energy. While performance and area remain to be two major design goals, power consumption has become a critical concern in todays VLSI system design. Multiplication is a fundamental operation in most signal processing algorithms. Multipliers have operating frequency and processing capacity per chip, large current has to be delivered and the heat due to large power consumption must be removed by proper cooling techniques. Second, battery life in portable electronic devices is limited. Low power design directly leads to prolonged operation time in these portable devices. Multipliers have large area, long latency and consume considerable power. Therefore designing multipliers having lowpower consumption, minimum area is an important part in low-power VLSI system design. There has been extensive work on low-power multipliers at technology, physical, circuit and logic levels. These low-level techniques are not unique to multiplier modules and they are generally applicable to other types of modules. The characteristics of arithmetic computation in multipliers are not considered well. Fast multipliers are essential parts of digital signal processing system. Well as the general purpose processors today, especially since the media processing took off. In the past multiplication was generally implemented via a sequence of addition, subtraction, and shift operations[1]. Multiplication can be considered as a series of repeated additions. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. In most computers, the operand usually contains the same number of bits. When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one collects and add them. 1. Design and Architecture Following multipliers are designed using DSCH2 and Microwind VLSI CAD tools in 0.35 m and 0.25 m design feature sizes: 1. CSA multiplier. 2. Braun array multiplier. 3. Proposed Vedic multiplier 2.1 CSA Multiplier The Carry Save Array (CSA) multiplier is a linear array multiplier (Fig.1). The linear multiplier propagates data down through the array cell. Each row of CSAs adds one additional partial-product to the partial sum..As the operand size increases, linear arrays grow at a rate equal to the square of the operand size. because the number of rows in the array is equal to the length of the multiplier, and the width of each row is equal to the width of multiplicand The large size of full arrays typically prohibits their use, except for with small operand sizes, or on special-purpose math chips, where major portion of the silicon area can be assigned to the multiplier array[2][3].
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Fig 1. Carry Save Array Multiplier 2.1.1 CSA multiplier in DSCH2 and MICROWIND:Fig.2 shows the implementation of CSA multiplier in DSCH2.In this partial product generator is formed by using AND gates and these partial products are going to be added by using carry save adders and output is displayed on hexadecimal display
Fig.2. CSA multiplier in DSCH2 Fig.3 shows layout of CSA multiplier in Microwind The layouts are generated by compiling verilog files generated in DSCH2 for 0.25 m and 0.35 m.
Fig.3. CSA multiplier in Microwind 2.2 Braun array multiplier These multipliers are regularly arranged arrays that have n(n-1) adders and n2 AND gates (Fig.4), where n is the number of inputs. Each of the inputs A and B of the multiplier cells product bits is generated in parallel with the AND gates. The partial products can be added to the previous sum of the partial product by using one row of an adder. The carry signals are shifted one bit to the left and then added to the sums of the first adder and the new partial product. They are then passed diagonally onwards to the next adder stage. There is no horizontal carry propagation for the first rows. Instead, the carry bit is saved for the subsequent adder stage.[4][6]
Fig.4. Braun Array multiplier Fig.5 shows the implementation of Braun Array multiplier in DSCH2.In this partial product generator is formed by using AND gates and these partial products are going to be added by using carry save adders and output is displayed on hexadecimal display
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Fig.5. Braun Array multiplier in DSCH2 Fig.6. Braun Array multiplier in Microwind Fig.6 shows layout of Braun Array multiplier in Microwind The layouts are generated by compiling verilog files generated in DSCH2. 2.3 Proposed 4 bit Vedic multiplier To implement Vedic multiplier following equations are used[5]. Multiplier and multiplicand are shown by a3a2a1a0 and b3b2b1b0. And output bits are as P0, P1, P2, P3, P4, P5, P6, and P7. P0=a0b0; (1) P1=a1b0+a0b1; (2) P2=c1+a2b0+a1b1 + a0b2; (3) P3=c2+a3b0+a2b1 + a1b2 + a0b3; (4) P4=c3+a3b1+a2b2 + a1b3; (5) P5=c4+a3b2+a2b3; (6) P6=c5+a3b3; (7)
Fig.8. Vedic multiplier in DSCH2 3 SIMULATION RESULT 1.Simulation of CSA multilplier in DSCH2 And Microwind Input is given using switches 1111*1111 for that output is E1 .
Fig.9 Simulation Of CSA in Dsch2 Simulation of Braun array
Fig.11 Simulation Of Braun array inDsch2

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Input is given using switches 1111*1111 for that output is E1
ISSN: 2230-8520; e-ISSN: 2230-8539
Fig.13 Simulation Of Vedic in Dsch2 After simulation in Microwind results are summarized in following table. 4*4 Bit Multiplier Comparison in 0.25 m for BSIM4
No . of P M O S No . of N M O S Be st ca se i/p po w er ( m w) 1. 13 7 2. 05 3 0. 96 6 Be st ca se i/p po w er ( m w) W or st ca se i/p po w er Best case i/p delay(ps) Pow er Diss ipati on at 40 (mw ) Pow er Diss ipati on at 120 (mw ) Pow er Dissi patio n Vs Cap acita nce mw)
Multi pliers
Wid th (um)
Heig ht (um)
Wi dth ()
Hei ght ()
Ar ea (n m) 2
Risin g Dela y
Falli ng Dela y
M ax Id d (m a)
Late ncy (ns)
Thro ught put (Gbit s/s)
Braun
0.25 85 258. 5 258. 5
0.17 95 210. 8
206 8 206 8 206 8
143 6 168 6
39 6 51 1 22 0
39 6 51 2 22 0
CSA Propo sed Vedic
102
826
0. 04 64 0. 05 45 0. 02 64
3. 25 3 4. 19 3. 41 2
82
49
589
478
346
196
16 .5 23 16 .2 53 15 .7 09
3.48 5 4.52 4 3.54 9
3.02 3 3.99 4 3.30 6
3.07 9
0.5
4.19 3.45 8
1.328
0.75
3.07
0.33
4*4 Bit Multiplier Comparison in 0.35 m for BSIM4

No . of P M O S No . of N M O S W or st ca se i/p po w er Best case i/p delay(ps) M a x Id d ( m a) Pow er Diss ipati on at 40 (mw ) Pow er Diss ipati on at 120 (mw ) Pow er Dissi patio n Vs Cap acita nce (mw)
Multi pliers
Wid th (um)
Heig ht (um)
Wi dth ()
Hei ght ()
A re a (n m )2
Risin g Dela y
Falli ng Dela y
Late ncy (ns)
Thro ught put (Gbit s/s)
Braun
413. 6
287. 2
206 8
287. 2
39 6
39 6
0. 11 9 0. 13 9 0. 06 8
4. 26 8
9. 79 13 .1 8 12 .4 5
164
108
CSA Propo sed Vedic
413. 6
337. 2
206 8
168 6
51 1
51 2
7. 03 3. 24 9
856
826
413. 6
165. 2
206 8
826
22 0
22 0
406
370
2 6. 1 1 2 5. 8 9 2 5. 5 9
10.7 3
9.07 3
9.791
0.5
14.1
12.3 5
13.18
1.516
0.66
13.1 5
11.6 2
12.68
1.122
0.89
4. CONCLUSION This paper has presented the architecture, logic design, and circuit implementation of 4*4 bit multiplier architecture. The objective for Area, power, latency and throughput optimization in Multipliers was carried out for different logic implementation. The proposed Vedic architecture VLSI design demonstrates that it gives
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ISSN: 2230-8520; e-ISSN: 2230-8539
good Area optimization and Latency as compared with Braun Array multiplier and CSA multiplier with highspeed operation REFERENCES [1].C. Senthilpari, Ajay Kumar Singh, K. Diwakar, Design of a low-power, high performance, 8*8 bit multiplier using a Shannon-based adder cell, IEE Electr. (2008). [2].C.-H. Chang, J. Gu, M. Zhang, A review of 0.18-mm full adder performances for tree structured arithmetic circuits, IEEE Trans. Very Large Scale Integer. (VLSI) Syst. 13 (6) (2005) 686695. [3].Dhireesha Kudithipudi and Eugene John, Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks, Journal of Low Power Electronics Vol.1, 111, 2005. [4].S.Savari Rani, S.Ramasamy, C.Christober Asir Rajan, and V.Harini, An 8x8 Subthreshold Braun Array Multiplier in 32nm CMOS Technology for Wireless SensorNodes, International J. of Recent Trends in Engineering and Technology, Vol. 3, No. 2, May 2010. [5].Prabha S. Kasliwal, Dr. B. P.Patil, Dr. D.K.Gautam, Performance Evaluation of Squaring Operation using Vedic Mathematics, IETE Journal of Research, Vol 57 ,Issue 1, Jan-Feb 2011,pp 39-41 [6].Muhammad H. Rais and Mohammed H. Al Mijalli, Virtex-5 FPGA Based Brauns Multipliers, IJCSNS International Journal of Computer Science and Network Security, VOL.11 No.8, August 2011. [7].M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram , A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture, To appear in IEEE Trans. on VLSI Systems, 2008 . [8].Raminder Preet Pal Singh, Parveen Kumar, Balwinder Singh, Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder, International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009. [9].Nirlakalla Ravi, Anchula Satish, Dr.Talari Jayachandra Prasad and Dr. Thota Subba Rao, A New Design for Array Multiplier with Trade off in Power and Area, IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011. [10]. Joel Ferguson and John Paul Shen, The Design of Two Easily-Testable VLSI Array Multipliers, IEEE Transaction on Computers, vol C-30, August1981. Authors Biography: Varsharani V. Haibatpure is currently pursuing Masters in Electronics and Telecommunication Engineering from Maharashtra Academy of Engineering Pune, India. Her area of interest is VLSI Technology. Her project work is Performance evaluation of Multipliers in Microwind.
Prof. Prabha S. Kasliwal, Associate Professor, Department of Electronics Engineering, Maharashtra Academy of Engineering, Pune. She completed her Masters in Digital Electronics. She is research scholar at MAE Department of Electronics Research Centre and working on Performance evaluation of Arithmetic unit using Vedic algorithm. Her area of interest is Systems on FPGA, Embedded Systems, Wireless Communication Systems. E-mail: prabha.kasliwal@gmail.com Dr. B. P. Patil, Research Guide, Department of Electronics Engineering, Maharashtra Academy of Engineering, Pune. He completed his doctorate degree in Electronics Technology from Guru Nanak Dev University, Amritsar in year 2000. Received the "Sir Thomas Ward memorial Medal" from the Institution of Engg., Calcutta, for the best paper in E & T Journal division for the year 1999-2000. Total research grants received 3.0 Lakhs, He has more than 80 publications to his credit at national and international journals and proceedings. His area of interest is Wireless Communication, Sensor network, Solar Energy and Vedic mathematics.

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498

ISSN: 2230-8520; e-ISSN: 2230-8539

PERFORMANCE EVALUATION OF PROPOSED VEDIC MULTIPLIER IN MICROWIND

ISSN: 2230-8520; e-ISSN: 2230-8539

ISSN: 2230-8520; e-ISSN: 2230-8539

Fig.9 Simulation Of CSA in Dsch2 Simulation of Braun array

Fig.11 Simulation Of Braun array inDsch2

ISSN: 2230-8520; e-ISSN: 2230-8539

Late ncy (ns)

Thro ught put (Gbit s/s)

0.25 85 258. 5 258. 5

206 8 206 8 206 8

CSA Propo sed Vedic

3.48 5 4.52 4 3.54 9

3.02 3 3.99 4 3.30 6

4*4 Bit Multiplier Comparison in 0.35 m for BSIM4

Late ncy (ns)

Thro ught put (Gbit s/s)

CSA Propo sed Vedic

ISSN: 2230-8520; e-ISSN: 2230-8539

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