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Users Guide
Lattice Semiconductor
Introduction
Thank you for choosing the Lattice Semiconductor MachXO2-1200ZE Breakout Board Evaluation Kit! This users guide describes how to start using the MachXO2-1200ZE Breakout Board, an easy-to-use platform for evaluating and designing with the MachXO2-1200ZE PLD. Along with the board and accessories, this kit includes a pre-loaded demonstration design. You may also reprogram the on-board MachXO2-1200ZE device to review your own custom designs. Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage and Handling section of this document for handling and storage tips.
Features
The MachXO2-1200ZE Breakout Board Evaluation Kit includes: MachXO2-1200ZE Breakout Board The board is a 3 x 3 form factor that features the following on-board components and circuits: MachXO2-1200ZE PLD (LCMXO2-1200ZE-1TG144C) USB mini-B connector for power and programming Eight LEDs 60-hole prototype area Four 2x20 expansion header landings for general I/O, JTAG, and external power 1x8 expansion header landing for JTAG 3.3V and 1.2V supply rails Pre-loaded Demo The kit includes a pre-loaded counter design that highlights use of the embedded MachXO2-1200ZE oscillator and programmable I/Os configured for LED drive. USB Connector Cable The board is powered from the USB mini-B socket when connected to a host PC. The USB channel also provides a programming interface to the LCMXO2-1200ZE JTAG port. Lattice Breakout Board Evaluation Kits Web Page Visit www.latticesemi.com/breakoutboards for the latest documentation (including this guide) and drivers for the kit. The content of this users guide includes demo operation, programming instructions, top-level functional descriptions of the Breakout Board, descriptions of the on-board connectors, and a complete set of schematics.
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Figure 1. MachXO2-1200ZE Breakout Board, Top Side
LED Array (J4) 4x15 60-Hole Prototype Array (J6)
Software Requirements
You should install the following software before you begin developing new designs for the Breakout board: Lattice Diamond design software FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program)
MachXO2-1200ZE Device
This board features the MachXO2-1200ZE PLD which offers embedded Flash technology for instant-on, non-volatile operation in a single chip. Numerous system functions are included, such as a PLL and 64Kbits of embedded RAM plus hardened implementations of I2C, SPI, timer/counter, and user Flash memory. Flexible, high performance I/Os support numerous single-ended and differential standards including LVDS, and also source synchro-
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nous interfaces to DDR/DDR2/LPDDR DRAM memory. The 144-pin TQFP package provides 108 user I/Os in a 20mm x 20mm form factor. A complete description of this device can be found in the MachXO2 Family Data Sheet.
Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO2-1200ZE device. The design integrates an up-counter with the on-chip oscillator. Note: You may obtain your Breakout Board after it has been reprogrammed. To restore the factory default demo and program it with other Lattice-supplied examples see the Download Demo Designs section of this document.
c_delay[21:0]
2.08 MHz
WARNING: Do not connect the Breakout Board to your PC before you follow the driver installation procedure of this section. Communication with the Breakout Board with a PC via the USB connection cable requires installation of the FTDI chip USB hardware drivers. Loading these drivers enables the computer to recognize and program the Breakout Board. Drivers can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a stand-alone package. To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation: 1. Select Programmer Drivers in the Product Options of Lattice Diamond Setup. 2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box. 3. Click Finish to install the USB driver. 4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the boards USB mini-B socket (J2). After the connection is made, a green Power LED (D9) will light indicating the board is powered on. 5. The demonstration design will automatically load and drive the LED array in an alternating pattern.
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To load the FTDI chip USB hardware drivers via the stand-alone package: 1. Browse to www.latticesemi.com/breakoutboards and download the FTDI Chip USB Hardware Drivers package. 2. Extract the FTDI chip USB Hardware driver package to your PC hard drive. 3. Connect the USB cable from a USB port on your PC to the boards USB mini-B socket (J7). After the connection is made, a green Power LED (D9) will light indicating the board is powered on. 4. If you are prompted, Windows may connect to Windows Update select No, not this time from available options and click Next to proceed with the installation. Choose the Install from specific location (Advanced) option and click Next. 5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL Certified folder and click OK. 6. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message indicating that the installation was successful. 7. Click Finish to install the USB driver. 8. The demonstration design will automatically load and drive the LED array in an alternating pattern. See the Troubleshooting section of this guide if the board does not function as expected.
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4. Click the Programmer icon.
5. Click Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0). 6. Click the Program icon. When complete, PASS is displayed in the Status column.
Overview
The Breakout Board is a complete development platform for the MachXO2-1200ZE PLD. The board includes a prototyping area, a USB program/power port, an LED array, and header landings with electrical connections to most of the PLDs programmable I/O, power, and JTAG pins. The board is powered by the PCs USB port or optionally with external power. You may create or modify the program files and reprogram the board using Lattice Diamond software. Figure 3. MachXO2-1200ZE Breakout Board Block Diagram
Bank 0 2x20 Header Landing (J2) USB Controller 1x8 Header Landing (J1, Optional JTAG Interface) USB Mini B Socket A/Mini-B USB Cable
GPIO
JTAG Programming
Bank 1
GPIO
LCMXO2-1200ZE1TG144C
8
LED Array
GPIO
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Table 1 describes the components on the board and the interfaces it supports. Table 1. Breakout Board Components and Interfaces
Component/Interface Circuits USB Controller USB Mini-B Socket Components LCMXO2-1200ZE Interfaces LED Array Four 2x20 Header Landings 1x8 Header Landing 4x15 60-Hole Prototype Area Test points Power TP1: +3.3V TP2: +1.2V TP3: GND Output I/O I/O D8-D1 J2: header_2x20 J3: header_2x20 J4: header_2x20 J5: header_2x20 J1: header_1x8 Red LEDs User-definable I/O Optional JTAG interface Prototype area 100mil centered holes. Power and ground reference points PLD U3: LCMXO21200ZE-1TG144C 1200-LUT device packaged in a 20 x 20mm, 144-pin TQFP Circuit I/O U2: FT2232H J7:USB_MINI_B USB-to-JTAG interface and dual USB UART/FIFO IC Programming and debug interface Type Schematic Reference Description
Subsystems
This section describes the principle sub systems for the Breakout Board in alphabetical order. Clock Sources All clocks for the counter demonstration designs originate from the MachXO2-1200ZE PLD on-chip oscillator. You may use an expansion header landing to drive a PLD input with an external clock source. Expansion Header Landings The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the MachXO2-1200ZE. The remaining pins serve as power supplies for external connections. Each landing is configured as one 2x20 100 mil. Table 2. Expansion Connector Reference
Item Reference Designators Part Number J2, J3, J4, J5 header_2x20 Description
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Table 3. Expansion Header Pin Information (J2)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function NC VCCIO0 PT17D/DONE PT17C/INITn PT17B PT17A GND GND PT16D PT16C PT16B PT16A PT15D/PROGn PT15C/JTAGen GND GND PT15B PT15A PT12D/SDA/PCLKC0_0 PT12C/SCL/PCLKT0_0 PT12B/PCLKC0_1 PT12A/PCLKT0_1 GND GND PT11D/TMS PT11C/TCK/TEST_CLK PT11B PT11A PT10D/TDI PT10C/TDO GND GND PT10B PT10A PT9D PT9C PT9B PT9A GND GND
MachXO2-1200ZE Pin N/A 118, 123, 135 109 110 111 112 N/A N/A 113 114 115 117 119 120 N/A N/A 121 122 125 126 127 128 N/A N/A 130 131 132 133 136 137 N/A N/A 138 139 140 141 142 143 N/A N/A
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Table 4. Expansion Header Pin Information (J3)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function VCC_1.2V VCCIO1 VCC_1.2V NC PR10C PR10D PR10A PR10B GND GND PR9C PR9D PR9A PR9B GND GND PR8C PR8D PR8A PR8B GND GND PCLKT1_0/PR5C PCLKC1_0/PR5D PR5A PR5B GND GND PR4C PR4D PR4A PR4B GND GND PR3A PR3B PR2C PR2D PR2A PR2B
MachXO2-1200ZE Pin 36, 72, 108, 144 79, 88, 102 36, 72, 108, 144 N/A 74 73 76 75 N/A N/A 78 77 82 81 N/A N/A 84 83 86 85 N/A N/A 92 91 94 93 N/A N/A 96 95 98 97 N/A N/A 100 99 105 104 107 106
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Table 5. Expansion Header Pin Information (J4)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function VCC_3.3V VCCIO3 VCC_3.3V NC PL2A/L_GPLLT_FB PL2B/L_GPPLC_FB PL2C/L_GPLLT_IN PL2D/L_GPLLC_IN PL3A/PCLKT3_2 PL3B/PCLKC3_2 PL3C PL3D GND GND PL4A PL4B PL4C PL4D GND GND PL5A/PCLKT3_1 PL5B/PCLKC3_1 PL5C PL5D GND GND PL8A PL8B PL8C PL8D GND GND PL9A/PCLKT3_0 PL9B/PCLKC3_0 GND GND PL10A PL10B PL10C PL10D
MachXO2-1200ZE Pin N/A 7, 16, 30 N/A N/A 1 2 3 4 5 6 9 10 N/A N/A 11 12 13 14 N/A N/A 19 20 21 22 N/A N/A 23 24 25 26 N/A N/A 27 28 N/A N/A 32 33 34 35
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Table 6. Expansion Header Pin Information (J5)
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function NC VCCIO2 SI/SISPI/PB20D PB20B SN/PB20C PB20A PB18D PB18B PB18C PB18A GND GND PB15D PB15B PB15C PB15A GND GND PCLKC2_1/PB11B PB11D PCLKT2_1/PB11A PB11C GND GND PCLKC2_0/PB9B PB9D PCLKT2_0/PB9A PB9C GND GND S0/SPISO/PB6D PB6B MCLK/CLK/PB6C PB6A GND GND PB4D PB4B CSSPIN/PB4C PB4A
MachXO2-1200ZE Pin N/A 37, 51, 66 71 69 70 68 67 62 65 61 N/A N/A 60 58 59 57 N/A N/A 56 54 55 52 N/A N/A 50 48 49 47 N/A N/A 45 43 44 42 N/A N/A 41 39 40 38
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Figure 4. J2/J4 Header Landing Callout
J2 1 NC 109 111 GND 113 115 119 GND 121 125 127 GND 130 132 136 GND 138 140 142 GND 2 IO0 110 112 GND 114 117 120 GND 122 126 128 GND 131 133 137 GND 139 141 143 GND 1 3.3 3.3 1 3 5 9 GND 11 13 GND 19 21 GND 23 25 GND 27 GND 32 34 J4 2 IO3 NC 2 4 6 10 GND 12 14 GND 20 22 GND 24 26 GND 28 GND 33 35
Top Side
J2
J4
J5 2 IO1 NC 73 75 GND 77 81 GND 83 85 GND 91 93 GND 95 97 GND 99 104 106 1 NC 71 70 67 65 GND 60 59 GND 56 55 GND 50 49 GND 45 44 GND 41 40 2 IO2 69 68 62 61 GND 58 57 GND 54 52 GND 48 47 GND 43 42 GND 39 38
J3
J5
1 1.2 1.2 74 76 GND 78 82 GND 84 86 GND 92 94 GND 96 98 GND 100 105 107
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Figure 6. J1 Header Landing and LED Array Callout
J1 D8
LED D8 D7 D6 D5 D4 D3 D2 D1
D1
MachXO2-1200ZE PLD The MachXO2-1200ZE-1TG144C is a 144-pin TQFP package PLD device which provides 108 I/Os in a 20 x 20mm package. Table 7. MachXO PLD Interface Reference
Item Reference Designators Part Number Manufacturer Web Site U3 LCMXO2-1200ZE-1TG144C Lattice Semiconductor www.latticesemi.com Description
JTAG Interface Circuits For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a PC host and the JTAG programming chain of the Breakout Board. The USB 5V supply is also used as a source for the 3.3V supply rail. A USB mini-B socket is provided for the USB connector cable. Table 8. JTAG Interface Reference
Item Reference Designators Part Number Manufacturer Web Site U1 FT2232HL Future Technology Devices International (FTDI) www.ftdichip.com Description
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Table 9. JTAG Programming Pin Information
Description Test Data Output Test Data Input Test Mode Select Test Clock 137:TDO 136:TDI 130:TMS 131:TCK
MachXO2-1200ZE Pin
LEDs A green LED (D9) is used to indicate USB 5V power. Eight red LEDs are driven by I/O pins of the MachXO21200ZE device. Table 10. Power and User LEDs Reference
Item Reference Designators Part Number Manufacturer Web Site Description D1, D2, D3, D4, D5, D6, D7, D8, D9 LTST-C190KRKT (D1-D8) LTST-C190KGKT (D9) Lite-On It Corporation www.liteonit.com
Power Supply 3.3V and 1.2V power supply rails are converted from the USB 5V interface when the board is connected to a host PC. Test Points In order to check the various voltage levels used, test points are provided: TP1: +3.3V TP2: +1.2V TP3: GND USB Programming and Debug Interface The USB mini-B socket of the Breakout Board serves as the programming and debug interface. JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the Breakout Board to serve as the programming interface to the MachXO2-1200ZE PLD. Programming requires the Lattice Diamond or ispVM System software. Table 11. USB Interface Reference
Item Reference Designators Part Number Manufacturer Web Site U1 FT2232HL Future Technology Devices International (FTDI) www.ftdichip.com Description
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This section describes modifications to the board to change or add functionality. Bypassing the USB Programming Interface The USB programming interface circuit (USB Programming and Debug Interface section) may be optionally bypassed by removing the 0 ohm resistors: R5, R6, R7, R8 (See Appendix A. Schematics, Sheet 2 of 5). Header landing J1 provides JTAG signal access for jumper wires or a 1x8 pin header. Applying External Power The Breakout Board is powered by the circuit of Schematic Sheet 5 of 5 based on the 5V USB power source. You may disconnect this power source by removing the 0 ohm resistors: R42 (VCC_1.2V) and R44 (VCC_3.3V). Power connections are available from the expansion header landings, J3 (+1.2V, pins 1 and 3, schematic sheet 3 of 5) and J4 (+3.3V, pins 1 and 3, schematic sheet 4 of 5). Measuring Bank and Core Power In addition to the expansion headers, test points (TP1, TP2) provide access to power supplies of the MachXO21200ZE PLD. Inline 1 ohm resistors: R24 (VCCIO0, +3.3V, Bank 0), R25 (VCCIO1, +3.3V, Bank 1), R26 (VCCIO2, +3.3V, Bank 2), R27 (VCCIO3, +3.3V, Bank 3), R56 (VCC core, +1.2V) can be used to measure current for the power supplies.
Mechanical Specifications
Dimensions: 3 in. [L] x 3 in. [W] x 1/2 in. [H]
Environmental Requirements
The evaluation board must be stored between -40 C and 100 C. The recommended operating temperature is between 0 C and 90 C. The board can be damaged without proper anti-static handling.
Glossary
PLD: Programmable Logic Device DIP: Dual in-line package LED: Light Emitting Diode. LUT: Look Up Table PCB: Printed Circuit Board RoHS: Restriction of Hazardous Substances Directive USB: Universal Serial Bus WDT: Watchdog Timer
Troubleshooting
Use the tips in this section to diagnose problems with the Breakout Board. LEDs Do Not Flash If power is applied but the board does not flash according to the preprogrammed counter demonstration then it is likely the board has been reprogrammed with a new design. Follow the directions in the Demonstration Design section to restore the factory default.
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USB Cable Not Detected
If Lattice Diamond Programmer or ispVM System does not recognize the USB cable after installing the Lattice USB port drivers and rebooting, the incorrect USB driver may have been installed. This usually occurs if you attach the board to your PC prior to installing the Lattice-supplied USB driver. To access the Troubleshooting the USB Driver Installation Guide: For Diamond software and standalone Diamond Programmer: 1. Start Diamond or Diamond Programmer and choose Help. 2. Search for USB driver or Troubleshooting, then select the Troubleshooting the USB Driver topic. 3. Follow the directions to install the Lattice USB driver. For ispVM: 1. Start ispVM System and choose Options > Cable and I/O Port Setup. The Cable and I/O Port Setup Dialog appears. 2. Click the Troubleshooting the USB Driver Installation Guide link. The Troubleshooting the USB Driver Installation Guide document appears in your systems PDF file reader. 3. Follow the directions to install the Lattice USB driver. Determine the Source of a Pre-Programmed Device If the Breakout Board has been reprogrammed, the original demo design can be restored. To restore the board to the factory default, see the Download Demo Designs section for details on downloading and reprogramming the device.
Ordering Information
Description MachXO2-1200ZE Breakout Board Evaluation Kit Ordering Part Number LCMXO2-1200ZE-B-EVN China RoHS Environment-Friendly Use Period (EFUP)
Revision History
Date Version Change Summary Initial release. Figure MachXO2-1200ZE Breakout Board, Top Side updated with revision B board photo.
01.0 01.1
2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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5 1
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HEADER
I/Os + I2C
JTAG
Appendix A. Schematics
LCMXO2-1200ZE-1TG144C
BANK 1
RS232
USB CONNECTOR
Power from USB 5V BANK 2
I/Os
HEADER
HEADER
BANK 3 FPGA
17
4 3 2
AXELSYS
Title
LCMXO2-1200ZE-B-EVN
Thursday, April 21, 2011 Sheet
1
Rev A 1 of 5
5 1
+3.3V
C1 4u7 R2 R3
L2
1 2 600ohm 500mA
C4 +3.3V 0.1uF TDO VCC1_8FT +3.3V J1 C3 4u7 TDI
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+3.3V
2k2
VCC1_8FT
+3.3V
4 9
+3.3V
12 37 64
20 31 42 56
U1 FT2232HL
1 2 3 4 5 6 7 8
header_1x8 DNI
1 2 3 4 5 6 7 8
VPHY VPLL
C5
C8
C6
C9
C7
50
0.1uF 0.1uF 0.1uF
0.1uF
0.1uF
49 7 8 14
10uF +3.3V R10 12k 1% 0.1uF
DM DP
16 17 18 19 21 22 23 24
0 0 0 0
R5 R6 R7 R8
3 3 3 3
6
R11 10k FT_EECS FT_EECLK FT_EEDATA R12 10k R13 10k
AGND
10
1 5 11 15 25 35 47 51
18
63 62 61 EECS EECLK EEDATA OSCI 2
R19 X1 2k2
+3.3V
26 27 28 29 30 32 33 34
3 3 FOR FUTURE RS232 FUNCTION
U2
C12
8 7 6 5 1 1 G1 G2
12MHZ C14 18pF
CS CLK DI DO
1 2 3 4
0.1uF
93LC56-SO8
38 39 40 41 43 44 45 46
0 0 0 0 0 0 0
2
C13 18pF
BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 PWREN# SUSPEND#
48 52 53 54 55 57 58 59 60 36
AXELSYS
Title
Document Number
LCMXO2-1200ZE-B-EVN
Thursday, April 21, 2011 Sheet
1
Rev A 2 of 5
Figure 9. FPGA
5 1
+3.3V
VCCIO1
VCC_1.2V
VCCIO0 C15 MAKE PWR TRACES CAPABLE OF 1A BANK 1 0.1uF C16 0.1uF
D
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BANK 0
PT17C_INITn PT17A PT16D PT16B PT15D_PROGn PR9D PR9B PR8D PR8B PCLKC1_PR5D PR5B PR4D PR4B PR3B PR2D PR2B PT15B PT12D_SDA_PCLKC0_0 PT12B_PCLKC0_1 PT15D_PROGn PT15C_JTAGen PT15B PT15A PT16D PT16C PT16B PT16A
PT17D_DONE PT17B
109 110 111 112 PT17D/DONE PT17C/INITn PT17B PT17A PT16D PT16C PT16B PT16A PT15D/PROGRAMn PT15C/JTAGENB PT15B PT15A 87 89 91 92 93 94
PCLKC1_PR5D PCLKT1_PR5C PR5B PR5A
PR10D PR10C PR10B PR10A PR9D PR9C PR9B PR9A PR8D PR8C PR8B PR8A 83 84 85 86
PR8D PR8C PR8B PR8A
73 74 75 76
PR10D PR10C PR10B PR10A RS232_Rx_TTL RS232_Tx_TTL RTSn 2 CTSn 2 DSRn DCDn DTRn 2 2 2 PR10D PR10B 2 2 PR9D PR9C PR9B PR9A J3
113 114 115 117 119 120 121 122 125 126 127 128 130 131 132 133 136 137 138 139 99 100
PR3B PR3A
77 78 81 82
PR10C PR10A PR9C PR9A PR8C PR8A PCLKT1_PR5C PR5A PR4C PR4A PR3A PR2C PR2A
PT15A PT12C_SCL_PCLT0_0 PT12A_PCLKT0_1 PT11D_TMS PT11B PT10D_TDI PT10B PT9D PT9B 2 2 TMS TCK PT11D_TMS PT11C_TCK_TESTCLK PT11B PT11A PT10D_TDI PT10C_TDO PT10B PT10A PT9D PT9C PT9B PT9A PT12D_SDA_PCLKC0_0 PT12C_SCL_PCLT0_0 PT12B_PCLKC0_1 PT12A_PCLKT0_1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 95 96 97 98
PR4D PR4C PR4B PR4A LED0 LED1 LED2 LED3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
5 5 5 5
Header2x20 DNI
19
140 141 142 143 103 104 105 106 107
PR2D PR2C PR2B PR2A VCCIO0 C17 C18 C20 0.1uF
LCMXO2-1200ZE-1TG144C
NC4 PT12D/SDA/PCLKC0_0 PT12C/SCL/PCLKT0_0 NC5 PT12B/PCLKC0_1 PT12A/PCLKT0_1 PCLKC1_0/PR5D PCLKT1_0/PR5C PT11D/TMS PR5B PT11C/TCK/TEST_CLK PR5A PT11B PR4D PT11A PR4C PT10D/TDI PR4B PT10C/TDO PR4A PT10B PT10A PR3B PR3A PT9D NC6 PT9C PT9B PT9A PR2D PR2C PR2B PR2A
LED4 LED5 LED6 LED7 5 5 5 5
VCCIO1
C19 0.1uF
79 88 102
0.01uF
0.1uF
+3.3V VCCIO0
+3.3V
VCCIO1
R24
R25
AXELSYS
Title
Document Number
LCMXO2-1200ZE-B-EVN
Thursday, April 21, 2011 Sheet
1
Rev A 3 of 5
5 1
VCCIO3 VCCIO2
VCC_3.3V
MAKE PWR TRACES CAPABLE OF 1A C25 0.1uF J5 J4 PB20B PB20A PB18B PB18A PB15B PB15A PB11D PB11C PB9D PB9C PB6B PB6A PB4B PB4A PL2A_L_GPLLT_FB PL2B_L_GPPLC_FB PL2C_L_GPLLT_IN PL2D_L_GPLLC_IN 0.1uF BANK 3 BANK 2 MAKE PWR TRACES CAPABLE OF 1A C26
Lattice Semiconductor
U3-3
1 2 3 4 PL2A/L_GPLLT_FB PL2B/L_GPPLC_FB PL2C/L_GPLLT_IN PL2D/L_GPLLC_IN PB4A PB4B CSSPIN/PB4C PB4D PB6A PB6B MCLK/CCLK/PB6C SO/SPISO/PB6D 47 48 49 50
PB9C PB9D PCLKT2_0_PB9A PCLKC2_0_PB9B
38 39 40 41
PB4A PB4B CSSPIN_PB4C PB4D PB6A PB6B MCLK_CCLK_PB6C S0_SPISO_PB6D
PL2B_L_GPPLC_FB PL2D_L_GPLLC_IN PL3B_PCLKC3_2 PL3D PL4A PL4C PL5A_PCLKT3_1 PL5C PL8A PL8C PL9A_PCLKT3_0 PL10A PL10C PL8A PL8B PL8C PL8D PL4A PL4B PL4C PL4D
42 43 44 45
SI_SISPI_PB20D SN_PB20C PB18D PB18C PB15D PB15C PCLKC2_PB11B PCLKT2_PB11A PCLKC2_0_PB9B PCLKT2_0_PB9A S0_SPISO_PB6D MCLK_CCLK_PB6C PB4D CSSPIN_PB4C
C
PL4B PL4D
PL5B_PCLKC3_1 PL5D
11 12 13 14 15 17 PL4A PL4B PL4C PL4D NC0 NC1 PB11C PB11D PCLKT2_1/PB11A PCLKC2_1/PB11B 57 58 59 60
PB15A PB15B PB15C PB15D PB18A PB18B PB18C PB18D PB20A PB20B SN_PB20C SI_SISPI_PB20D VCCIO2 +3.3V VCCIO2
PL8B PL8D
PL9B_PCLKC3_0
PL10B PL10D
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
PL5A_PCLKT3_1 PL5B_PCLKC3_1 PL5C PL5D
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 19 20 21 22 PL5A/PCLKT3_1 PL5B/PCLKC3_1 PL5C PL5D PL8A PL8B PL8C PL8D PL9A/PCLKT3_0 PL9B/PCLKC3_0 NC2 PL10A PL10B PL10C PL10D PB20A PB20B SN/PB20C SI/SISPI/PB20D 68 69 70 71 PB18A PB18B NC3 PB18C PB18D 61 62 63 65 67 PB15A PB15B PB15C PB15D 23 24 25 26 27 28 31 32 33 34 35
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Header2x20 DNI PL9A_PCLKT3_0 PL9B_PCLKC3_0 PL10A PL10B PL10C PL10D VCCIO3 +3.3V C27 C28 R27 0.01uF 0.1uF 0.1uF 0.1uF
LCMXO2-1200ZE-1TG144C
Header2x20 DNI
20
VCCIO3 C29 C30
37 51 66
R26
NOTE PLACE ALL 100 OHM DIFF TERM RESISTORS ON BOTTOM OF BOARD
PL10A +3.3V PB4A PB4B CSSPIN_PB4C R30 DNI PB4D C53 DNI 0.1uF PB6A PB6B R32 DNI 100 100 R36 DNI R38 DNI PCLKT2_0_PB9A PCLKC2_0_PB9B PB11C PB11D R40 DNI 100 100 100 Title 100 Size B Date:
4 3 2
100
PB15A PB15B PB15C PB15D PB18A PB18B PB18C PB18D PB20A PB20B
R29 DNI R31 DNI R33 DNI R35 DNI R37 DNI SN_PB20C R39 DNI SI_SISPI_PB20D
X2
1 Vcc Output
PB9C PB9D
EN 3
PL9A_PCLKT3_0
4
MCLK_CCLK_PB6C R34 DNI S0_SPISO_PB6D
GND
CB3LV-3C-50M0000
50MHz OSC
100
AXELSYS
Lattice MachXO2 1200ZE Breakout Board - FPGA
PCLKT2_PB11A R41 DNI PCLKC2_PB11B Document Number Rev A
LCMXO2-1200ZE-B-EVN
Thursday, April 21, 2011 Sheet
1
of
5 1
VBUS_5V FAN1112 R42 0 L3 R56 C35 10uF 1uF 0.01uF 0.1uF 0.1uF 0.01uF 0.1uF 0.1uF 10uF 1uF 0.1uF C36 C38 C39 C41 C42 C43 C37 C40 C44 C45 1
U4
3 Output Tab
R55 22uF 100
Input 4
C47
2 1 600ohm 500mA
C46
GND
10uF
Lattice Semiconductor
+1.2V
U3-1
DNI
DNI
129
VCCP
U5 R44 0
R43
3 IN GND 1
NCP1117 22uF 0.1uF C49 C50
VBUS_5V
+3.3V
+1.2V
1K
OUT TAB
2 4
L4 1 2 600ohm 500mA
36 72 108 144
D9 Green
C48
10uF
GND GND GND GND GND GND GND GND GND GND GND GND
LCMXO2-1200ZE-1TG144C
+3.3V
LEDs
VBUS_5V
J6
D8 Red
D7 Red
D6 Red
D5 Red
D4 Red
D3 Red
D2 Red
1
D1 Red
B
STATUS_LED7 2
STATUS_LED6 2
STATUS_LED5 2
STATUS_LED4 2
STATUS_LED3 2
STATUS_LED2 2
STATUS_LED1 2
1 2 3 4 5
STATUS_LED0 2
21
R45 C51 1K 0.1uF 1K 1K 1K 1K 1K 1K 1K R46 R47 R48 R49 R50 R51 R52
A
L5
600ohm 500mA
J7
R53
Document Number
LCMXO2-1200ZE-B-EVN
Thursday, April 21, 2011 Sheet
1
Rev A 5 of 5
Lattice Semiconductor
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
5 2 6 2 2 8 1 1 4 1 1 5 3 5 8 1 3 7 5 14 9 1 3 1 1 1 1 1 1 1
Taiyo Yuden Kemet Kemet Kemet Taiyo Yuden LITE-On, Inc. LITE-On, Inc. Molex Samtec
22