HUMBOLDT-UNIVERSITT ZU BERLIN

INSTITUT FR INFORMATIK

COMPUTER ARCHITECTURE
Lecture 10

ALU
Sommersemester 2002 Leitung: Prof. Dr. Miroslaw Malek
www.informatik.hu-berlin.de/rok/ca

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ALU ARITHMETIC / LOGIC UNIT

Arithmetic Units Classification Number Representations Hardware/Software Continuum and Vertical Migration Integer Arithmetic
addition/subtraction multiplication/division

Decimal Arithmetic Unit Floating-Point Arithmetic

addition/subtraction multiplication/division

Logic Functions

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TYPES OF ARITHMETIC UNITS

SERIAL
Operations are performed bit by bit. A carry out bit is fed back in the next cycle. Results are routed to a shift register to assemble a word.
a n 1

A
b n 1

....... .......

a0 z n 1 b0

+
carry

......

z0

PARALLEL

Operands are presented to the unit in parallel. To carry out the operation circuits may be:
Sequenced (ripple carry technique) Occur concurrently, e.g., carry-lookahead technique
a n 1

.......
Z

a0

b n 1

B
32 32

.......

b0

ALU
z n 1
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......

32

z0

ARITHMETIC UNITS CLASSIFICATION BY LEVEL OF DESIGN COMPLEXITY

1. Fixed-Point Arithmetic
a. b. c. d. addition/subtraction of positive numbers addition/subtraction of positive and negative numbers multiplication division

2. Decimal Arithmetic (BCD)

similar to Fixed-Point arithmetic

3. Floating-Point Arithmetic
a. multiplication b. division c. addition and subtraction

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TRADEOFF BETWEEN HARDWARE/SOFTWARE IMPLEMENTATION

ALU units usually as minimum have addition and subtraction, then:
Multiplication (fixed) Division (fixed) Floating Point Special Functions/Tables

HARDWARE/SOFTWARE CONTINUUM AND VERTICAL MIGRATION

ADD SUBTRACT SHIFT STORE HALT Hardware Hardware Hardware Polynomial evaluation Table search Matrix operations Function evaluation

MULTIPLY DIVIDE

Floating-point arithemetic operations Software

Square root

Software Software

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NUMBER REPRESENTATION (1)

Bit pattern Values represented ----------------------------------------------------------------------------------------------------b3,b2,b1,b0 Sign and magnitude 1's complement 2's complement ----------------------------------------------------------------------------------------------------0111 +7 +7 +7 0110 +6 +6 +6 0101 +5 +5 +5 0100 +4 +4 +4 0011 +3 +3 +3 0010 +2 +2 +2 0001 +1 +1 +1 0000 +0 +0 +0 1000 -0 -7 -8 1001 -1 -6 -7 1010 -2 -5 -6 1011 -3 -4 -5 1100 -4 -3 -4 1101 -5 -2 -3 1110 -6 -1 -2 1111 -7 -0 -1 ----------------------------------------------------------------------------------------------------0 N-1 N-2 1 2 1110 -1 1101 -3 1100 -4 -5 1011 1010 -6 -7 -8 +7 0110 1001 1000 0111 -2 1111 0000 0001 0010 0 +1 +2 +3 +4 +5 +6 0101 0100 0011

(a) Circle representation of integers mod N

(b) Mod 16 system for 2'scomplement numbers

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NUMBER REPRESENTATION (2) BCD

1. Binary-Coded Decimal (BCD) can represent the numbers 0 through 9 in 4 4 binary bits. Arithmetic is accomplished modulo 10. Since 4 bits = 2 = 16, numbers greater than 10 are adjusted by adding 6 (=0110), (16-10 = 6).
1010 is used for + and 1011 for -

Example: in BCD-Code:

4739+1281=6020 0111 0010 1001 0011 1000 1011 1001 0001 1010)

0100 + 0001 *( 0101

The number needs to be adjusted by adding 0110:

0101 0101 0101 1 0110 6

1001 1001 1 1010 0110 0000 0

1011 1 1100 0110 0010 0010 2

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1010 0110 0000 0000 0000 0

NUMBER REPRESENTATION (3) BINARY REPRESENTATION

1. Position and magnitude B=bn-1 ......b1b0 n-1 1 0 V(B)= bn-1 2 +...+b12 +b02 2. Signed numbers bn-1=0 positive n - number of bits

bn-1=1 negative N - the actual number

b0

Sign & Magnitude bn-1 magnitude S 1's Complement N

N=(2 -1) - N

negation

2's Complement N* n n N*= 2 - N = (2 - 1) - N+1 = N + 1 negation plus one

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FRACTIONAL 2's COMPLEMENT REPRESENTATION (I)

N* = 2 FRACTIONS FORM
X.XXX . . . X 0.-1-2 . . . . -m
n+1

-N

FOR FRACTION
n=0 N* =21 - N

EXAMPLE Let N = 0.0100101 2 (N) N* = = = 10.0000000 0.0100101 1.1011011

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FRACTIONAL 2's COMPLEMENT REPRESENTATION (II)

decim. binary positive 0 0.000 .125 0.001 .250 0.010 .375 0.011 .500 0.100 .625 0.101 .750 0.110 .875 0.111 decim. binary negative -.875 -.750 -.625 -.500 -.375 -.250 -.125 1.001 1.010 1.011 1.100 1.101 1.110 1.111

N* = 2 - N
2 = (.375) = -.375 = 10.000 - .011 1.101 .625 = 0.101 + (-.125) = 1.111 .500 =*0.100 .375 = 0.011 = 0.011 + (-.250) =-0.010 =1.110 .125 = 0.001 = 0.001
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.375 = 0.011 + (.250) = 0.010 .625 = 0.101 * carry ignored

ARITHMETIC OPERATIONS

1. Addition of positive numbers 2. Addition/subtraction of positive and negative numbers 3. Multiplication a. positive numbers b. signed numbers 4. Division (Integer) 5. Floating point

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EXECUTION TIME
Execution time = Logic Gate Delay - Assume any stage of an n-bit serial adder requires 5 ns - A 32-bit add takes 32 x 2 ns = 64 ns

- Memory access may be 5 ns (basic cycle) - We want to improve the add speed to fall below the basic cycle speed: - Faster logic - Accelerating the carry The carry causes delay, so the basic problem is to calculate the carry more rapidly by looking ahead for it. (e.g., Carry Lookahead logic facilitates increased speed of operation)
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N-bit adder/subtractor with 2's-complement ADD/SUBTRACT control

2's-complement's big advantage: same circuit for add and sub ADD SUB

x0

S=X+Y S = X + Y +1 y1 yn-1 y0

ADD/SUB control
ADD = 0 SUB = 1

xn-1 cn sn-1

x1

n-bit adder s1 s0

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LOGIC FOR ADDING TWO BITS

= x i yi c i + x i y i c i + xi y i c i + x iyi ci c i+1 = xi c i + yi c i + x i yi si
xi yi ci x i yi c i x i yi c i xi yi ci c

si

= (xi + yi +ci) mod 2

ci+1 = (xi + yi +ci) / 2

xi ci yi ci xi yi x i y i c i+1 c

i+1

ADDER (A)

i si
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FAST ADDER DESIGN

The logic equations for two level logic expressions are: (1)

xi yici + xi yi ci + xi yi ci + xi yici ci+1 = xici + yici + xi yi

si =

Factoring the second of these (carry-out equation) into ci +1 = xi yi + ( xi + yi )ci (2) and defining a generate function (3)

Gi = xi yi

and a propagate function (4)

Pi = xi + yi

we can write (5) ci +1 = Gi + P ci i (6)

ci 1+1 = Gi 1 + Pi 1ci 1 ci = Gi 1 + Pi 1ci 1

ci +1 = Gi + Pi (Gi 1 + Pi 1ci 1 )
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(7) (8)

c i + 1 = G i + Pi G i 1 + Pi Pi 1 c i 1 c i + 1 = G i + P i G i 1 + P i P i 1 G i 2 + ... + P i ... P1 G 0 + P i ... P 0 c 0

Pure Carry Lookahead circuit for computing the carry out cn of an n-bit adder
Gi-1 Pi-1 Gi-2 Pi-2 Gi-3 P1 G0 P0 c 0

ci

c i = G i 1 + P i 1 G i 2 + ... + P i 1 ... P1 G 0 + P i 1 ... P 0 c 0

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BLOCK LOOKAHEAD
~ ~ GK , PK ~ Po = P3 P2 P P 1 0 ~ G0 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P G0 1

K=0 1st Block K=1 2nd Block etc.

Carry for a 16-bit adder:

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ c16 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P G0 + P3 P2 P P0 c0 1 1

Example: a 4-bit adder

c 4 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1G 0 + P 3 P 2 P 1 P 0 c 0

x3 y3 P1 G1 c4 s3

x2 y2

x1 y1

x0 y0

Control inputs
c0 s2 s1 s0

4-bit integrated ALU block

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TIMING FOR AN ADDITION OPERATION BASED ON CARRY LOOKAHEAD

Two expressions must be evaluated a) Carry Lookahead
c i = G i 1 + P i 1 G i 2 + ... + P i 1 ... P 1 G 0 + P i 1 ... P 0 c 0

b) The Sum
si = x i y ic i + x iy i c i + xi y i c i + x i y ic i

Ad a) A carry can be generated in three logic gate delays. 1 Compute Pi, Gi 1 AND P's, G's 1 OR resulting AND P's, G's 3 Ad b) The completion of the sum can be generated in three additional logic gate delays. 1 Form ci 1 AND x i , y i , c i , x i , y i , c i 1 OR AND Products 3
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LIMITATION
a) Carry Lookahead with 4 blocks (32 bit, k=8)
Gate fan-in is limited to 8 (usual circuit constraint) Generate Gi Generate Pi 1

2 2 2 2 3 delays

Form C8 Form C16 Form C24 Form C31 Form S31

12 delays at 5 ns per 1 gate 60 ns for an add. b) Carry Lookahead fully integrated (32 bits, k=32)
without circuit constraints

2 2 3 delays

Generate Gk Form C31 Form S31

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Generate Pk

7 delays at 5 ns per 1 gate 35 ns for an add

CARRY SKIP ADDER

a15b15 c12 P12,15 Notation: Pi, j = Pi Pi+1 Pj P8,11 c8 P4,7 c4 a3b3 ... a0b0 c0

CARRY SELECT ADDER

a7b7 a6b6 a5b5 a b 4 4 0 a4b4 1 c0 c4 s3 s2 s1 s0 a3b3 a2b2 a1b1 a b 0 0

s7

s6

s5

s4

- two additions are performed in parallel, one assuming carry 0 the other assuming carry 1 - when the carry is finally known, correct sum is selected
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SUMMARY - ADDITION TECHNIQUES

Serial addition simple logic slow execution complex logic faster execution - Ripple carry - Carry lookahead - Carry skip - Carry select Time O(n) O(log n)
O( n) O( n)

Parallel addition

Technique Ripple CLA (Carry Lookahead) Carry skip Carry select

Space O(n) O(n log n) O(n) O(n)

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