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VOUT VOUT
S R
Turn-Off Turn-Off
Q
OCP
RSENSE SENSE
Feedback Feedback OVP Disable
Ramp
Error Amp
Gating Signal
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AN6027
APPLICATION NOTE
Figure 3 shows the block diagram of the FAN7530. The only difference between the FAN7529 and the FAN7530 is the pin configuration of pin 2 and pin 3. For the FAN7529, the INV pin and the COMP pin are adjacent, but because the voltage of pin 1 is 2.5V and the operating range of pin 2 is from 1V
to 5V, the PFC output voltage can increase at light load if pins 1 and 2 are shorted. For the FAN7530, however, the INV pin and the MOT pin are adjacent. Because the voltage of the MOT pin is 2.9V, the over-voltage protection works if pin 1 and pin 2 are shorted.
Block Diagram
VCC 8 UVLO
Vref VCC
12V
8.5V
Drive Output
13V
7 OUT
CS
Disable
0.45V 0.35V
1V Offset
MOT 2
Sawtooth Generator
INV
Figure 3. Block Diagram of the FAN7530 Showing Error Amplifier Block, Zero Current Detector Block, Sawtooth Generator Block, Over-Current Protection Block, and Switch Drive Block
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AN6027
APPLICATION NOTE
the junction capacitor of the MOSFET resonates with the boost inductor and the auxiliary winding voltage decreases resonantly. If it reaches 1.4V, the zero current detector turns on the MOSFET. The ZCD pin is protected internally by two clamps: the 6.5V HIGH clamp and the 0.65V LOW clamp, as shown in Figure 5.
Turn-on Signal Timer S Q VIN ZCD 5 6.5V 1.4V 1.5V Zero Current Detector R
Figure 6 shows typical ZCD-related waveforms. Because the ZCD pin has some capacitance, there can be some delay caused by Rzcd and the turn-on time can be delayed.
IPEAK tzero 0A ton tdis INEG toff n(V OUT-V IN)
Disable
0.45V
0.35V V OUT
Error Amp
Gm
V ref (2.5V)
Inductor Current
COMP
V AUX -nV IN
0V
V DS
Minimum Voltage Turn-on
0V
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APPLICATION NOTE
Ideally, the switch must be turned on when the inductor current reaches zero; but because of the structure of the ZCD block and Rzcd delay, it is turned on after some delay time. During this delay time, the stored charge of the COSS (MOSFET output capacitor) is discharged through the path indicated in Figure 7. This charge is transferred into a small filter capacitor, Cin1, which is connected to the bridge diode. Therefore, there is no current flow from the input side, meaning the input current Iin is zero during this period. For better total harmonic distortion (THD), it is important to make tzero / TS as small as possible. As shown in Figure 6, tzero is proportional to L C oss but ton and tdis are proportional to L. Therefore tzero / TS is approximately inversely proportional to L . Therefore THD increases as the inductance decreases. Reducing the inductance can decrease the inductor size and cost but the switching loss increases because of the increased switching frequency. In real case, boost diodes junction capacitance and boost inductors parasitic capacitance should be added to COSS when calculating tzero. That means it is important to minimize the parasitic capacitance of the boost inductor and diode junction capacitance for better THD.
iin AC IN C IN1 L iL Q C OSS CO D V OUT
Off Signal
MOT
3 2.9V
CS 4
In the ZCD block, there is an internal timer to provide a means to start or restart the switching if the drive output has been low for more than 150s from the falling edge of the drive output. Without this timer, the PFC converter does not work because the inductor current is always zero when the IC initially starts operation and the ZCD winding voltage does not become positive without any switching.
AN6027
APPLICATION NOTE
L= 4 fsw (min)
Vin ( peak )2
Vin ( peak ) Vo Io (max) 1 + Vo Vin ( peak )
(6)
The boost inductor value is determined by the output power and the minimum switching frequency. The minimum switching frequency must be above the audio frequency (20kHz) to prevent audible noise. The maximum switching period, TS(max), is a function of Vin(peak) and Vo, the output voltage. It can have a maximum value at the highest input voltage or at the lowest input voltage according to Vo. Compare TS(max) at Vin(peak_min) and Vin(peak_max), then select the higher value for the maximum switching period. The boost inductor value can be obtained by Equation 6.
The auxiliary winding voltage is lowest at the highest line. So the turn number of the auxiliary winding can be obtained by Equation 7. The voltage should be higher than the ZCD threshold voltage of 1.5V.
Naux >
(7)
ton = L
= L
(1)
= L
2 Iin( peak )
The voltage ripple of the input capacitor is maximum when the line is lowest and the load is heaviest. If fsw(min) >> fac, the input current can be assumed to be constant during a switching period.
toff = L = L
IL( peak ) (t ) Vo Vin( peak ) sin(t ) 2 Iin( peak ) sin(t ) Vo Vin( peak ) sin(t )
Inductor Current
(2)
Input Current
2 I in
I in
Iin( peak ) =
2 Vo Io Vin( peak )
(3)
t on / 2 t on
t off
TS = ton + toff 1 sin(t ) = 2 L Iin( peak ) + (4) Vin( peak ) Vo Vin( peak ) sin(t ) Vin( peak ) sin(t ) 4 L Vo Io = 1+ 2 Vin( peak ) Vo Vin( peak ) sin(t )
Figure 10. Input Current and Inductor Current Waveform During a Switch Cycle
Cin
Vin(max)
ton 2 0
t dt (8)
TS (max)
(5)
The input capacitor must be larger than the value calculated by Equation 8 and the maximum input capacitance is limited by the input displacement factor (IDF), defined as IDFcos. As shown in Figure 11, the input capacitor generates 90
2006 Fairchild Semiconductor Corporation Rev. 1.0.3 1/11/07 www.fairchildsemi.com
AN6027
APPLICATION NOTE
leading current, which causes phase difference between the line current and the line voltage. The phase difference increases as the capacitance of the input capacitor increases. Therefore, the input capacitor must be smaller than Cin(max) calculated by Equation 12. Cin(max) is the sum of all the capacitors connected at the input side.
The output capacitor is selected by the relationship between the input and output power. As shown in Figure 13, the minimum output capacitance is determined by Equation 14.
IIN ID PFC LOAD IO
(9)
+
VIN
+
CO VO
(10)
= tan1
Cin(max)
(11)
Pin = Iin( rms ) Vin( rms ) (1 cos(2t ) ) = IDVo ID = Iin ( rms ) Vin( rms ) Vo
) )
(12)
(1 cos(2t ))
(13)
2 Vo Io
2 Vin( peak _ max)
tan cos1(IDF )
= Io (1 cos(2t ) )
ID(avg) = IO (1- cos(2t))
iA
Lin iC Cin
ia
IO
+
VA
+
Va PFC Circuit
VO
VO =
Input Filter Im
IO CO
iA iC
Co(min)
(14)
ia VA
Re
Figure 11. Input Voltage and Current Displacement Due to Input Filter Capacitance
The maximum MOSFET RMS current is obtained by Equation 15 and the conduction loss of the MOSFET is calculated by Equation 16. When MOSFET turns on, the MOSFET current rises from zero, so the turn-on loss is negligible. The MOSFET turn-off loss and the MOSFET discharge loss are obtained by Equations 17 and 18, respectively. The switching frequency of the critical conduction mode boost PFC converter varies according to the line and load conditions.
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AN6027
APPLICATION NOTE
The switching frequency is the average value during a line period. The total MOSFET loss can be calculated by Equation 19 and a MOSFET can be selected considering the MOSFET thermal characteristic.
PFC OUT
1 4 2 Vin( LL ) 6 9 Vo 1 4 2 Vin( LL ) 6 9 Vo
R o1 1 Cp
(15) (16)
Figure 14. Output Voltage Sensing Circuit
INV R o2
2 2 Vo Io(max)
Vin(LL )
Pturn off = =
The diode average current can be calculated by Equation 20. The total diode loss can be calculated by Equation 21. Select a diode considering diode thermal characteristic.
(20) (21)
The feedback loop bandwidth must be lower than 20Hz for the PFC application. If the bandwidth is higher than 20Hz, the control loop may try to reduce the 120Hz ripple of the output voltage and the line current may be distorted, decreasing the power factor. A capacitor is connected between COMP and GND to eliminate the 120Hz ripple voltage by 40dB. If a capacitor is connected between the output of the error amplifier and the GND, the error amplifier works as an integrator and the error amplifier compensation capacitor can be calculated by Equation 23. To improve the power factor, Ccomp must be higher than the calculated value. If the value is too high, the output voltage control loop may become slow.
Ccomp = gm
(23)
The output voltage sensing resistors, Ro1 and Ro2, are determined by the output voltage at the high line by Equation 22. The output voltage sensing resistors cause power loss, therefore Ro1 should be higher than 1M. Too high resistance can cause some delay of the OVP circuit due to internal capacitance (Cp), which may slightly increase the OVP level.
To improve the output voltage regulation, a resistor and a capacitor can be added to a simple integrator, as shown in Figure 15. The resistor, Rcomp, increases mid-band gain and the capacitor, Cfilter, which is 1/10~1/5 of the Ccomp, is used to filter high-frequency noise. The gain of the error amplifier with the circuit in Figure 15 is shown in Figure 16.
(22)
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AN6027
APPLICATION NOTE
INV 1 Vref
Ro1
crossing point of the AC line, as shown in Figure 18. To minimize the zero crossing distortion, COSS must be minimized and a larger inductor should be used. There is a limitation in minimizing COSS and using a large inductor because a small MOSFET increases MOSFET conduction loss and a larger inductor is more expensive.
Ro2
3 Rcomp Ccomp
INEG =
IPEAK
(25)
COMP
Inductor Current ton tdis INEG toff n(VOUT-VIN)
Cfilter
0A
C comp
Integrator Proportional gain R comp Freq C filter High frequency Noise filter
VAUX -nVIN
0V
Figure 16. Gain of the Error Amplifier 2) Zero Current Detection Resistor Design
The ZCD current should be less than 10mA; therefore the zero current detection resistor, RZCD is determined by Equation 24.
If the RZCD is selected appropriately, the MOSFET can be turned on when the Vds voltage is minimum to reduce switching loss. It is recommended to design the RZCD to turn on the MOSFET when the Vds voltage is minimum. To improve the zero crossing distortion, the MOSFET turnon time should be increased near the AC line zero crossing point. If a resistor is connected between the MOT and the auxiliary winding, as shown in Figure 19, the function can be implemented easily. Because the auxiliary winding voltage is negatively proportional to the input voltage during the MOSFET turn-on time, the current I2 is proportional to the input voltage (as shown in Figure 19). Therefore, the slope of the internal ramp changes according to input voltage as the current flowing out of the MOT pin changes, as shown in Figure 20. I2 current is maximum at the highest line voltage and the zero crossing improvement is best when I2 is 100% ~ 200% of I1. R2 value should be chosen by experiment.
(24)
Because the ZCD pin has some capacitance, the ZCD resistor and the capacitor cause some delay for ZCD detection, as shown in Figure 17. Because of this delay, the MOSFET is not turned on when the inductor current reaches zero and the MOSFET junction capacitor and the inductor resonate. The inductor current changes its direction and flows negatively. The peak value of this negative current is determined by Equation 25. As shown in Equation 25, the negative current increases as the input voltage is close to zero and COSS increases. This negative current decreases average inductor current and causes zero crossing distortion near the zero
2006 Fairchild Semiconductor Corporation Rev. 1.0.3 1/11/07
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AN6027
APPLICATION NOTE
1st
Output Voltage
Input Current
To start up the FAN7530, the start-up current must be supplied through a start-up resistor. The resistor value is calculated by Equations 26 and 27. The start-up capacitor must supply IC operating current before the auxiliary winding supplies IC operating current, maintaining VCC voltage higher than the UVLO voltage. The start-up capacitor is determined by Equation 28.
3rd 5th
RST
PRST =
Figure 18. Zero Crossing Distortion
RST
1 W
CST
AC IN
VAUX
NAUX RZCD
The CS pin voltage is highest when the AC line voltage is lowest and the output power is maximum. The current sense resistor is determined by Equations 29 and 31, limiting the power loss of the resistor to under 1W.
I2
R2 ZCD CO
Rsense <
= 0.8V
(29)
VCC MOT
INV
PRsense
(30)
(31)
Ramp Slope Change Slope Decrease VAC Slope Increase VEAO Ramp Variable On-time On-time Decrease
On-time Increase
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APPLICATION NOTE
4. Design Example
A 100W converter is used here to illustrate the design procedure using a design spreadsheet. Enter the system parameters in the file to get the designed parameters. The system parameters are as follows: Maximum output power Input voltage range Output voltage AC line frequency PFC efficiency Minimum switching frequency Input displacement factor (IDF) Input capacitor ripple voltage Output voltage ripple 100W 90Vrms~264Vrms 392V 60Hz 90% 37kHz 0.98 24V 8V
ZCD pin and the ground to increase the delay time for the MOSFET minimum voltage turn-on.
MOT =
2 L Po
2 Vin( rms _ min)
106
(32) (33)
RMOT >
Switching Nosie
Figure 22 shows the designed application circuit diagram and Table 2 shows the 100W demo board components list.
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APPLICATION NOTE
PFC OUTPUT D2
R5 D3 Q1 D1 C11
6 5
R10
ZD1
8
R6 C9
ZCD
Vcc
7 OUT
GND
LF1
FAN7530
MOT COMP CS
C1 V1 F1 C6 AC INPUT
R9
R11 R7
R1 R8 C8
C7
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AN6027
APPLICATION NOTE
Table 2. 100W Demo Board Part List PART# VALUE Fuse F1 V1 RT1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 IC1 LF1 250V/3A TNR 471 NTC 10D-9 Resistor 42k 370k 330k 150 20k 100 0.2 10k 10k 2M 12.6k IC FAN7530 Line Filter 38mH
NOTE
PART# C1 C2
VALUE Capacitor 150nF/275VAC 470nF/275VAC 2.2nF/3kV 22F/25V 47nF/50V 220nF 100F/450V 12nF/100V 47pF/50V Diode KBL06 1N4148 BYV26C SB140 1N4746 Inductor 400H(44T:6T)
NOTE Box Capacitor Box Capacitor Ceramic Capacitor Electrolytic Capacitor Ceramic Capacitor MLCC Electrolytic Capacitor Film Capacitor Ceramic Capacitor Fairchild Fairchild 600V/1A Fairchild Fairchild EI3026
470V
C3,C4 C6 C7 C8
1/4W 1/4W 1/2W 1/2W 1/4W 1/4W 1/2W 1/4W 1/4W 1/4W 1/4W
Primary: 0.2*10, from Pin 5 to Pin 3 Secondary: 0.2, from Pin 2 to Pin 4 MOSFET Wire 0.45mm Q1 FQPF13N50C 500V/13A
Table 3. Performance Data 90VAC PF 100W THD Efficiency PF 50W THD Efficiency 0.999 3.97% 90.3% 0.998 4.81% 90.1% 110VAC 0.998 4.43% 92.7% 0.997 5.28% 90.8% 220VAC 0.991 5.25% 94.7% 0.974 6.74% 91.7% 264VAC 0.985 5.47% 95.2% 0.956 7.67% 92.5%
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AN6027
APPLICATION NOTE
Table 4. 200W Demo Board Part List (600H, Wide Input Range Application) PART# VALUE NOTE PART# VALUE Fuse F1 V1 RT1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 IC1 LF1 250V/5A TNR 471 NTC 10D-9 Resistor 37k 250k 330k 150 20k 100 0.1 10k 10k 2M 12.6k IC FAN7530 Line Filter 22mH Wire 0.7mm Q1 1/4W 1/4W 1/2W 1/2W 1/4W 1/4W 1W 1/4W 1/4W 1/4W 1/4W T1 BD D1 D2 D3 ZD1 470V C1 C2 C3,C4 C6 C7 C8 C9 C10 C11 Capacitor 470nF/275VAC 470nF/275VAC 2.2nF/3kV 47F/25V 47nF/50V 220nF 220F/450V 12nF/100V 47pF/50V Diode KBU8K 1N4148 SUF30J SB140 1N4746 Inductor 200H(30T:3T)
NOTE Box Capacitor Box Capacitor Ceramic Capacitor Electrolytic Capacitor Ceramic Capacitor MLCC Electrolytic Capacitor Film Capacitor Ceramic Capacitor Fairchild Fairchild 600V/3A Fairchild Fairchild PQ3230
Primary: 0.1*100, from Pin 5 to Pin 3 Secondary: 0.2, from Pin 2 to Pin 4 MOSFET FDPF20N50 Fairchild
Table 5. Performance Data 85VAC PF 200W THD Efficiency PF 150W THD Efficiency PF 100W THD Efficiency 0.999 3.8% 91.8% 0.999 4.7% 93.3% 0.997 6.5% 94.3% 115VAC 0.998 4.3% 94.8% 0.998 5.2% 95.5% 0.996 7.4% 95.3% 230VAC 0.993 6.5% 96.9% 0.990 7.0% 96.9% 0.981 9.0% 96.2% 265VAC 0.990 6.5% 97.3% 0.985 6.9% 97.0% 0.971 8.5% 96.0%
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AN6027
APPLICATION NOTE
Table 6. 300W Wide Input Range Application Part List PART# VALUE NOTE Fuse F1 V1 RT1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 IC1 LF1 250V/5A TNR 471 NTC 6D-22 Resistor 60k 330k 330k 100 20k 100 0.06 10k 10k 2M 12.6k IC FAN7530 Line Filter 40mH Wire 1mm 1/4W 1/4W 1/2W 1/2W 1/4W 1/4W 1W 1/4W 1/4W 1/4W 1/4W 470V
VALUE Capacitor 680nF/275VAC 680nF/275VAC 2.2nF/3kV 47F/25V 33nF/50V 220nF 33F/450V 12nF/100V 9pF/50V Diode KBU8J 1N4148 SUF30J SB140 1N4746 Inductor 200H(36T:3T)
NOTE Box Capacitor Box Capacitor Ceramic Capacitor Electrolytic Capacitor Ceramic Capacitor MLCC Electrolytic Capacitor Film Capacitor Ceramic Capacitor Fairchild Fairchild 600V/3A Fairchild Fairchild PQ3535
Primary: 0.1, *100, from Pin 5 to Pin 3 Secondary: 0.2, from Pin 2 to Pin 4 MOSFET Q1 FQA28N50 Fairchild
Table 7. Performance Data 85VAC PF 300W THD Efficiency PF 225W THD Efficiency PF 150W THD Efficiency PF 75W THD Efficiency 0.999 4.5% 91.4% 0.999 3.9% 92.8% 0.998 4.8% 94.0% 0.994 9.3% 94.8% 115VAC 0.998 4.7% 94.5% 0.998 4.7% 95.1% 0.997 5.8% 95.7% 0.989 10.8% 95.9% 230VAC 0.993 6.4% 97.4% 0.989 6.1% 97.4% 0.978 7.4% 97.0% 0.929 11.2% 95.3% 265VAC 0.988 6.5% 97.7% 0.982 6.2% 97.7% 0.963 7.4% 97.3% 0.885 12.0% 95.2%
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AN6027
APPLICATION NOTE
Nomenclature Ccomp: compensation capacitance CIN: input capacitance COUT: output capacitance CST: start-up capacitance fac: AC line frequency fsw(max): maximum switching frequency fsw(min): minimum switching frequency fsw: switching frequency HY(ST) min: minimum UVLO hysteresis ID: boost diode current IDavg: diode average current IDrms: diode RMS current Iin (peak): input current peak value Iin (peak_max): maximum of the input current peak value Iin (rms): input current RMS value Iin (t): input current IL (t): inductor current IL(peak) (t): inductor current peak value during one switching cycle IL(peak): inductor current peak value during one AC line cycle IL(peak_max): maximum inductor current peak value IO (max): maximum output current IO: output current IQrms: MOSFET RMS current ISTmax: maximum start-up supply current L: boost inductance Naux: auxiliary winding turn number NP: boost inductor turn number Pin: input power PO(max): maximum output power PO: output power Rsense: current sense resistance
2006 Fairchild Semiconductor Corporation Rev. 1.0.3 1/11/07
RST: start-up resistance Rzcd: zero current detection resistance tf: MOSFET current falling time toff: switch off time ton: switch on time TS: switching period Vin (peak): input voltage peak value Vin (peak_low): input voltage peak value at low line Vin (peak_max): maximum input voltage peak value Vin (peak_min): minimum input voltage peak value Vin (rms): input voltage RMS value Vin (rms_max): maximum input voltage RMS value Vin (rms_min): minimum input voltage RMS value Vin (t): input voltage VO or VOUT: output voltage
Vin (max): maximum input voltage ripple VO (max): maximum output voltage ripple : converter efficiency : AC line angular frequency
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AN6027
APPLICATION NOTE
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reason ably expected to result in significant injury to the user.
2006 Fairchild Semiconductor Corporation Rev. 1.0.3 1/11/07
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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