MICROCHIP FABRICATION A Brief Guide to Semiconductor Processing

Hafeth A. Dawbaa1, Sana'a University, Faculty of Electrical Engineering, Email: abumussa89@gmail.com

ABSTRACT

| Modern life is totally intertwined with the innovative products of the electronic revolution, but what are the

powerful engines that enable these products to work?, we find them hidden in small packages attached to circuit board. They are microchips, made on tiny pieces of semiconductor materials usually silicon. A chip can contain many millions of mini-electronic devices, all wired together to form an integrated circuit. State-of-the-art chips contain billions of components, but what exactly are integrated circuits? And how are they made? We'll answer these questions and reveal a manufacturing process that pushes the limits of technology, just as it would push your imagination.
KEYWORDS

| Microchip; Fabrication; IC; Semiconductor; MOS; Transistor; Wafers; CVD; PVD; MBE; CMP. operation. The first, Photoresist Coat, begins with sequential dehydration, priming and baking steps. These are followed by the application of photoresist in a spin process and another baking step to drive off the photoresist solvents. In step two, the critical alignment and exposure procedure, the pattern on a radical or photo mask is aligned to the wafer, and then transferred into the photoresist layer using one of several different approaches. After alignment and exposure, the photoresist layer has regions of exposed and unexposed resist. Bringing out the pattern in the resist layer occurs during the Development process. Dry Etch takes place in Plasma Etch Systems where the pattern photoresist acts as an Etch tensile. The Doping process drives very small amounts of dopants into the wafer surface through openings created in patterning operation. Doping alters the conductivity of

1. INTRODUCTION
Microchip fabrication, a series of demanding process steps that produces millions of chips in factories all around the world. Microchip manufacturing is divided into four distinct stages. Stage one: Material Preparation extracts and purifies the semiconductor material. Next, comes the growing of crystals from the semiconductor material and preparation of thin disks called wafers in a process called wafer manufacturing. In stage three, Microchip Fabrication, the circuit components are formed in and on the wafer surface. Finally, the wafer is separated into individual chips also called "die" and placed in protective packages; this is called packaging or assembly.2 Because Microchips are extremely sensitive to incredibly small amounts of contaminants, a necessary first step in wafer fabrication is the design and construction of a clean room which exceeds the cleanness of a hospital operating room. Every aspect of a chip fabrication area is designed and controlled to protect the wafers from unwanted contamination. Fabricating integrated circuits requires the formation of thin films of various materials on the wafer surface. The operations, used to create thin films, are referred to as Layering Processes. These layers perform different circuit functions, some are conductors, some are insulators, still other layers may be added layers of semiconductor material. Patterning is the most demanding and costly semiconductor manufacturing operation. There are five basic steps to the patterning
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Academic Number (228/2009)

Figure (1) : Simplified illustration of the process of fabrication of a CMOS inverter on p-type substrate in semiconductor microchip fabrication.

Figure (1)2

semiconducting materials. The Dopants create electrically active n- and p-type regions in the wafer surface. Ion Implantation is the most commonly used doping method. The deposition of many thin layers is needed in building integrated circuit structures. A deposited layer may be a semiconducting layer, such as silicon, an insulating material, such as silicon dioxide or silicon nitride, or a conducting layer of metal, such as aluminum, copper or tungsten. Chemical viper deposition or "CVD" is often used to deposit silicon and dielectric layers. Insulating materials are referred to as "dielectrics". Many device structures are built on the wafer surface using CVD layers. This results in height variations that cause focus problems for subsequent patterning operations. The solution to this problem is to flatten or planarize the surface of the insulating layer which is deposited over the structures on the wafer surface. However, the most important planarizing technique is chemical mechanical polishing or "CMP". CMP combines chemical action with light mechanical polishing. Metal layers deposited and patterned on the wafer surface are used to connect the individual components creating an integrated circuit. The most common technique for depositing metals is sputtering. Sputtering is physical process and a form of PVD (Physical Vapor Deposition). Sputtering is similar to freeing pieces from a concrete wall using a sand plaster. Another method of depositing metal on the wafer is Electro-Mechanical Deposition or "ECD", also referred to as Electro-Plating. An important use of ECD is to deposit copper layers. An important issue in the multi-level wiring structure is the dielectric constant called "k" of the material used for the insulating layers. The metal oxide semiconductor or MOS transistor is a key circuit component, used in very large numbers as a switch or amplifier. It has a simple sandwich structure. The main parts of the transistor are the source, drain and gate. [2][8]

Front-end-of-line (FEOL) processing Back-end-of-line (BEOL) processing

Figure (2)3

3. PROCESSING
Microchip fabrication is actually a collection of technologies which are utilized in making microdevices. Some of them have very old origins, not connected to manufacturing, like lithography or etching. Polishing was borrowed from optics manufacturing, and many of the vacuum techniques come from 19th century physics research. Electroplating is also a 19th century technique adapted to produce micrometre scale structures, as are various stamping and embossing techniques. To fabricate a microdevice, many processes must be performed, one after the other, many times repeatedly. These processes typically include depositing a film, patterning the film with the desired micro features, and removing (or etching) portions of the film. For example, in memory chip fabrication there are some 30 lithography steps, 10 oxidation steps, 20 etching steps, 10 doping steps, and many others are performed. The complexity of microfabrication processes can be described by their mask count. This is the number of different pattern layers that constitute the final device. Modern microprocessors are made with 30 masks while a few masks suffice for a microfluidic device or a laser diode. Microfabrication resembles multiple exposure photography, with many pattern s aligned to each other to create the final structure. [1] [4]

2. WAFERS PREPARATION
A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface. [2] Once the wafers are prepared, many process steps are necessary to produce the desired semiconductor integrated circuit. In general, the steps can be grouped into two major parts:

4. LIST OF STEPS
This is a list of processing techniques that are employed numerous times in a modern electronic device and do not necessarily imply a specific order. [5] Wafer processing o Wet cleans o Photolithography
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Figure (2) : The Czochralski process

o o o o

o o o o o o o

Ion implantation (in which dopants are embedded in the wafer creating regions of increased (or decreased) conductivity) Dry etching Wet etching Plasma ashing Thermal treatments Rapid thermal anneal Furnace anneals Thermal oxidation Chemical vapor deposition (CVD) Physical vapor deposition (PVD) Molecular beam epitaxy (MBE) Electrochemical deposition (ECD). See Electroplating Chemical-mechanical planarization (CMP) Wafer testing (where the electrical performance is verified) Wafer backgrinding (to reduce the thickness of the wafer so the resulting chip can be put into a thin device like a smartcard or PCMCIA card.)

epitaxial. These materials include: silicon, carbon fiber, carbon nanofibers, filaments, carbon nanotubes, SiO2, silicon-germanium, tungsten, silicon carbide, silicon nitride, silicon oxynitride, titanium nitride, and various high-k dielectrics. The CVD process is also used to produce synthetic diamonds. [2][7]

(a)

(b)
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Figure (3)4
CHEMICAL-MECHANICAL PLANARIZATION (CMP)

6.
Die preparation o Wafer mounting o Die cutting IC packaging o Die attachment o IC bonding Wire bonding Thermosonic bonding Flip chip Wafer bonding Tab bonding o IC encapsulation Baking Plating Lasermarking Trim and form IC testing

Chemical mechanical planarization is a process of smoothing and planning surfaces with the combination of chemical and mechanical forces, a hybrid of chemical etching and free abrasive polishing. Mechanical grinding alone causes too much surface damage, while wet etching alone cannot attain good planarization. Most chemical reactions are isotropic and etch different crystal planes with different speed. CMP involves both effects at the same time. [6][9]

5. CHEMICAL VAPOR DEPOSITION (CVD)

Chemical vapor deposition (CVD) is a chemical process used to produce high-purity, high-performance solid materials. The process is often used in the semiconductor industry to produce thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile by-products are also produced, which are removed by gas flow through the reaction chamber. Microfabrication processes widely use CVD to deposit materials in various forms, including: monocrystalline, polycrystalline, amorphous, and
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Figure (4)5

7. PHYSICAL VAPOR DEPOSITION (PVD)

Physical vapor deposition (PVD) is a variety of vacuum deposition methods used to deposit thin films by the condensation of a vaporized form of the desired film material onto various workpiece surfaces (e.g., onto semiconductor wafers). The coating method involves purely physical processes such as high temperature vacuum evaporation with subsequent condensation, or
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Figure (3) : (a) Plasma assisted CVD, (b) Hot-wall thermal CVD Figure (4) : The CMP Process

plasma sputter bombardment rather than involving a chemical reaction at the surface to be coated as in chemical vapor deposition.[2]6 Figure (5)6

9. PHOTOLITHOGRAPHY
Figure (7)8 Photolithography (also termed "optical lithography" or "UV lithography") is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical "photoresist", or simply "resist," on the substrate. A series of chemical treatments then either engraves the exposure pattern into, or enables deposition of a new material in the desired pattern upon, the material underneath the photo resist. For example, in complex integrated circuits, a modern CMOS wafer will go through the photolithographic cycle up to 50 times. Photolithography shares some fundamental principles with photography in that the pattern in the etching resist is created by exposing it to light, either directly (without using a mask) or with a projected image using an optical mask. This procedure is comparable to a high precision version of the method used to make printed circuit boards. Subsequent stages in the process have more in common with etching than with lithographic printing. It is used because it can create extremely small patterns (down to a few tens of nanometers in size), it affords exact control over the shape and size of the objects it creates, and because it can create patterns over an entire surface costeffectively. Its main disadvantages are that it requires a flat substrate to start with, it is not very effective at creating shapes that are not flat, and it can require extremely clean operating conditions.[1][5]8

8. MOLECULAR BEAM EPITAXY (MBE)

Molecular beam epitaxy (MBE) is one of several methods of depositing single crystals. It was invented in the late 1960s at Bell Telephone Laboratories by J. R. Arthur and Alfred Y. Cho. MBE is widely used in the manufacture of semiconductor devices, including transistors for cellular phones and Wi-Fi. Recently, the world's most efficient solar cells have been demonstrated with MBE and are being commercialized. Molecular beam epitaxy takes place in high vacuum or ultra-high vacuum (108 Pa). The most important aspect of MBE is the deposition rate (typically less than 3000 nm per hour) allows the films to grow epitaxially. These deposition rates require proportionally better vacuum to achieve the same impurity levels as other deposition techniques. The absence of carrier gases as well as the ultra-high vacuum environment result in the highest achievable purity of the grown films. [4][7][10]7

Figure (6)7

10. HAZARDOUS MATERIALS

Many toxic materials are used in the fabrication process. [2] These include:

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Figure (5): PVD: Process flow diagram Figure (6): A simple sketch showing the main components and rough layout and concept of the main chamber in a Molecular Beam Epitaxy system

Figure (7): Simplified illustration of dry etching using positive photoresist during a photolithography process in semiconductor microfabrication (not to scale).

 poisonous elemental dopants such as arsenic, antimony and phosphorus poisonous compounds like arsine, phosphine and silane highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid and hydrofluoric acid It is vital that workers not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure of this sort. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges etc., to control the risk to workers and also the environment if these toxic materials are released into the atmosphere. [6]

10. McCray, W.P. (2007). "MBE Deserves a Place in the History Books". Nature Nanotechnology 2 (5): 259261.

11. CONCLUSION
This research effort generated a substantial quality of knowledge of one of the technical wonders of a modern world, the Microchip Manufacturing Process. It is a series of high-tech steps that requires the absolute limit in precision machines and state-of-the-art materials. It is a process that produces the miniature engines that drive the information age. The semiconductor industry is truly at the limits of modern technology.

12. REFERENCES 1. Introduction to Microfabrication (2004) by S. Franssila. 2. Fundamentals of Microfabrication (2nd ed, 2002) by M. Madou. 3. Micromachined Transducers Sourcebook by Gregory Kovacs (1998) . & Murray: The Physics of 4. Brodie Microfabrication (1982). 5. Demystifying chipmaking By Richard F. Yanda, Michael Heynes and Anne K. Miller 2005. 6. Website:http://www.uic.com/wcms/WCMS2. nsf/index/Resources_26.html, Assembly and Reliability of a Wafer Level CSP. 7. Kaeslin, Hubert (2008), Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication, Cambridge University Press, section 14.2. 8. P. van Zant: Microchip Fabrication (2000, 5th ed). 9. Jaeger, Richard C. (2002). "Film Deposition". Introduction to Microelectronic Fabrication (2nd ed.). Upper Saddle River: Prentice Hall.