Finite State Machines Lecture 15

Salvador Ruiz Correa Centro de Investigaciones en Matemticas

04/17/08

Block Diagram Serial Adder

A a Shift register Adder FSM Shift register b s Shift register Sum = A + B

B Clock

State Diagram for the Serial Adder FSM

Reset 00 0 01 1 10 1 ( ab s) 11 0 H 00 1 G: carry-in= 0 H: carry-in= 1 01 0 10 0 11 1

State Table for the Serial Adder

Next state ab =00 G G 01 G H 10 G H 11 H H 00 0 1 Output s 01 1 0 10 1 0 11 0 1

Present state G H

State-assigned Table
Present state y 0 1 0 0 Next state ab =00 01 Y 0 1 0 1 1 1 0 1 1 0 10 11 00 Output 01 s 1 0 0 1 10 11

Figure for the Adder FSM

a b Full adder s Y carry-out Clock Reset D Q Q y

State Diagram for the MooreType Serial Adder FSM

Reset

00

G0 s = 0 00 00

11

H0 s = 0

01 10

01 10

11

11

01 10

01 10

G1 s = 1

00

H1 s = 1

11

State Table for the Moore-type Serial Adder

Present state G0 G1 H0 H1 Nextstate ab =00 G0 G0 G1 G1 01 G1 G1 H0 H0 10 G1 G1 H0 H0 11 H0 H0 H1 H1 Output s 0 1 0 1

State Table for the Moore-type Serial Adder

Present state y2 y 1 00 01 10 11 Nextstate ab =00 01 Y2 Y1 00 00 01 01 01 01 10 10 01 01 10 10 10 10 11 11 10 11 Output s 0 1 0 1

Circuit for the Moore-Type Serial Adder

a b Sum bit Full adder Carry-out Y1 D Q Q y1 s

Y2

Q Q

y2

Clock Reset

State Minimization (1)

Two states Si and Sj are said to be equivalent if and only if for every possible input sequence, the same output sequence will be produced regardless of whether Si and Sj is the initial state.

State Minimization (2)

A partition of states consist of one or more blocks where each block comprises a substate of states that ma be equivalent, but the states in a given block are definitely no equivalent to states in other blocks.

Example State Minimization (1)

Present state A B C D E F G Next state w= 0 B D F B F E F w= 1 C F E G C D G Output z 1 1 0 1 0 0 0

P1 = (ABCDEFG) P2 = (ABD)(CEFG) May be equivalent

Example State Minimization (2)

Present state A B C D E F G Next state w= 0 B D F B F E F w= 1 C F E G C D G Output z 1 1 0 1 0 0 0

0 and 1- successors of (ABD) 0 .- (BDB) 1.- (CFG)

P2 = (ABD)(CEFG)

Example State Minimization (3)

Present state A B C D E F G Next state w= 0 B D F B F E F w= 1 C F E G C D G Output z 1 1 0 1 0 0 0

0 and 1- successors of (CEFG) 0 .- (FFEF) 1.- (ECDG)

P2 = (ABD)(CEFG)

Example State Minimization (4)

Present state A B C D E F G Next state w= 0 B D F B F E F w= 1 C F E G C D G Output z 1 1 0 1 0 0 0

P3 = (ABD)(CEG)(F) P4 = (AD)(B)(CEG)(F) P5 = (AD)(B)(CEG)(F)

P4 = P5 !!!

Minimized State Table

Present state A B C F Nextstate w= 0 B A F C w= 1 C F C A Output z 1 1 0 0

Example: Vending Machine

The machine accepts 5 and 10 cents coins It takes 15 cents for a piece of candy to be released from the machine If 20 cents is deposited, the machine will not return change, but it will credit the buyer with 5 cents and wait for the buyer to make a second purchase.

Example: Vending Machine

All electronic signals in the vending machine are synchonized to the positive edge of a clock. The clock frequency is 100 (ns) The vending machine coin receptor generates two signals, senseD and senseN,which are asserted when a 10 cent and a 5 cent coin is detected.
N-5c D-10c

Example: Vending Machine

Because the coin receptor is a mechanical device, an thus very slow compared to the electronic circuit, inserting a coin causes senseD and senseN, to be set to 1 for a large number of clock cycles The coin rec eptor also generates signals named D and N. The signal D is set for one clock cycle after senseD becomes 1, and N is set to 1 for one clock signal, after senseN becomes 1. If ther is not enough credit to release a candy the vending machine set an output z to 0.

Signals for Vending Machine

Clock sense N sense D N D

(a) Timing diagram

N sense N Clock D Q Q D Q Q

(b) Circuit that generates N

DN Reset DN DN DN D S4 1 N S2 0 D DN S5 1 N S8 1 S6 0 D S9 1 DN DN N S3 0 N D S7 1 S1 0 DN DN

State Diagram for Vending Machine

State Table for Vending Machine

Present state S1 S2 S3 S4 S5 S6 S7 S8 S9 Next state DN =00 S1 S2 S3 S1 S3 S6 S1 S1 S3 01 S3 S4 S6 S8 10 S2 S5 S7 S9 11 Output z 0 0 0 1 1 0 1 1 1

Minimized State Table for Vending Machine

Present state S1 S2 S3 S4 S5 Next state DN =00 S1 S2 S3 S1 S3 01 S3 S4 S2 10 S2 S5 S4 11 Output z 0 0 0 1 1

DN

S1 0 N S3 0 N DN S2 0 N D S4 1 D DN S5 1

DN D DN

Minimized state diagram for Vending Machine