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BASIC CONCEPTS IN GRAPH THEORY: Undirected graph degree of a vertex, degree sequence, subgraphs, vertex induced subgraphs, complement of a graph, self complementary graphs, walk, path, connectivity, eccentricity, radius, diameter, vertex and edge cuts, vertex partition, independent set, clique. Digraph orientation, strongly, weakly and unilaterally connected digraphs, directed acyclic graph. Adjacency matrix and incidence matrix of graphs. Trees, spanning trees, matrix tree theorem. (6) SPECIAL CLASSES OF GRAPHS: Complete graphs, bipartite graphs, grid graphs, Eulerian graphs - Eulers theorem. Hamiltonian graphs Diracs and Ores theorems, closure of a graph, Bondy-Chvatal theorem, traveling salesman problem. Planar graphs Eulers formula, Kuratowskis theorem, embedding, dual, five color and four color theorems (without proof). Overlap graph, containment graph, interval graph, permutation graph, neighborhood graph and rectangular dual, relationship between these graph classes. (8) GRAPH ALGORITHMS IN VLSI PHYSICAL DESIGN: Search algorithms depth first search and breadth first search, spanning tree algorithms Kruskal and Prim, shortest path algorithms Dijkstra and Floyd-Warshall, vertex coloring Welsh-Powell algorithm, matching, perfect matching, bipartite matching augmenting path algorithm, min-cut and maxcut algorithms. (14) LINEAR PROGRAMMING: Definition, simplex, two-phase simplex and dual simplex algorithms. (5)
DYNAMIC PROGRAMMING: Multistage decision process, computational procedure, final and initial value problems, continuous dynamic programming, discrete dynamic programming. (9) Total 42 REFERENCES: 1. Sherwani N A, Algorithms for VLSI Physical Design Automation, Springer-Verlag, 2007. 2. Taha H A, Operations Research, Prentice Hall, 2003. 3. West D B, Introduction to Graph Theory, Pearson Education, 2007. 4. Yellen J and Gross J, Graph Theory and its Applications, Chapman & Hall, 2006. 5. Gerez S H, Algorithms for VLSI Design Automation, John Wiley, 2007. 6. Kocay W and Kreher D L, Graphs, Algorithms and Optimization, Chapman & Hall, 2005. 7. Papadimitriou C H and Steiglitz K, Combinatorial Optimization, Prentice Hall, 1997.
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OVERVIEW OF VLSI DESIGN METHODOLOGY: VLSI design process - Architectural design - Logical design - Physical design - Layout styles - Fullcustom, Semicustom approaches. (4) LAYOUT DESIGN RULES: Need for design rules - Mead Conway design rules for silicon gate nMOS process - CMOS nwell / pwell design rules - simple layout examples - Sheet resistance - Area capacitance - wiring capacitance. (6) MOS INVERTER: nMOS inverter - steered input to an nMOS inverter - Depletion mode and enhancement mode pull ups CMOS inverter - DC characteristics, Transient characteristics. (8) LOGIC DESIGN: Pass transistor and transmission gate - static CMOS design, Pseudo nMOS, dynamic CMOS logic Clocked CMOS logic - precharged domino logic. (7) SEQUENTIAL LOGIC: Clocked sequential circuits - Two phase clocking - charge storage - Dynamic sequential circuits JK Flip-flop circuit, Memory Design. (8) VLSI BUILDING BLOCKS DESIGN: Adders, Shifters, PLA design - Arithmetic logic unit design -Multipliers Design using Booth's algorithm, Modified Booths Algorithm. (9) Total 42 REFERENCES: 1. Jan M Rabaey, Digital Integrated circuits - A design", Prentice Hall, Dec 2004. 2. Kang, CMOS Digital integrated Circuits, McGraw Hill, 2002. 3. Neil Weste and Kamran Eshranghian Principles of CMOS VLSI Design, Addison Wesley, 2000. 4. Saida M Sait and Habib Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing Company, 1st edition Nov 1999. 5. Mead C and Conway L, Introduction to VLSI Systems, Addison Wesley, 1979. 6. Glaser L and Dobberpuhl D, The Design and Analysis of VLSI Circuits, Addison Wesley, 1985.
DATA STRUCTURES AND ALGORITHMS: Data Structures - Graph Theory paths, trees, search algorithms, Complexity of algorithms, dynamic programming, Integer linear programming, Genetic algorithm, Simulated Annealing. (8) SIMULATION & SYNTHESIS: Compiler driven simulation-Event driven simulation - Switch level simulation - Circuit simulation - logic synthesis two level synthesis ,Binary decision diagrams ,ROBDD principles (8) PHYSICAL DESIGN AUTOMATION: Partitioning - KL, FM algorithms, Placement Simulation based algorithmsSimulated Annealing , Force Directed Algorithm, Partitioning based algorithms- Breuers Algorithm, Terminal propagation Algorithm , Cluster Growth Algorithm , Floor planning slicing floor plan , Constraint Based Floor Planning, Integer Program Based Floor Planning Pin Assignment. (8) ROUTING: Grid routing Maze Routing Algorithms, Global routing - Shortest Path Based Algorithms, Steiner tree based Algorithms, detailed routing Left Edge algorithm, Dog-Leg Algorithm , Greedy Channel Routing, Switch Box Routing algorithms- over the cell routing, Clock Routing. (8) LAYOUT SYNTHESIS AND OPTIMISATION: Layout generation and Optimization of standard cell layout, gate matrix layout and PLA, Layout Compaction one dimensional and two dimensional compaction (8) Total 42 REFERENCES: 1. Sherwani N A, Algorithms for VLSI Physical Design Automation, Kluwer, 1999. 2. Sait S M and Youssef H, VLSI Physical Design Automation, World Scientific, 1999. 3. Sabih H Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons, 1999. 4. Micheli G D, Synthesis and Optimization of Digital Circuits, Tata McGraw Hill, 2004.
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BASIC CONCEPTS OF HARDWARE DESCRIPTION LANGUAGE:,Comparison between HDL and High Level Language Hierarchy, Concurrency, Logic and Delay Modelling, Structural, Data flow, Behavioral Styles of Hardware Description, Architecture of event driven simulation. (7) VHDL: Data Types, Operators, Classes of Objects, entities and architectures , Attributes concurrent statementssequential statements- signals and variables- Behavior, dataflow and structural modeling- Configurations, functionsprocedures- packages - test benches- Design Examples (10) VERILOG: Signals, Identifier Names, Net and Variable Types, operators, Gate instantiations, Verilog module, concurrent and procedural statements, UDP, sub circuit parameters, function and task, -test benches- Design Examples (15) TIMING ISSUES: Modeling delay, Timing Modeling, Timing Assertion, Setup and hold times for clocked devices. SYSTEM MODELLING: Processor model, RAM model, UART Model, Interrupt Controller REFERENCES: 1. Bhasker J, A VHDL Primer, Prentice Hall, 1999. 2. Bhaskar J, VHDL Synthesis Primer, Prentice Hall, 2nd Edition 1998. 3. Bhasker J, A Verilog Primer, Prentice Hall, 1999. 4. Bhaskar J, Verilog Synthesis Primer, Prentice Hall,1999. 5. Stefan Sjoholm and Lennart Lindh, VHDL for Designers 1997. 6. Michael D Ciletti, Advanced Digital Design with Verilog HDL, Pearson education,2005. 7. Douglass Perry, VHDL, Tata McGraw Hill, McGraw-Hill Professional, 4th Edition, May 2002. 8. Volnei A Pedroni, Circuit Design with VHDL, Prentice Hall, 2004. 9. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall NJ, USA, 2003. 10. Neil Weste and Kamran Eshranghian Principles of CMOS VLSI Design, Addison Wesley, 2000. (5) (5) Total 42
Total 42 REFERENCES: 1. Kaushik Roy and Sharat C Prasad Low Power CMOS VLSI circuit Design, John Wiley and Sons, 2000. 2. Gary B Yeap K, "Practical Low Power Digital VLSI Design, Kluwer Academic Publishers, 1998. 3. Kuo J B and Lou J H, Low Voltage CMOS VLSI Circuits, John Wiley and Sons, Singapore, 1999. 4. Anantha P Chandrakasan and Robert W Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Holland, 1995.
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ANALOG CIRCUIT BUILDING BLOCKS: Switches, active resistors - Current sources and sinks - Current mirrors/amplifiers - Voltage and current references, Comparator, Multiplier. (8) AMPLIFIERS: MOS and BJT inverting amplifier - Improving performance of inverting amplifier - CMOS and BJT differential amplifiers - Characterization of Op-Amp - The BJT two stage op-amp - The CMOS two stage op-amp -Opamps with output stage, Folded Cascode op-amp, Transconductance Amplifier. (11) FILTERS: Low pass filters - High pass filters Band Pass filters Phase Locked Loops (6)
DATA CONVERTER FUNDAMENTALS: Ideal A/D and D/A converters, Quantization noise, Signed codes, Performance limitations. (6) D/A AND A/D CONVERTERS: D/A converter : Current scaling, Voltage scaling and Charge scaling D/A converters Serial D/A converters - Serial A/D converters, Parallel - High performance A/D converters. (6) LAYOUT ISSUES: CMOS design rules - layout of CMOS - BJT- Capacitors Resistors - Mixed layout issues: Floor planning, power supply & ground, fully differential matching, Guard rings and shielding. (5) Total 42 REFERENCES: 1. Randall L Geiger, Phillip E Allen and Noel R Strader, "VLSI Design Techniques for Analog and Digital Circuits", McGraw Hill, International Edition, 1990. 2. Jose E Franca Hannis Tsividis, Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing, Prentice Hall, International Edition, 2002. 3. David A Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley and Sons, 2002. 4. Phillip Allen and Douglas Holberg, CMOS Analog Circuit Design, Oxford University Press, 2000. 5. Benhard Razavi, Data Converters, Kluwer Publishers, 2000. 6. Jacob Baker R, Lee H W and Boyce D E, CMOS Circuit Design, Layout and Simulation, Prentice Hall of India, 1998. 7. Mohammed Ismail and Terri Faiz, Analog VLSI Signal and Information Process, Mc-Graw Hill Book Company, 1994. 8. Paul R Gray and Robert G Meyer Analysis and Design of Analog Integrated Circuits, John Wiley and Son,2001.
COMBINATIONAL CIRCUIT TESTING: Test generation algorithms for combinational logic circuits - Fault Table, Boolean difference, Path sensitization, D - algorithm PODEM,FAN algorithms . (12) SEQUENTIAL CIRCUIT TESTING: Functional testing Fault model based testing- Time frame expansion. (5)
FAULT SIMULATION TECHNIQUES: Serial, Single-fault propagation, Deductive, Parallel and Concurrent Simulation. (3) DESIGN FOR TESTABILITY: Key testability concepts Ad Hoc design for Testability scan based design - Signature analysis - Compression techniques-Built-in self-test -Architectures (9) SPECIAL TESTING PROBLEMS: Memory testing techniques- Micro processor and Microcontrollers testing Register decoding - Instruction decoding - data storage, transfer, manipulation functions - Testing analog components. Testability features for board test. FPGA testing. (10) Total 42 REFERENCES: 1. Vishwani D Agarwal, Essential of Electronic Testing for Digital, Memory and Mixed Signal Circuits, Springer, 2000. 2. Abramovici M, Breuer M A and Friedman A D, Digital Systems Testing and Testable Design, Wiley, 1994. 3. Robert J Feugate and Jr Steven M, Introduction to VLSI testing, Prentice Hall, Englewood Cliffs, 1998. 4. Parag K Lala, Digital Circuit Testing and Testability, Academic Press, 1997.
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INTRODUCTION: - -Testing Versus Verification- Verification and Design Reuse. VERIFICATION TECHNIQUES AND TOOLS: Functional Verification, Timing Verification, Formal Verification. Tools-Simulators-Third Party Models-Waveform Viewers-Code Coverage-Issue- Tracking Metrics. Linting
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VERIFICATION PLAN: Verification plan-Levels of Verification-Verification StrategiesSpecification Features Test cases -Test Benches (8) STIMULUS AND RESPONSE: Simple Stimulus- Output Verification Self Checking Test Benches Complex Stimulus and Response Prediction of Output (8) ARCHITECTING TESTBENCHES: Reusable Verification Components VHDL and Verilog Implementation Autonomous Generation and Monitoring Input and Output Paths- Verifying Configurable Design. (8) SYSTEM VERILOG: Data types, RTL design, Interfaces, clocking, Assertion based verification, classes, Test bench automation and constraints. (8) Total 42 REFERNCES 1. Janick Bergeron, Writing Test Benches Functional Verification of HDL Models, Springer 2nd Edition, 2003. 2. Andreas Meyer, Principles of Functional Verification, Newnes, 2003. 3. Samir Palnitkar, Design Verification with e, Prentice Hall, 2003. 4. Kropf T, Introduction to Formal Hardware Verification, Springer Verlag, 2000. 5. Chris spear, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Springer, 2006. 6. Janick Bergeron, Edward Cerny, Alan Hunter and Andrew Nightingale, Verification Methodology Manual for System Verilog, Springer, 2005.
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DIGITAL TO ANALOG & ANALOG TO DIGITAL CONVERTERS: Non-idealities in the DAC - Types of DACs: Current switched, Resistive, Charge redistribution (capacitive), Hybrid, segmented DACs - Techniques for improving linearity Analog to Digital Converters: quantization errors - non-idealities - types of ADCs: Flash, two step, pipelined, successive approximation, folding ADCs. (10) SIGMA DELTA CONVERTERS: Over sampled converters - over sampling with out noise & with noise - implementation imperfections - first order modulator - decimation filters - second order modulator - sigma delta DAC & ADCs. (6) ANALOG AND MIXED SIGNAL EXTENSIONS TO VHDL: Introduction - Language design objectives - Theory of differential algebraic equations - the 1076 .1 Language - Tolerance groups - Conservative systems - Time and the simulation cycle - A/D and D/A Interaction - Quiescent Point - Frequency domain modeling and examples. (6) ANALOG EXTENSIONS TO VERILOG: Introduction - data types Expressions Signals- Analog behavior Hierarchical Structures Mixed signal Interaction. (5) Total 42 REFERENCES: 1. David A Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley and Sons, 2002. 2. Rudy van de Plassche Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer, 1999. 3. Antoniou, Digital Filters Analysis and Design, Tata McGraw Hill, 1998. 4. Phillip Allen and Douglas Holberg CMOS Analog Circuit Design, Oxford University Press, 2000. 5. Benhard Razavi, Data Converters, Kluwer Publishers, 1999. 6. JacobBake R, Harry W Li, and David E Boyce CMOS, Circuit Design Layout and Simulation, Wiley- IEEE Press, 1st Edition Aug, 1997. 7. Tsividis Y P, Mixed Analog and Digital VLSI Devices and Technology, Mc-Graw Hill, 1996.
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Access Memories (DRAM): DRAM Technology Development, CMOS DRAM, DRAM cell theory and advanced cell structures, BiCMOS DRAM, soft error failures in DRAM, Advanced DRAM Design and Architecture, Application Specific DRAM. (9) NON-VOLATILE MEMORIES: Masked Read only Memories (ROM), High Density ROMs, Programmable ROM, Bipolar ROMs, CMOS PROMs, Erasable(UV) Programmable ROM(EPROM), Floating, Gate EPROM Cell, One time Programmable EPROM (OTPEPROM), Electrically Erasable PROMS, EEPROM Technology and Architecture, Non volatile SRAM, Flash Memories (EPROM or EEPROM), Advanced Flash Memory Architecture. (8) MEMORY FAULT MODELLING TESTING AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE: RAM Fault Modeling, Electrical Testing, Peusdo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing. Ram FAULT Modelling, BIST Techniques for Memory. (8) SEMICONDUCTOR MEMORY RELIABILITY AND RADIATION EFFECTS: General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for Reliability-Reliability Test Structures-Reliability Screening and Qualification. Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening Techniques-Radiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing - Radiation Dosimetry-Water Level Radiation Testing and Test Structures (9) ADVANCED MEMORY TECHNOLOGIES AND HIGH-DENSITY MEMORY PACKAGING TECHNOLOGIES: Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories- Magnetoresistive Random Access Memories (MRAMs)-Experimental Memory Devices. Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability Issues-Memory Cards-High Density Memory Packaging Future Directions. (8) Total 42 REFERENCES: 1. Ashok K Sharma, Semiconductor Memories Technology, Testing and Reliability, Wiley, 2002. 2. Ashok K Sharma, Advanced Semiconductor Memories Architecture, Design and Applications, Wiley, 2002.
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DIFFUSION & ION IMPLANTATION: Nature of diffusion-interstitial, Substitutional, interstitial substitutional movements, Diffusion constant, Dissociate process, Diffusion equation- D is constant & function, Diffusion systems, problems in Si Diffusion, Evaluation Techniques Ion Implantation: Penetration range, Implantation Damage, Annealing, Implantation Systems (10) OXIDATION & EPITAXY OXIDATION: Thermal Oxidation-Intrinsic, Extrinsic silicon Glass, Oxide formation, Kinetics of Oxide growth, Oxidation systems, Faults, Anodic Oxidation EPITAXY: Vapour Phase Epitaxy (VPE)- transport, reaction and growth, Chemistry of growth, Insitu etching, Selective epitaxy, imperfections, Liquid Phase Epitaxy, LPE system, Evaluation of epitaxial layers (8) ETCHING & LITHOGRAPHY: LITHOGRAPHY: Pattern generation & Masking, Printing & Engraving-Optical, E-Beam, ion Beam, X-Ray, Photoresists, Defects ETCHING: Wet chemical etching- anisotropic etchants, Etching for non-crystalline films-Plasma etching, Plasma-assisted etching, Cleaning (9) DEVICE & CIRCUIT FABRICATION: Isolation- Mesa, Oxide, PN-junction isolations, Self Allignment, Local Oxidation, Planarisation, Metallisation and Packaging. Circuits N, P and CMOS Transistors, Memory devices, BJT Circuits Buried Layer, PNP and NPN Transistors, Diodes, Resistors, Capacitors. (8) Total 42 REFERENCES: 1. Sorab K Gandhi VLSI Fabrication Principles Silicon and Gallium Arsenide, Wiley Interscience Publications, New York 1983. 2. Sze S M VLSI Technology, McGraw Hill, New York, 1983. 3. Chang S Y and Sze S M, ULSI Technology, McGraw Hill, New York, 1996. 4. Groove A S, Physics and Technology of Semiconductor Devices, Wiley Interscience Publications, New York, 1983. 5. Sze S M, Physics of Semiconductor Devices, 2nd Edition McGraw Hill, New York, 1981.
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MICRO SENSORS: Introduction- microsensors- biomedical sensors-pressure sensors-thermal sensors-chemical sensorsmoptical sensors-microactuation mems with micro actuators (12) Total 42 REFERENCES: 1. Tai-Ran Hsu, MEMS and Microsystems Design and Manufacture, Tata McGraw-Hill, 2002. 2. John A Pelesko, Modelling MEMs and NEMS, CRC press, 2002.
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ARCHITECTURAL SUPPORT FOR SYSTEM DEVELOPMENT: Advanced Microcontroller Bus Architecture ARM Memory Interface ARM Reference Peripheral Specification Hardware System Prototyping Tools Armulator Debug Architecture. (8) ARCHITECTURAL SUPPORT FOR OPERTAING SYSTEM: An Introduction to Operating Systems ARM System Control Coprocessor- CP15 Protection Unit Registers ARM Protection Unit CP15 MMU Registers ARM MMU Architecture Synchronization Context Switching Input and Output. (8) Total 42 REFERENCES: 1. Steve Furber, ARM System on Chip Architecture, Addison- Wesley Professional, 2nd Edition, Aug 2000. 2. Ricardo Reis Design of System on a Chip: Devices and Components Springer, 1st Edition, July 2004. 3. Jason Andrews Co-Verification of Hardware and Software for ARM System on Chip Design (Embedded Technology) Newnes, BK and CD-ROM (Aug 2004). 4. Rashinkar P, Paterson and Singh L, System on a Chip Verification Methodologies and Techniques, Kluwer Academic Publishers, 2001.
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Mixer - Distortion in Single Ended Sampling Mixer - Intrinsic Noise in Single Ended Sampling Mixer - Extrinsic Noise in Single Ended Sampling Mixer- Demodulators. (12) FREQUENCY SYNTHESIZERS: Phase Locked Loops - Voltage Controlled Oscillators - Phase Detector Analog Phase Detectors Digital Phase Detectors - Frequency Dividers - LC Oscillators - Ring Oscillators - Phase Noise - A Complete Synthesizer Design Example (DECT Application). (8) LOOP FILTER: General Description - Design Approaches. (5)
Total 42 REFERENCES: 1. Bosco H Leung VLSI for Wireless Communication, Pearson Education, 2002. 2. Emad N Farag and Mohamed I Elmasry, Mixed Signal VLSI Wireless Design - Circuits and Systems, Kluwer Academic Publishers, 2000.
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SYSTEM RELIABILITY MODELLING: Series and parallel system, time dependent situation and series parallel system - Partial redundancy - Redundancy effectiveness for simple method - Open and short circuit failures - Redundancy involving switching - Standby redundancy (6) RELIABILITY PREDICTION: Monte Carlo method - Random observation from probability distribution - Application of Monte Carlo method - Final design prediction procedure - Development of Reliability formula (6) MAINTAINABILITY AND AVAILABILITY: Objectives and forms of maintainability - Measures of maintainability Availability - Intrinsic availability - Equipment availability. (5) RELIABILITY PHYSICS MODELS: Stress strength models - Accelerated testing - Interpretation of life test data - Human reliability engineering (5) Total 42 REFERENCES: 1. Von Alven, W H, Reliability Engineering, Prentice Hall Inc., New Jersey, 1964. 2. Govil, A K, Reliability Engineering, Tata McGraw Hill Book Company, 1983. 3. Kapur K C and Lamberson L R, Reliability in Engineering Design, John Wiley and Sons, New York, 1977.
EMI MEASUREMENTS: EMI test instrument/systems, EMI test, EMI shielded chamber, Open area test site, TEM cell antennas, conducted sensors/injectors/couplers, military Test method and procedures, Calibration procedures. (8) EMI CONTROL TECHNIQUES: Shielding, Filtering, grounding, bonding, Isolation transformer, Transient suppressors, Cable routing, signal control, Component selection and mounting. (8) EMC DESIGN OF PCBS: PCB traces, Crosstalk, Impedance control, Power distribution decoupling, Zoning, Motherboard Designs, Propagation delay performance models. (5) Total 42 REFERENCES: 1. Clayton R Paul, Introduction to Electromagnetic Compatibility, John Wiley & Sons, 1992. 2. Bernard Keiser, Principles of Electromagnetic Compatibility, Artech House, 3rd Edition, 1994. 3. Henry W Ott, Noise Reduction Techniques in Electronics in electronic Systems, A Wiley -Interscience Publication, John Wiley and sons, 1988. 4. Kodali V P, Engineering EMC Principles, Measurements and Technologies IEEE Press, 1996.
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Design and Simulation of analog circuits using synopsis EDA tool (CosmosSE) Design and Simulation of analog circuits using Cadence EDA tool (Virtuoso and spectre) Timing and power analysis for analog circuit design using Synopsys EDA tool(Prime Time and Prime power) Generation of synthesis report using Mentor Graphics EDA tool (Leonardo spectrum)
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