SEMATECH Symposium June 23, 2011 Tokyo Accelerating the next technology revolution

CMOS Scaling Beyond FinFETs: Nanowires and TFETs

Chris Hobbs, Wei-Yip Loh, Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010
Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

Outline
Advanced CMOS Scaling Overview Nanowires TFETs Summary

14 June 2011

Device scaling options

Id,sat

Vg
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Device scaling options

Id,sat

Vg
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Device scaling options

Very high mobility/high injection velocity SiGe, Ge, InGaAs Graphene [e ~15000 cm2/V-s at RT]

Id,sat

Vg
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Device scaling options

Very high mobility/high injection velocity SiGe, Ge, InGaAs Graphene [e ~15000 cm2/V-s at RT] Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET

Id,sat

Vg
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Why are Multi-Gates beneficial?

Single Gate Device
Gate Source
Extension Halo
Channel

Conventional MOSFET Scaling to improve performance

Drain Source

Lg

Drain

Gate cant control down here, so drain leaks to source Well

Source and drain are much closer Gate looses control of channel region

Thin Silicon Channel

Thin silicon channel with gate on both sides helps maintain channel control.
FinFET
n ai r

Double Gate Device

Fin Gate
D

4-Gate Device

Nanowire Gate
D n ai r

Source

Drain

Gates on both sides

ur So
Si Wafer Surface

ce

c ur So

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Performance and power tradeoff

Typical Ion-Ioff for CMOSFETs

Same transistor with specifications tuned for performance or power @ cost.

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Al m l Fa at c er e i a Tr ls/ an ar si ch st ite or c t Sc ur a es lin /n g I ov s s el ue pr s o c (n es ee se d s) ne w

Performance and power tradeoff

Typical Ion-Ioff for CMOSFETs

Same transistor with specifications tuned for performance or power @ cost.

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MOSFET scaling trends

Planar
High-K 32nm

New materials
22nm? 16nm?

Si-Ge Device

III-V Device 12nm+

45nm

SEMATECH, VLSI 2009 (Production) Intel IEDM 2007 (Production) Intel IEDM 2009 IBM, IEDM 2009 6nm Length B. Doris IEDM 2002

Intel, IEDM 2007,9

SEMATECH, IEDM 2010

2007 2009

2009

2011

2013

2015

Past: Performance improved by scaling device dimensions. Now: Performance improved by Novel Materials and Architectures. Planar CMOS and Beyond: A continuous spectrum of devices.
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Non planar

Intel Tri-Gate, VLSI 2006

NXP FINFET, VLSI 2007

SEMATECH, IEDM 2009

Nano-wire (LETI IEDM08)

10

Non-planar devices
Motivation:
Gate wrap-around helps control short channel effects in scaled devices High mobility channels enables higher drive currents Scaling Pathways
w and w/o 3rd gate ?

OR
High

Heterogeneous

High

Bulk vs SOI

OR

SiN HM

Si BOX
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HfO2 TiN

Homgeneous

11

Critical FinFET/Trigate/Nanowire Modules

Source/Drain SEG, doping and silicide Gate etch Fin Scaling and smoothness Source/Drain SEG, doping and silicide Gate etch NW Scaling and smoothness

Si SiGe Si SiGe Si
Spacer etch and process schemes Processing and integration Group IV channel material

SiGe SiGe BOX Si

Spacer etch and process schemes

Processing and integration

Group IV channel material

FinFET/Trigate

Nanowire

Most nanowire module issues are similar to FinFET module issues with added degree of integration complexity.
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Silicon Nanowires
Wmask = 50 nm

suspended wires 45 source

MG

0n m

Si

HiK

drain
10 nm

Single Si Nanowire Silicide Data

|VD| = 1 V |VD| = 50 mV

450

ID (A/um)

Wmask = 50 nm

nm

PFET

NFET
Gate length = 40 nm NW width = 50 nm NW height = 20 nm

VGS (V)
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Gate wraparound improves rolloff

Swing (V/dec)

Omega Gate FinFET

Nanowire device has smaller rolloff compared to FinFET.

Wrapping gate around channel improves short channel control.

VDS = -50 mV

PFET

Long channel SS is similar for Omega-Gate and FinFET.

Vdd scaling limited by SS. Different device structure needed to reduce Vdd. TFET!

DIBL (V/V)

SiN HM

PFET

Si BOX

HfO2 TiN

Gate-All-Around (GAA) Device:

Total current in nanowire limited by crossectional area. Multiple GAA nanowires to meet ITRS targets. In contrast, total current in FinFET can be increased with taller fins.
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Lmask (nm)

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Stacked Si nanowire formation using SiGe

SiGe/Si Superlattice Fin etch Selective SiGe etch

Si Si Si

SiGe SiGe BOX

Si Si Si

SiGe SiGe

Si
SiGe

Si Si

SiGe

BOX

Suspended NWs

Pt SiN

Si SiGe Si SiGe Si

BOX

Si SiGe Si SiGe Si

200 nm Si

BOX

Stacking nanowires helps increase total drive current to meet ITRS targets.
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High mobility SiGe FinFETs/nanowires

350 300
(110)

SiGe fin SiGe {100}<100>

(Tinv= 1.8nm) Si {110}<110>

SiGe {110}<110>

eff (cm /V-s)

250 200 150 100 50 0 0

(100)

shell/core fin (100) universal

(Tinv=1.5nm)

Si {100}<100>

Si fin
(Tinv = 1.2nm)

Universal (100)
13

1x10

2x10
3

13

NINV (#/cm )

Extracted by Split CV Method

SiGe PFETs have higher mobility than Si fins. Potential for performance > strained Si in non-planar devices
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Outline
Advanced CMOS Scaling Overview Nanowires TFETs Summary

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17

Device scaling options

Very high mobility/high injection velocity SiGe, Ge, InGaAs Graphene [e ~15000 cm2/V-s at RT] Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET Improve on-off ratio Tunnel FET Very steep SS << 60 mV/dec Low bias voltages (<< 1V) Nano Electro Mechanical switch (NEMS) Hybrid: Ion by CMOS + Ioff by NEMS Zero Leakage Power

Id,sat

Vg
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Device scaling options

Very high mobility/high injection velocity SiGe, Ge, InGaAs Graphene [e ~15000 cm2/V-s at RT] Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET Improve on-off ratio Tunnel FET Very steep SS << 60 mV/dec Low bias voltages (<< 1V) Nano Electro Mechanical switch (NEMS) Hybrid: Ion by CMOS + Ioff by NEMS Zero Leakage Power

Id,sat
3

Vg
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VCC scaling for green electronics

1E+03

Power Density (W/cm2)

Active Power Density

1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 1E-04 Passive Power Density

1E-05 0.01

0.1

Gate Length (m)

(B. Meyerson et al., , IBM, Semico Conf., 2004)

(P. Packan (Intel), 2007 IEDM Short Course)

Passive power has shown continuous increase due to VDD scaling limit. VCC scaling limited by VT and subthreshold slope (which is kT/q limited) need green devices not governed by kT/q ~ 60mV/dec limit.
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Working mechanism of TFET

MOSFET
Low ION Log ID
COX VG S

High IOFF
Operation Range

Ec Ev

CDEP

MOSFET: For Narrow On/Off Voltage Range:

Low Ioff Low Ion High Ion High Ioff

0.0

0.2

0.4

0.6

0.8

1.0

Cox q I DS exp( VGS ) Cox Cdep kT

1.5 1.0
Energy [eV]

TFET

0.5 0.0 -0.5 -1.0 -1.5

ON

Log ID

OFF

EC EV
40 50 X [nm] 60 70

0.0

0.2

0.4

0.6

0.8

1.0

-2.0 20

30

Electrons go over thermionic energy barrier Boltzmann distribution of carriers causes leakage. TFET: Carriers go through the energy barrier.

Band-to-Band Tunneling, SS < 60mV/dec

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Si PIN tunneling FETs

10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10
-5

5x10 4x10 3x10 2x10

-6

VG=-2.0V
-6

-6

ID [A/um]

-6

VG=-1.5V

1x10

-6

46mV/dec
-1.5

VG=-1.0V

-2.0

VG [V]

-1.0

-0.5

0.0

0 -2.0

-1.5

VD [V]

-1.0

-0.5

0.0

Several types TFETs with Si PIN, Metal Schottky PIN and Si-pocket PIN have been demonstrated. Ultra-low subthreshold of < 50 mV/dec has been achieved over 103 order of drive current.
SEMATECH-UCB DARPA STEEP Project
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Very Low SS, need more Ion.

22

ND activation for high Ion Si TFET

SEMATECH-UCB ESSDERC 2010

10 10

-3 -4 -5 -6 -7 -8 -9

Idrain (A/m)

Experimental Sim. Overlap 10nm Sim. Overlap 5nm Sim. Overlap 0nm

10 10 10 10

-6

-7

Lg ~ 46 nm Vg = 0V

Lg = 56nm
Metal gate

SiN spacer High-K

ID (A/m)

10 10 10 10

-8

I ITunnel Thermonic

-9

NiSi

n+

80nm Si p+

NiSi

10 10

-10

10

Temp = 213K~313K in step of 20K

-11

-2.0 -1.5 -1.0 -0.5 0.0 0.5

Highest Ion (~ 109 A/m) at Vcc = 1.0V for Si TFET using optimized flash anneal for Nd activation. Good Ion, poor SS.

Vgate-VBT (V)

-0.2 0.0 0.2 0.4 0.6

Vds (V)
Vds (V) 0.75 1.00 1.00 0.80 0.80 1.50 1.00 0.70 1.00

References S. Mookerjea [1] T. Krishnamohan [2] T. Krishnamohan [2] F. Mayer [3] F. Mayer [3] K. K. Bhuwalka [4] W. Y. Choi [5] This work [6]
1

Channel SS (mV/dec) Material @ RT InGaAs 150~290 Ge 50 ~ 60 Si 460 Ge >400 Si Si Si Si 42 ~ 200 285 52.8 120 ~ 250

Ion (A/m) 20 10 -4 10 4 0.04 0.1 12* 84 109

Ion/Ioff > 10 6 10 2 > 10 2 > 10 10 10

5 4 4 3

[1] IEDM Tech. Dig. 2009, p.949. [2] IEDM Tech. Dig. 2008, p. 947. [3] IEDM Tech. Dig. 2008, p. 163. [4] IEEE Trans, ED., vol 51(2), p. 279, 2004. [5] IEEE EDL, vol. 28(8), p. 743, 2007. [6] 40th ESSDERC 2010, p162

10 5 >10 4 >10

Ion is taken at overdrive of Vg-VBT = 2.0V except for *. Ioff taken at onset of BT-BT, VBT
23

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Eg engineering : H-TFET
Effective Eg can be engineered by using heterostructure (e.g. Ge on Si) Ge % from 25 ~ 50% Bandgap engineering to enhance tunneling Abrupt doping gradient by in-situ Bdoped SiGe and post annealing
n+ Si (Drain) Gate p+Ge (Source)

i-Si Heterostructure TFET

Ec offset and bandgap narrowing for high tunneling g g g

SEMATECH-UCB DARPA Joint Project

Much lighter Hole mass

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III-V tunnel FETs

(InAs) Eg=0.36eV, Vd=0.2V
1E03 Drain Current (A/m)
10
13

High Dit
In0.53GaAs CB edge
10

Junction Leakage
3

Dit (#/cm /eV

1E06 -

VB edge
12

Idiode (A/cm )

(Ge) Eg=0.69eV, Vd=0.5V

10 10 10 10 10

n+i-p+ In0.53GaAs Diodes

-1

1st lot 2nd lot

(Si) Eg=1.1eV, Vd=1V

10

-3

1E09 0.0 0.2 0.4 0.6 0.8 1.0

-5

p-Type

n-Type

Gate Voltage (V)

10

11

-7

-2.0 -1.5 -1.0 -0.5 0.0 0.5

-1.0

-0.5

[C. Hu et al, VLSI-TSA, pp.14-15, 2008]

Vgate (V)

Vdiode (V)

0.0

0.5

1.0

Tunneling is a strong function of bandgap. III-V has smaller bandgap and heterostructures (e.g. InAs/AlxGa1-xSb) have staggered or even zero bandgap direct tunneling. Preliminary InGaAs TFETs results indicates further optimization is needed to improve the poor SS, high Ioff, high Dit and poor Rco.
25

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Novel design: pocket structure TFET

P+ Pocket N+ S ource PBuried Oxide P+ Drain

[ C. Hu et al, VLSI-TSA, April, 2008 ]

Large field, good capacitive coupling btw gate & pocket Abrupt turn-on due to overlap of valence/conduction bands Tunable turn-on voltage
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Dopant-segregated Si-pocket TFET

SEMATECH-UCB VLSI Symp. 2010

NiSi Achieved sub-60 mV/dec (46mV/dec) with 30% dies showing sub60mV/dec Si TFET with high-K/MG
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Schottky-Source P-I-N TFET Silicon

Gate

BOX
100nm
10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10
-4

NiSi
BOX

N+ Si

Gate
NiSi

Si

Probability

ID [A/m]

BOX N+ < Pocket >

Gate
NiSi

Si

20

60 100 140 180 220 Subthreshold Swing [mV/dec]

Measured Sim. w/ pocket Sim. no pocket

BOX N+ < No Pocket >

-1.5

-1.0

V G [V]

-0.5

0.0

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27

S-MLD pocket InGaAs pocket TFETs

10 10
-4 -5 -6 -7 -8 -9

Pocket

AlOx

Idrain (A/m

10 10 10 10

n+

AlOx
i

Control
V g-V BT = 0.2 V to 1.5 V L g = 100 nm -0.5 in step of 0.1 V 0.0 0.5
13

P++ P+

N+

Tunneling Front

P++ P+

N+

10 10
4

-10 -11

TFET with pocket

Control TFET

-1.0

V drain (V)

1.0
Control Pocket VB edge CB edge

10

N+/p- pocket structure achieved on InGaAs TFET. Enhanced drive current obtained due to enhanced vertical field at gated pocket n-p+ junction. Improved gate coupling and Dit observed.
28

300K

pocket
2

Dit (#/cm /eV

PVCR

10

12

C o n tro l
1 0 .5 1 .0 1 .5 2 .0

p-Type
10
11

n-Type

V g a te (V )

-2.0 -1.5 -1.0 -0.5 0.0 0.5

Vgate (V)

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Simulation of TFETs
IV TFETs (Simulation)
10
-3

IIIV TFETs (Simulation)

10
-3

Ge/Si pocket [1]

s-Ge/s-Si [2]

Ge pocket [1]
-5

Si pocket [1] Ge UTB [4]

Idrain (A/m

Idrain (A/m

10 10 10

Ge-source Si NW [3]

10 10 10

-5

SG Pocket Eg =0.36 [1] GaSb-InAs UTB [7] GaSb-InAs NW [7]

InSb UTB [7] InGaAs [8] Eg = 0.72 eV InAs NW [6] Eg = 0.37 eV

60 mV/dec
-7

Ge NW [3] Si NW [3]

-7

InSb NW [7] 60 mV/decEg = 0.17 eV

-9

Si PNPN [5] Intel 32nm LP IEDM 2009 [9]

Si TFET Ge TFET Si MOSFET

-9

Intel 32nm LP IEDM 2009 [9]

10

-11

0.0

0.2

Vgate (V)

0.4

0.6

0.8

1.0

10

-11

0.0

0.2

Vgate (V)

0.4

0.6

0.8

1.0

[1] C. Hu et al. (invited), VLSI-TSA 2008 [3] A.S. Verhulst et al., APL, 104, 064514, 2008. [5] V. Nagavarapu et al., TED, 1013, 2008. [7] M. Luisier et al., IEDM, 913, 2009.
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[2] O.M. Nayfeh et al., EDL, 1074, 2008. [4] Q. Zhang et al., Solid-State Elect. 30, 2009. [6] M. Luisier et al., EDL, 602, 2009. [8] S. Mookerjea et al., IEDM, 949, 2009.
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Current TFET performance

P-TFET (experimental)
10
-3

N-TFET (experimental)
10
-3

Idrain (A/m

32nm pFET [9] (LP)

p-channel

n-channel
Si TFET[12] Lg = 70nm

PNPN Si TFET [5] Lg = 1m

10 10 10

-5

60 mV/dec
DSS Si TFET [17] Lg = 20 m SOI TFET [14] Lg = 100 nm Si TFET [16] Lg = 56 nm

Idrain (A/m

60 mV/dec

32nm nFET
GeOI TFET [14] Lg = 0.4 m

10 10 10

-5

-7

-7

In0.53GaAs
-9

In0.7GaAs

-9

10

-11

-1.0 -0.8 -0.6 -0.4 -0.2

Vgate (V)

0.0

0.2

10

-11

Ge-source TFET [15] Lg = 5m

TFET [13] TFET [8] L = 100nm g Lg = 100nm

0.0

0.2

Vgate (V)

0.4

0.6

0.8

1.0

Experiments show higher sub-threshold slope than simulations. No physical demonstration of TFET with both high Ion > 100 A/m and SS < 60 mV/dec has been demonstrated so far.
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Summary
Power Constrained CMOS Scaling requires new materials and device structures to enable continued scaling. Nanowires:
Better short channel control than FinFETs with added degree of integration complexity

TFETs:
Band to band tunneling transport mechanism allows for sub60mV subthreshold slope
Vcc reduction lower power consumption

TFETs simulations show promise for Vcc reduction and additional process improvements are needed to improve device performance.
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