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SEMATECH Symposium June 23, 2011 Tokyo Accelerating the next technology revolution CMOS Scaling Beyond FinFETs:

SEMATECH Symposium June 23, 2011 Tokyo

Accelerating the next technology revolution

CMOS Scaling Beyond FinFETs:

Nanowires and TFETs

Chris Hobbs, Wei-Yip Loh, Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010

Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010 Copyright ©2009 SEMATECH, Inc. SEMATECH, and
Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010 Copyright ©2009 SEMATECH, Inc. SEMATECH, and
Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010 Copyright ©2009 SEMATECH, Inc. SEMATECH, and

Copyright ©2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

Outline

Outline • Advanced CMOS Scaling Overview • Nanowires • TFETs • Summary 14 June 2011 2

Advanced CMOS Scaling Overview Nanowires

TFETs

Summary

d,sat

I

Device scaling options

d , s a t I Device scaling options V g 14 June 2011 3

V g

d , s a t I Device scaling options V g 14 June 2011 3

Device scaling options

Device scaling options I d,sat V g 14 June 2011 4
I d,sat
I
d,sat

V g

Device scaling options I d,sat V g 14 June 2011 4

Device scaling options

Device scaling options 1 I d,sat V g • Very high mobility/high injection velocity • SiGe,
1 I d,sat
1
I
d,sat

V g

Very high mobility/high injection velocity

SiGe, Ge, InGaAs

Graphene [e ~15000 cm 2 /V-s at RT]

Device scaling options

Device scaling options 2 1 I d,sat V g • Very high mobility/high injection velocity •
2 1 I d,sat
2
1
I
d,sat

V g

Very high mobility/high injection velocity

SiGe, Ge, InGaAs

Graphene [e ~15000 cm 2 /V-s at RT]

Better electrostatic control

Multiple gates + more channel area

FinFETs, nanowire FET

Why are Multi-Gates beneficial?

Why are Multi-Gates beneficial? Lg Gate Conventional MOSFET Scaling to improve performance Channel Source Drain
Lg Gate Conventional MOSFET Scaling to improve performance Channel Source Drain Source Drain Extension Halo
Lg
Gate
Conventional MOSFET Scaling
to improve performance
Channel
Source
Drain
Source
Drain
Extension
Halo
Gate can’t control down here,
so drain leaks to source
Source and drain are much closer…
Gate looses control of channel region
Well
Thin silicon channel with gate on both
sides helps maintain channel control.
Single Gate Device

Thin

Silicon FinFET Fin Channel Gate Source Drain Gates on Si Wafer Surface both sides Double
Silicon
FinFET
Fin
Channel
Gate
Source
Drain
Gates on
Si Wafer Surface
both sides
Double Gate Device
Source
Drain

Nanowire

Gate Source Drain 4-Gate Device
Gate
Source
Drain
4-Gate Device

Performance and power tradeoff

Performance and power tradeoff Typical Ion-Ioff for CMOSFETs • Same transistor with specifications tuned for
Typical Ion-Ioff for CMOSFETs
Typical Ion-Ioff for CMOSFETs

Same transistor with specifications tuned for performance or power @ cost.

All Face Transistor Scaling Issues (need new Performance and power tradeoff Typical Ion-Ioff for CMOSFETs
All Face Transistor Scaling Issues (need new
All Face Transistor Scaling Issues
(need new

Performance and power tradeoff

Typical Ion-Ioff for CMOSFETs materials/architectures/novel processes)
Typical Ion-Ioff for CMOSFETs
materials/architectures/novel
processes)

Same transistor with specifications tuned for performance or power @ cost.

MOSFET scaling trends

MOSFET scaling trends Planar 45nm (Production) Intel IEDM 2007 High-K 32nm (Production) Intel IEDM 2009 New

Planar

45nm

MOSFET scaling trends Planar 45nm (Production) Intel IEDM 2007 High-K 32nm (Production) Intel IEDM 2009 New

(Production) Intel IEDM 2007

High-K

32nm

trends Planar 45nm (Production) Intel IEDM 2007 High-K 32nm (Production) Intel IEDM 2009 New materials 22nm?

(Production) Intel IEDM 2009

New materials

22nm?

32nm (Production) Intel IEDM 2009 New materials 22nm? IBM, IEDM 2009 16nm? 6nm Length B. Doris

IBM, IEDM 2009

16nm?

Intel IEDM 2009 New materials 22nm? IBM, IEDM 2009 16nm? 6nm Length B. Doris IEDM 2002

6nm Length B. Doris IEDM 2002

Si-Ge Device

IEDM 2009 16nm? 6nm Length B. Doris IEDM 2002 Si-Ge Device SEMATECH, VLSI 2009 III-V Device

SEMATECH,

VLSI 2009

III-V Device

12nm+

2002 Si-Ge Device SEMATECH, VLSI 2009 III-V Device 12nm+ Intel, SEMATECH, IEDM 2007,9 IEDM 2010 2007
2002 Si-Ge Device SEMATECH, VLSI 2009 III-V Device 12nm+ Intel, SEMATECH, IEDM 2007,9 IEDM 2010 2007

Intel,

SEMATECH,

IEDM 2007,9

IEDM 2010

2007

2009

2011

2013

2015

IEDM 2007,9 IEDM 2010 2007 2009 2011 2013 2015 • Past: Performance improved by scaling device

Past: Performance improved by scaling device dimensions.

Now: Performance improved by Novel Materials and Architectures.

Planar CMOS and Beyond:

A continuous spectrum of devices.

Non planar

and Beyond: A continuous spectrum of devices. Non planar Intel Tri-Gate, NXP FINFET, SEMATECH, VLSI 2006
and Beyond: A continuous spectrum of devices. Non planar Intel Tri-Gate, NXP FINFET, SEMATECH, VLSI 2006
and Beyond: A continuous spectrum of devices. Non planar Intel Tri-Gate, NXP FINFET, SEMATECH, VLSI 2006

Intel Tri-Gate,

NXP FINFET,

SEMATECH,

VLSI 2006

VLSI 2007

IEDM 2009

Tri-Gate, NXP FINFET, SEMATECH, VLSI 2006 VLSI 2007 IEDM 2009 Nano-wire (LETI IEDM’08) 14 June 2011

Nano-wire

(LETI IEDM’08)

Tri-Gate, NXP FINFET, SEMATECH, VLSI 2006 VLSI 2007 IEDM 2009 Nano-wire (LETI IEDM’08) 14 June 2011

Non-planar devices

Motivation:

Non-planar devices Motivation: – Gate wrap-around helps control short channel effects in scaled devices – High

Gate wrap-around helps control short channel effects in scaled devices

High mobility channels enables higher drive currents

OR Scaling Pathways High  w and w/o 3 rd gate ? High  Bulk
OR
Scaling Pathways
High 
w and w/o 3 rd gate ?
High 
Bulk vs SOI
OR
Heterogeneous
Homgeneous
SiN HM HfO 2 Si TiN BOX
SiN HM
HfO 2
Si
TiN
BOX
w and w/o 3 rd gate ? High  Bulk vs SOI OR Heterogeneous Homgeneous SiN
w and w/o 3 rd gate ? High  Bulk vs SOI OR Heterogeneous Homgeneous SiN
w and w/o 3 rd gate ? High  Bulk vs SOI OR Heterogeneous Homgeneous SiN
w and w/o 3 rd gate ? High  Bulk vs SOI OR Heterogeneous Homgeneous SiN
w and w/o 3 rd gate ? High  Bulk vs SOI OR Heterogeneous Homgeneous SiN

14 June 2011

11

Critical FinFET/Trigate/Nanowire Modules

Critical FinFET/Trigate/Nanowire Modules Source/Drain Gate etch Fin Scaling and smoothness SEG, doping and silicide
Source/Drain Gate etch Fin Scaling and smoothness SEG, doping and silicide Spacer etch and Processing
Source/Drain
Gate etch
Fin Scaling and
smoothness
SEG, doping
and silicide
Spacer
etch and
Processing
process
and
schemes
Group IV
integration
channel
material
FinFET/Trigate
Source/Drain Gate etch NW Scaling and smoothness SEG, doping and silicide Si SiGe SiGe Si
Source/Drain
Gate etch
NW Scaling and
smoothness
SEG, doping
and silicide
Si
SiGe
SiGe
Si
SiGe
SiGe
Si
BOX
Processing
Spacer
and
Si
etch and
integration
process
schemes
Group IV
channel
material
Nanowire

Most nanowire module issues are similar to FinFET module issues with added degree of integration complexity.

Silicon Nanowires

450 nm W mask = 50 nm suspended wires source drain
450 nm
W mask = 50 nm
suspended
wires
source
drain
MG HiK Si 1010 nmnm
MG
HiK
Si
1010 nmnm
nm suspended wires source drain MG HiK Si 1010 nmnm Single Si Nanowire Silicide Data |V

Single Si Nanowire Silicide Data

|V D | = 1 V |V D | = 50 mV W mask =
|V D | = 1 V
|V D | = 50 mV
W mask = 50 nm
PFET
NFET
Gate length = 40 nm
NW width = 50 nm
NW height = 20 nm
V GS (V)
14 June 2011
13
I D (A/um)

DIBL (V/V)

Gate wraparound improves rolloff

DIBL (V/V) Gate wraparound improves rolloff Omega Gate FinFET V DS = -50 mV PFET Swing
Omega Gate FinFET V DS = -50 mV PFET Swing (V/dec)
Omega Gate
FinFET
V DS = -50 mV
PFET
Swing (V/dec)
PFET SiN HM HfO 2 Si TiN BOX
PFET
SiN HM
HfO 2
Si
TiN
BOX

Lmask (nm)

Nanowire device has smaller rolloff compared to FinFET.

Wrapping gate around channel improves short channel control.

Long channel SS is similar for Omega-Gate and FinFET.

Vdd scaling limited by SS.

Different device structure needed to reduce Vdd. TFET!

Gate-All-Around (GAA) Device:

Total current in nanowire limited by crossectional area.

Multiple GAA nanowires to meet ITRS targets.

In contrast, total current in FinFET can be increased with taller fins.

Stacked Si nanowire formation using SiGe

Stacked Si nanowire formation using SiGe SiGe/Si Superlattice Fin etch SiGe Si Si SiGe SiGe Si

SiGe/Si Superlattice

Fin etch

SiGe Si Si SiGe SiGe Si Si SiGe Si Si BOX BOX
SiGe
Si
Si
SiGe
SiGe
Si
Si
SiGe
Si
Si
BOX
BOX
Selective SiGe etch Si SiGe Si SiGe Si Suspended NWs
Selective SiGe etch
Si
SiGe
Si
SiGe
Si
Suspended
NWs
Pt SiN Si SiGe Si SiGe Si BOX 200200 nmnm Si
Pt
SiN
Si
SiGe
Si
SiGe
Si
BOX
200200 nmnm
Si
Si SiGe Si SiGe Si BOX
Si
SiGe
Si
SiGe
Si
BOX
SiGe Si BOX 200200 nmnm Si Si SiGe Si SiGe Si BOX • Stacking nanowires helps

Stacking nanowires helps increase total drive current to meet ITRS targets.

High mobility SiGe FinFETs/nanowires

High mobility SiGe FinFETs/nanowires 350 SiGe {110}<110> (110) SiGe fin 300 SiGe {100}<100> (Tinv=
350 SiGe {110}<110> (110) SiGe fin 300 SiGe {100}<100> (Tinv= 1.8nm) Si {110}<110> Si
350
SiGe {110}<110>
(110)
SiGe fin
300
SiGe {100}<100>
(Tinv= 1.8nm)
Si {110}<110>
Si {100}<100>
250
shell/core fin
(100) universal
(Tinv=1.5nm)
200
Si fin
150
(Tinv = 1.2nm)
100
50
(100)
Universal (100)
0
0
1x10 13
2x10 13
 eff (cm 2 /V-s)

N INV (#/cm 3 )

Extracted by Split CV Method

SiGe PFETs have higher mobility than Si fins.

Potential for performance > strained Si in non-planar devices

Outline

Outline • Advanced CMOS Scaling Overview • Nanowires • TFETs • Summary 14 June 2011 17

Advanced CMOS Scaling Overview Nanowires

TFETs

Summary

Device scaling options

Device scaling options 2 1 I d,sat V g • Very high mobility/high injection velocity •
2 1 I d,sat
2
1
I
d,sat

V g

Very high mobility/high injection velocity

SiGe, Ge, InGaAs

Graphene [e ~15000 cm 2 /V-s at RT]

Better electrostatic control

Multiple gates + more channel area

FinFETs, nanowire FET

Improve on-off ratio

Tunnel FET

Very steep SS << 60 mV/dec

Low bias voltages (<< 1V)

Nano Electro Mechanical switch (NEMS)

Hybrid: I on by CMOS + I off by NEMS

Zero Leakage Power

Device scaling options

Device scaling options 2 1 3 I d,sat V g • Very high mobility/high injection velocity
2 1 3 I d,sat
2
1
3
I
d,sat

V g

Very high mobility/high injection velocity

SiGe, Ge, InGaAs

Graphene [e ~15000 cm 2 /V-s at RT]

Better electrostatic control

Multiple gates + more channel area

FinFETs, nanowire FET

Improve on-off ratio

Tunnel FET

Very steep SS << 60 mV/dec

Low bias voltages (<< 1V)

Nano Electro Mechanical switch (NEMS)

Hybrid: I on by CMOS + I off by NEMS

Zero Leakage Power

V CC scaling for “green” electronics

V C C scaling for “green” electronics 1E+03 Active Power Density 1E+02 1E+01 1E+00 1E-01 1E-02
1E+03 Active Power Density 1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 Passive Power Density 1E-04 1E-05
1E+03
Active Power Density
1E+02
1E+01
1E+00
1E-01
1E-02
1E-03
Passive Power Density
1E-04
1E-05
0.01
0.1
1
Power Density (W/cm 2 )

Gate Length (μm)

0.01 0.1 1 Power Density (W/cm 2 ) Gate Length ( μ m) (B. Meyerson et

(B. Meyerson et al., , IBM, Semico Conf., 2004)

(P. Packan (Intel), 2007 IEDM Short Course)

• Passive power has shown continuous increase due to V DD scaling limit.

• V CC scaling limited by V T and subthreshold slope (which is kT/q limited)

need “green” devices not governed by kT/q ~ 60mV/dec limit.

Working mechanism of TFET

MOSFET

Low I ON High I OFF Operation Range Log I D
Low
I
ON
High
I
OFF
Operation
Range
Log I D

0.0

0.2

0.4

0.6

0.8

TFET

1.0

0.0 0.2 0.4 0.6 0.8 1.0 Log I D Energy [eV]
0.0
0.2
0.4
0.6
0.8
1.0
Log I D
Energy [eV]
V G φ S C OX E C c DEP E v q C ox
V G
φ S
C
OX
E
C
c
DEP
E
v
q
C ox
 exp(
)
I DS
V GS
C
 C
kT
ox
dep
1.5 1.0 0.5 OFF 0.0 E C -0.5 -1.0 ON E V -1.5 -2.0 20
1.5
1.0
0.5
OFF
0.0
E C
-0.5
-1.0
ON
E V
-1.5
-2.0
20
30
40
50
60
70

X [nm]

-1.0 ON E V -1.5 -2.0 20 30 40 50 60 70 X [nm] MOSFET: •

MOSFET:

For Narrow On/Off Voltage Range:

Low Ioff Low Ion

High Ion High Ioff

Electrons go over thermionic energy barrier

Boltzmann distribution of carriers causes

leakage. TFET:

Carriers go through

the energy barrier.

Band-to-Band Tunneling, SS < 60mV/dec

Si PIN tunneling FETs

Si PIN tunneling FETs I D [A/um] SEMATECH-UCB DARPA STEEP Project -5 10 -6 10 -7
I D [A/um]
I D [A/um]

SEMATECH-UCB DARPA STEEP Project

-5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
46mV/dec
10
-14
10
-2.0
-1.5
-1.0
-0.5
0.0
V G [V]

5x10

4x10

3x10

2x10

1x10

-6 V G =-2.0V -6 -6 V G =-1.5V -6 -6 V G =-1.0V 0
-6
V
G =-2.0V
-6
-6
V
G =-1.5V
-6
-6
V
G =-1.0V
0
-2.0
-1.5
-1.0
-0.5
0.0

V D [V]

Several types TFETs with Si PIN, Metal Schottky PIN and Si-pocket PIN have been demonstrated.

Ultra-low subthreshold of < 50 mV/dec has been achieved over 10 3 order of drive current.

Very Low SS, need more Ion.

14 June 2011

22

N D activation for high I on Si TFET

SEMATECH-UCB ESSDERC 2010

SiN SiN L g = 56nm L = 56nm spacer spacer g High-K High-K Metal
SiN
SiN
L g = 56nm
L
= 56nm
spacer
spacer
g
High-K
High-K
Metal gate
Metal gate
NiSi
NiSi
NiSi
NiSi
n+
n+
80nm Si
80nm Si
p+
p+
-3 -6 10 Experimental 10 Sim. Overlap 10nm -4 10 Sim. Overlap 5nm -7 10
-3
-6
10
Experimental
10
Sim.
Overlap 10nm
-4
10
Sim.
Overlap 5nm
-7
10
Sim.
Overlap 0nm
-5
10
-8
10
-6
10
-9
10
-7
10
-10
-8
10
10
-9
10
-11
10
-2.0 -1.5 -1.0 -0.5 0.0
0.5
I D (A/m)
I drain (A/m)
L g ~ 46 nm V g = 0V I Thermonic I Tunnel Temp =
L g ~ 46 nm
V g = 0V
I Thermonic
I Tunnel
Temp = 213K~313K
in step of 20K
-0.2 0.0
0.2
0.4
0.6

• Highest I on (~ 109 A/m) at Vcc = 1.0V for Si TFET using optimized flash anneal for N d activation.

• Good Ion, poor SS.

[1] IEDM Tech. Dig. 2009, p.949. [2] IEDM Tech. Dig. 2008, p. 947. [3] IEDM Tech. Dig. 2008, p. 163. [4] IEEE Trans, ED., vol 51(2), p. 279, 2004. [5] IEEE EDL, vol. 28(8), p. 743, 2007. [6] 40th ESSDERC 2010, p162

V gate -V BT (V)

V ds (V)

References

Channel

SS (mV/dec)

Ion 1

V ds (V)

Ion/Ioff 1

Material

@ RT

(A/m)

S.

Mookerjea [1]

InGaAs

150~290

20

0.75

>

10 3

T.

Krishnamohan [2]

Ge

50 ~ 60

10

1.00

 

10

6

T.

Krishnamohan [2]

Si

460

10

-4

1.00

>

10 2

F.

Mayer [3]

Ge

>400

4

0.80

>

10 2

F.

Mayer [3]

Si

42 ~ 200

0.04

0.80

 

10

5

K.

K. Bhuwalka [4]

Si

285

0.1

1.50

 

10

4

W. Y. Choi [5]

Si

52.8

12*

1.00

 

10

4

This work

[6]

Si

 

84

0.70

>10 5

120 ~ 250

109

1.00

>10 4

1 Ion is taken at overdrive of V g -V BT = 2.0V except for *. Ioff taken at onset of BT-BT, V BT

E g engineering : H-TFET

E g engineering : H-TFET • Effective E g can be engineered by using heterostructure (e.g.

• Effective E g can be engineered by using heterostructure (e.g. Ge on Si)

• Ge % from 25 ~ 50% Bandgap engineering to enhance tunneling

• Abrupt doping gradient by in-situ B- doped SiGe and post annealing

n+ Si

(Drain)

Gate Gate
Gate
Gate

p+Ge

(Source)

i-Si
i-Si
i-Si

i-Si

i-Si
i-Si
i-Si
i-Si
post annealing n+ Si (Drain) Gate Gate p+Ge (Source) i-Si SEMATECH-UCB DARPA Joint Project Heterostructure TFET

SEMATECH-UCB DARPA Joint Project

Heterostructure TFET

Heterostructure TFET

Ec offset and bandgap narrowing for high tunneling

TFET Heterostructure TFET Ec offset and bandgap narrowing for high tunneling Much lighter Hole mass 14

Much lighter Hole mass

III-V tunnel FETs

(InAs) Eg=0.36eV, Vd=0.2V

13 10 1E-03 (Ge) Eg=0.69eV, 1E-06 12 10 (Si) Eg=1.1eV, Vd=1V 1E-09 0.0 0.2 0.4
13
10
1E-03
(Ge) Eg=0.69eV,
1E-06
12
10
(Si) Eg=1.1eV, Vd=1V
1E-09
0.0
0.2
0.4
0.6
0.8
1.0
10 11
Drain Current
D it (#/cm 2 /eV

Gate Voltage (V)

[C. Hu et al, VLSI-TSA, pp.14-15, 2008]

High Dit

In 0.53 GaAs CB edge VB edge p-Type n-Type I diode (A/cm 2 )
In 0.53 GaAs
CB edge
VB edge
p-Type
n-Type
I diode (A/cm 2 )

-2.0 -1.5 -1.0 -0.5 0.0

V gate (V)

0.5

(A/cm 2 ) -2.0 -1.5 -1.0 -0.5 0.0 V gate ( V ) 0.5 Junction Leakage
Junction Leakage 3 10 n+i-p+ In 0.53 GaAs Diodes 1 10 1st lot 2nd lot
Junction Leakage
3
10
n+i-p+
In 0.53 GaAs Diodes
1
10
1st lot
2nd lot
-1
10
-3
10
-5
10
-7
10
-1.0
-0.5
0.0
0.5
1.0

V diode (V)

• Tunneling is a strong function of bandgap.

• III-V has smaller bandgap and heterostructures (e.g. InAs/Al x Ga 1-x Sb) have staggered or even zero bandgap direct tunneling.

• Preliminary InGaAs TFETs results indicates further optimization is needed to improve the poor SS, high I off , high Dit and poor R co .

Novel design: pocket structure TFET

Novel design: pocket structure TFET P+ Pocket N+ Source P+ Drain P- Buried Oxide [ C.
P+ Pocket N+ Source P+ Drain P- Buried Oxide
P+ Pocket
N+ Source
P+ Drain
P-
Buried Oxide
TFET P+ Pocket N+ Source P+ Drain P- Buried Oxide [ C. Hu et al, VLSI

[ C. Hu et al, VLSI-TSA, April, 2008 ]

Large field, good capacitive coupling btw gate & pocket

Abrupt turn-on due to overlap of valence/conduction bands

Tunable turn-on voltage

Dopant-segregated Si-pocket TFET

SEMATECH-UCB VLSI Symp. 2010

Achieved sub-60 mV/dec (46mV/dec) with 30% dies showing sub- 60mV/dec Si TFET with high-K/MG

100nm

NiSi

100nm NiSi BOX

BOX

sub- 60mV/dec Si TFET with high-K/MG 100nm NiSi BOX Gate Gate N+ N+ NiSi NiSi Si
Gate Gate N+ N+ NiSi NiSi Si Si BOX BOX
Gate
Gate
N+
N+
NiSi
NiSi
Si
Si
BOX
BOX
-4 10 0.9 -5 10 0.8 -6 10 0.7 -7 10 0.6 -8 10 0.5
-4
10
0.9
-5
10
0.8
-6
10
0.7
-7
10
0.6
-8
10
0.5
-9
10
0.4
-10
10
0.3
-11
10
0.2
-12
Schottky-Source
10
0.1
SiliconSilicon TFETTFET
P-I-N
-13
10
0.0
-14
20
60
100
140
180
220
10
Probability
I D [A/m]
Gate NiSi Si BOX N+ < Pocket > Gate NiSi Si BOX N+ Measured <
Gate
NiSi
Si
BOX
N+
< Pocket >
Gate
NiSi
Si
BOX
N+
Measured
< No Pocket >
Sim. w/ pocket
Sim. no pocket

Subthreshold Swing [mV/dec]

-1.5

-1.0

V G

-0.5

[V]

0.0

S-MLD pocket InGaAs pocket TFETs

S-MLD pocket InGaAs pocket TFETs -4 10 AlO x AlO x -5 10 Pocket n+ -6
-4 10 AlO x AlO x -5 10 Pocket n+ -6 10 Tunneling -7 10
-4
10
AlO x
AlO x
-5
10
Pocket
n+
-6
10
Tunneling
-7
10
i
i
P++
P+
N+
Front
-8
P++
P+
N+
10
Control
-9
10
V g -V BT = 0.2 V to 1.5
V
TFET with pocket
Control TFET
-10
in step of 0.1 V
10
L g = 100 nm
-11
10
-1.0
-0.5
0.0
0.5
1.0
N+/p- pocket structure achieved
on InGaAs TFET.
V drain (V)
13
4
10
Control
300K
Pocket
Enhanced drive current obtained
3
CB edge
VB edge
pocket
12
10
2
due to enhanced vertical field at
gated pocket n-p+ junction.
Control
1
p-Type
n-Type
11
10
0.5
1.0
1.5
2.0
-2.0 -1.5 -1.0 -0.5 0.0 0.5
Improved gate coupling and Dit
observed.
V gate (V)
V gate (V)
PVCR
I drain (A/m
D it (#/cm 2 /eV

Simulation of TFETs

IV TFETs (Simulation)

Ge/Si pocket [1] s-Ge/s-Si [2] -3 10 Si pocket [1] Ge UTB [4] Ge pocket
Ge/Si
pocket [1]
s-Ge/s-Si [2]
-3
10
Si pocket [1]
Ge UTB [4]
Ge
pocket [1]
Ge-source
-5
10
Si NW [3]
Ge NW [3]
60 mV/dec
-7
10
Si NW [3]
Si TFET
Si PNPN [5]
Ge TFET
-9
10
Si MOSFET
Intel 32nm LP
IEDM 2009 [9]
-11
10
0.0
0.2
0.4
0.6
0.8
1.0
I drain (A/m
I drain (A/m

V gate (V)

10

10

10

10

-3

-5

-7

-9

10 -11

V gate ( V ) 10 10 10 10 - 3 - 5 - 7 -

IIIV TFETs (Simulation)

SG Pocket E g =0.36 [1] InSb GaSb-InAs UTB [7] UTB [7] GaSb-InAs NW [7]
SG Pocket
E g =0.36 [1]
InSb
GaSb-InAs
UTB [7]
UTB [7]
GaSb-InAs
NW [7]
InGaAs [8]
E g = 0.72 eV
InAs NW [6]
E g = 0.37 eV
InSb NW [7]
60 mV/dec
E g = 0.17 eV
Intel 32nm LP
IEDM 2009 [9]
0.0
0.2
0.4
0.6
0.8
1.0

V gate (V)

[1] C. Hu et al. (invited), VLSI-TSA 2008 [3] A.S. Verhulst et al., APL, 104, 064514, 2008. [5] V. Nagavarapu et al., TED, 1013, 2008. [7] M. Luisier et al., IEDM, 913, 2009.

[2] O.M. Nayfeh et al., EDL, 1074, 2008. [4] Q. Zhang et al., Solid-State Elect. 30, 2009. [6] M. Luisier et al., EDL, 602, 2009. [8] S. Mookerjea et al., IEDM, 949, 2009.

Current TFET performance

Current TFET performance P-TFET (experimental) -3 p-channel 10 32nm pFET [9] (LP) -5 60 mV/dec 10

P-TFET (experimental)

-3 p-channel 10 32nm pFET [9] (LP) -5 60 mV/dec 10 DSS Si TFET [16]
-3
p-channel
10
32nm pFET [9]
(LP)
-5
60
mV/dec
10
DSS
Si TFET [16]
-7
10
Si TFET [17]
L g = 20 m
L g = 56 nm
-9
10
SOI
TFET [14]
L g = 100 nm
-11
10
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
I drain (A/m
I drain (A/m

V gate (V)

10

10

10

10

-3

-5

-7

-9

10 -11

N-TFET (experimental) PNPN Si TFET [5] n-channel L g = 1m 60 mV/dec 32nm nFET
N-TFET (experimental)
PNPN
Si
TFET [5]
n-channel
L g = 1m
60 mV/dec
32nm nFET
Si TFET[12]
Lg = 70nm
GeOI
TFET [14]
L g = 0.4 m
In 0.7 GaAs
In 0.53 GaAs
TFET [8]
L g = 100nm
TFET [13]
L g = 100nm
Ge-source
TFET [15]
L g = 5m
0.0
0.2
0.4
0.6
0.8
1.0

V gate (V)

• Experiments show higher sub-threshold slope than simulations.

• No physical demonstration of TFET with both high Ion > 100 A/m and SS < 60 mV/dec has been demonstrated so far.

Summary

Summary • Power Constrained CMOS Scaling requires new materials and device structures to enable continued scaling.

Power Constrained CMOS Scaling requires new materials and device structures to enable continued scaling.

Nanowires:

Better short channel control than FinFETs with added degree of integration complexity

TFETs:

Band to band tunneling transport mechanism allows for sub- 60mV subthreshold slope

Vcc reduction lower power consumption

TFETs simulations show promise for Vcc reduction and additional process improvements are needed to improve device performance.