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DIGITALDESIGNTECHNOLOGY& TECHNIQUES

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INTEGRATEDCIRCUITS(IC)

Anintegratedcircuit(IC)consistscomplexelectroniccircuitriesand theirinterconnections. WilliamShockleyetal.ofBellLaboratoriesinvented transistor in 1948. Most current integrated circuits are built with MOSFET (metal oxidesemiconductorfieldeffecttransistor)transistors. ICscommerciallyavailablesinceearly1960s. Phenomenal advancement in IC design and fabrication technologies.

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MoreandmoretransistorsarepackedinachipSSI,MSI,LSI,and VLSI. Currentlymillionsoftransistorsinasinglechip.E.g.,IntelPentium IVprocessorhas40milliontransistorsusing0.13mtechnology. Integration Scale SSI MSI LSI VLSI Number ofTransistors <10 101,000 1,00010,000 >10,000 Examples Logicgates Adders,counters Multipliers Microprocessors

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Moore's Law Maximum number of transistors on a chip approximatelydoubleseveryeighteenmonths. Thispredictionhasbeenaccurateforthelastfourdecades.

On-Chip Transistor Count
1 09 1 08 1 07 1 06 1 05 1 04 1 03 1 02 1970 1980 1990 Ye a r 2000

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DIGITALICIMPLEMENTATIONALTERNATIVES

Variousimplementationofdigitallogicdesigns TraditionalofftheshelfICchips,e.g.,SSIandMSITTL,performa fixedoperationdefinedbythedevicemanufacturer. ApplicationspecificIntegratedCircuits(ASICs)arecustomizedICs whoseinternalfunctionaloperationisuserdefined. CPLD or FPGA requiresuserhardwareprogrammingtoperform thedesiredoperation. The circuitlevel design of a VLSI or ASIC chip involves circuit componentsdesign,placement,andinterconnectrouting.

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Digital Implementation Alternatives

Standard Components

VLSI Integrated Circuits

SoC
(System-on-Chip)

Applications fixed

Applications by Programming

Reconfigurable ASIC

Semicustom VLSI

Structured ASIC

Full-custom VLSI

Prefabricated Logic Gates Software Hardware Reconfigurable Masked Gate & Logic Programming Programming Array (MGA) Microchip Modules CMOS TTL ECL Microprocessor & EPROM PLA PLD ROM Channeled GA Sea-of-gates GA master slice

Standard Cell-based Design

FPGA CPLD

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Fullcustom VLSI uses circuit elements, e.g., transistors and connectionsastheprimitivecomponents. Offers a designer flexibility to optimize circuit characteristics, placement,andtheirinterconnects,aslongascertaindesignrules aresatisfied. Very time consuming for complex ICs and requires a full knowledgeoftheoperationofthecomponentsatthecircuitlevel. Semicustomdesignusesalibraryofcircuitlevelcells(standardcells) specifiedbytheirfunctionsandcharacteristics. The use of standard cells at the logic level simplifies the design process,butreducesdesignflexibility.

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Anothersemicustomstyleisthegatearraydesign. Basic components (usually basic gates) are placed on a regular structurewithinachip,andthedesignconsistsofdeterminingthe connectionsbetweenthegates.
Horizontal routing channel a a' abd (y = abc + a'c + c'd) y

b b' a'c

c c' c'd

d Vertical routing channel (z = a + b) z

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Acombinationoffullcustomandsemicustomdesignisbest,where thecriticalportionsofthesystemaredesignedusingfullcustom. ICTYPE Masklayers customized All All Some None Logiccells customized Some None None None Fabrication leadtime >2months ~2months ~1to2weeks

FullcustomVLSI StandardCellbased ASIC MaskedGateArrays FPGA/CPLD

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DIGITALDESIGNABSTRACTION

Todayscircuitsaremorecomplex. Timetomarketisoneofthecrucialfactors. Newtechniquesmustbeusedwhenwemovefromasmallscaleto largescaledesigns Digitaldesignersusetwotechniques Designabstraction Hierarchicalmodulardesign Need electronic design automation (EDA) or computeraided design(CAD)tools.

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Designabstraction

Ateachdesignlevel,theinternaldetailsofacomplexmodulemay beabstractedawayandreplacedbyablackboxviewormodel. This model contains virtually all the information needed to deal withtheblockatthenext(lower)levelofthedesignhierarchy. For all purposes, the model can be considered a black box with knowncharacteristics.Asthereisnoneedforthesystemdesigner tolookinsidethisbox,designcomplexityissubstantiallyreduced. Designabstractioniscrucialinhardwaresystemdesign. Hardwaredesignersusethesemultiplelevelsofdesignabstraction tomeetperformancegoalsforverylargedesignsandreducedesign leadtimes.

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Hierarchicalmodulardesigntechnique

The solution to working in any complex environment is modularization(divideandconquer) Thecomplexityofdesignisbrokendown(divided)intoahierarchy ofmodulesgeneral(top)tospecific(bottom). Benefitsto Focusonasinglemoduleatatime Createcustomizedlowlevelmodulesfordesignreuse.

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The topdown approach decomposes the system into smaller subsystemsuptoalevelwhichthesubsystemscanberealized. Thebottomupapproachconnectsavailablemodulestoformbigger, morecomplexsubsystems. Usually combined topdown decomposition and bottomup composition(reuseofprimitivemodules).

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Top Level

A B

Bottom Level

A B

(a)Topdownapproach (b)Bottomupapproach.

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ELECTRONICDESIGNPROCESS

System Specification

Circuit Design

Architectural Design

Physical Design

Functional Design

Fabrication

Logic Design

Packaging

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System Specification

Architectural Modelling HW/SW Partition

Hardware Spec

Software Spec

Hardware Modelling Hardware Implementation Integrated Circuits ASIC FPGA PLD

Standard Parts

Software Modelling Software Implementation

Boards and Systems

Software

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COMPUTERAIDEDDESIGN(CAD)

A.k.a Electronic Design Automation (EDA) systems. Makes design process efficient, timely, and economical. CAD tools are intended to support all phases of a digital design: Description (specification), Design (synthesis), including various optimizations to reduce cost and improve performance, Verification (by simulation or formal approach) with respect to its specification. These three phases typically require several passes to obtain a suitable implementation.

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HDL(HardwareDescriptionLanguage)

It is replacing schematic capture Today, VHDL and Verilog are the two widely used languages These two description approaches can coexist.

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SchematicDesignvs.HDLDesign

Thetraditionalwayisby(schematiccapture) logicdiagramofthe system(modulesandtheirinterconnects). An alternative is using hardwaredescription language (HDL), e.g., VHDLandVerilogarethetwolanguageswidelyusedtomodel anddesigndigitalhardware. HDLsoffer/allow Reductionindevelopmenttimeandallowsmoreexplorationof designalternatives. Descriptioninhigherlevelsofabstraction. Ameantostandardizeormethodofspecifyingadesign. Representation of sequential logic and manipulation of data type.
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D e s ig n C o n ce p t

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P a rtitio n

D e s ig n o n e m o d u le

...

D e sig n o n e m o d u le

D e fin e in te rc o n n e ctio n b e tw e e n m o d u le s

Fu n c tio n a l s im u la tio n o f co m p le te syste m No

C o rre ct? Ye s Te ch n o lo g y m a p p in g

Tim in g sim u la tio n No

C o rre ct? Ye s Im p le m e n ta tio n

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CADMethodologywithHDL

DesignentryinHDLformat(e.g. UTM VHDLmg, AlteraQuartus II). HDLbehaviouralsimulation(e.g.AldecActiveVHDL). Synthesis (e.g., Altera Quartus II, Synopsys FPGA Express), convertingthecodetoalogicnetlistfile. Functionalsimulationtoverifyfordesigncorrectness(e.g. Altera QuartusII). Implementationconvertingnetlistfiletoaphysicaldesigntothe targetimplementationtechnology. Timing Simulation the physical layout is verified with timing information.
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Design Entry VHDL DESIGN .vhd or .v (hdl source code )

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Compilation

VHDL ANALYZER (translation)

Synthesis

LOGIC SYNTHESIS

Design Constraints Technology Library Functional Simulation

Design Verification

.edif file DEVICE FITTING partitioning fitting place & route .pof file .sof file Implementation DEVICE PROGRAMMING

WAVEFORM SIMULATOR EDITOR .scf file Timing Simulation Timing diagram

Physical Design

.snf file

FPGA

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LogicSynthesis
RTL Description

Translation
Unoptimized Intermediate Representation

Logic Optimization

Design Constraints
(Timing, Area, Power)

Technology Mapping and Optimization

Technology Library
(library of available gates, and leaf-level cells)

Gate-level Netlist
(Optimized Gate-Level Representation)

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AlteraQuartusIICADTool

AsophisticatedCADsystem. Comprehensivelyanintegrateddesignenvironment(IDE)forthe designofdigitalsystems. IncludessolutionsforallphasesofFPGAbaseddesigns.

Modelsim

CosteffectiveHDLsimulationsolution IntuitiveGUIforefficientinteractivedebug Integratedprojectmanagementsimplifiesmanagingprojectdata

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EVOLVINGTRENDS
Increasing Design Density and Complexity Gate Count
Electronic System Level - ESL (systemC/ systemverilog) Behavioural or Algorithmic Synthesis Register-Transfer Level - RTL (VHDL/ Verilog)

1M

500K

100K

Simple HDL, PLA-based (eg ABEL)

Schematicbased

10K 1K

1970's

1980's

1990's

2000

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FurtherReading
1.

2.

JanM.Rabaey,A.Chandrakasan&B.Nikolic,DigitalIntegrated CircuitsADesignPerspective,2ndedition,PrenticeHall,2003, Chapter1.11.2. NeilW.E.Weste&DavidHarris,CMOSVLSIDesignACircuitsand SystemsPerspective,3rdedition,PearsonAddisonWesley,2005, Chapter1.

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