Leakage in Nanometer scale CMOS: Mechanisms and Reduction Techniques

Sagar P. Bhavsar
Electrical Department, Veermata Jijabai Technological Institute Mumbai, India
sagar.bhavsar1410@gmail.com Abstract As transistor scaling continues, threshold voltage, channel length and gate oxide thickness are continually being reduced. Though transistor delay times have decreased by more than 30% per technology generation resulting in a doubling of microprocessor performance every two years, various leakage current components are becoming increasingly significant especially in low power applications. It is of utmost importance to deal with such components effectively to enhance the stand by time of most of our gadgets which are battery powered. Leakage power consumption is becoming a critical parameter for such devices. This paper first describes the various leakage current mechanisms in a transistor and then explains various reduction techniques to tackle these leakage currents. Keywords Sub-threshold leakage, DIBL, Power Gating, Gate tunnelling, transistor stacking.
[10] Figure 3: sub-threshold current in a NMOS

I. INTRODUCTION For more than 30 years, MOS device technologies have been improving at a dramatic rate. A large part of the success of the MOS transistor is due to the fact that it can be scaled to increasingly smaller dimensions, which results in higher performance. However, power consumption is also an important parameter in todays technology as most of the devices are battery powered and prolonging the battery life is a major concern. In VLSI circuits, voltage scaling is perhaps the most effective way to reduce power consumption due to square law dependence of digital circuit active power on supply voltage. However supply voltage scaling increases gate delays unless threshold voltage of transistors is also scaled down. This threshold voltage scaling leads to an exponential rise in the sub-threshold current. Also, as technology scales down and number of devices on a chip increase, the gate oxide thickness and channel length are also continually reduced.

This further increases the leakage currents due to prominent short channel effect and tunnelling of electrons though the thin gate oxide. The effects of scaling which is increase in the amount of leakage power in the total power dissipated is shown in Figure1 . II. LEAKAGE MECHANISMS In this section we will review various leakage currents mechanisms in a MOSFET. Figure 2 depicts the major leakage currents in a NMOS transistor viz.. drain to source sub-threshold current ISUB, gate tunnelling current IG, pn reverse bias current IREV and gate induced drain leakage IGIDL. A. Sub-threshold Leakage Current : Sub-threshold current is the leakage current from the drain to the source when the transistor is OFF. It flows when the gate to source voltage Vgs is less than the threshold voltage Vth that is in the weak inversion layer. In contrast to the strong inversion layer in which drift current dominates, sub-threshold current is dominated by diffusion current of the minority carriers in the channel of the MOS device. The magnitude of the sub-threshold current is dependent on temperature, supply voltage, device size and process parameters out of which the threshold voltage plays a dominant role[5]. The various effects that change the I SUB are as follows:

[9] Figure 1: Increase in Leakage Current With Scaling

[10]Figure 3: interaction of depletion regions with the channel

1) Drain Induced Barrier Lowering (DIBL): DIBL occurs when the depletion regions of the source and the drain diffusion regions interact with each other near the channel surface. This interaction is negligible in long channel devices but becomes prominent in short channel devices. As the channel length is reduced, overlapping source and drain depletion regions cause depletion region under the inversion layer to increase[5]. The wider depletion region is accompanied by larger surface potential which attracts more

[2]Figure 4: Components of Gate Tunnelling current

Figure 5: gate Tunneling mechanisms

Decreasing the threshold voltage increases the sub-threshold electrons to the channel. Thus a smaller gate voltage is current exponentially. [11]Table 1 summarises the required to form strong inversion layer and thus V TH decreases. dependence of sub-threshold current on various parameters. This effect is further magnified by an increased drain voltage leading to wider depletion regions. This phenomena B. Gate Direct Tunneling Current. [14]Gate oxide thickness scaling has been instrumental in whch reduces Vth as Vds increases is called DIBL effect. controlling short channel effects as MOS gate dimensions have been reduced from 10m to 0.1m. Gate oxide thickness 2) Body Effect: This is a well-known effect in which the threshold voltage must be approximately linearly scaled with channel length to increases with an increase in the body/well voltage of the maintain the same amount of gate control over the channel to transistor. Reverse bias of the well to source junction widens ensure good short channel behavior. As CMOS gate lengths reduce further than the 100nm regime, the physical gate oxide the bulk depletion region resulting in a decreases Vth. thickness is projected to be less than 2.5nm [3] which induces non negligible gate tunnelling currents. Today, it is technically 3) Narrow Width Effect: This effect occurs when the channel width W is decresed feasible to manufacture 1.5 nm and thinner oxides on 200 mm to small values. With regards to threshold voltage, narrow wafers [1]. The thickness limit for SiO2 is set by gate-towidth mosfets exhibit Vth that is larger than predicted by channel tunneling leakage.Thin gate oxides coupled with a gradual channel approximation. The amount of increase is due high electric field across the gate oxide result in gate tunneling to the bulk charge outside the gate region that is ignored in current. There are two mechanisms[6] of tunnelling viz.(1) normal analysis. This is due to fringing of electric fields that Fowler-Nordheim(FN) tunneling and (2) Direct tunneling of which direct tunnelling dominates the leakage current. deplete the silicon beyond the gate region. The gate tunnelling is composed of several components as shown in [2](Figure 4): The sub-threshold current is given by [1] (1) Gate to Substrate (bulk) leakage current, I gb (2) Current between gate and source/drain extension(SDE), Igso and Igdo. (3) Gate to channel tunnelling, I gc, which in turn is partitioned between the source and drain terminals. where

[11]Table 1: Dependence of ISUB on various parameters

[10] Figure 6: Band to Band Tunneling (a)

Mechanisms for direct tunnelling include electron tunnelling in the conduction band (ECB), electron tunnelling in the valence band (EVB), and hole tunnelling in the valance band (EVB) as shown in Figure 5.The magnitude of the gate direct tunneling current increases exponentially with the gate oxide thickness tox and supply voltage VDD. C. pn Reverse bias (Band-to-Band Tunneling) Current. The BTBT leakage current, which is also called reverse bias p-n junction leakage currents, is the current flow between the source/drain (S/D) and the substrate through the parasitic reverse-biased p-n junction diode during the OFF-state MOSFET[7]. The magnitude of the diodes leakage current depends on the area of the drain diffusion and the leakage current density, which is in turn determined by the doping concentration. If both n and p regions are heavily doped, band-to-band tunneling (BTBT) dominates the pn junction leakage [5]. Higher channel doping and channel length which reduce the short channel effects actually contribute to more BTBT current. High electric field (>106 V/cm) across the reverse-biased pn junction causes significant current to flow through the junction due to tunneling of electrons from the valence band of the p region to the conduction band of the n region, as shown in Figure 6. The total voltage drop across the junction should me more than the bandgap for electron tunneling to occur. D. Gate Induced Drain Leakage. GIDL is another form of gate leakage current observed in OFF state MOSFETs. The carriers responsible for GIDL originate in the region of the drain that is overlapped by the gate. GIDL occurs when the gate is grounded and drain is at VDD. A large electric field that exists across the oxide must be supported by charge in the drain region. This charge is provided by the formation of depletion region in the drain. As the electric field becomes sufficiently large, in addition to the depletion region, an inversion region will attempt to form in the silicon. However as the minority carriers arrive at the surface to form the inversion layer, they are immediately swept laterally by the substrate. This current that flows as a result of carriers being swept is called GIDL current. Figure 7 shows the GIDL mechanism.

(b) Figure 7: Condition of the depletion region near the drain-gate overlap region of an MOS transistor when (a) surface is accumulated with low negative gate bias; and (b) n+ region is depleted or inverted with high negative gate bias.

III. LEAKAGE REDUCTION TECHNIQUES The power dissipation in a mosfet can be broadly classified into dynamic and static power. The dynamic power is dissipated during switching of the transistor and during short circuit due to non-zero rise and fall time. The static power is determined by leakage current through each transistor. However, with reduction in the threshold voltage and scaling, leakage power becomes a significant component of total power consumption. We discuss various process and circuit level techniques to reduce leakage power. A. Alternative dielectric materials The thin SiO2 faces several challenges with the scaling of the device, such as (i) increase in direct tunneling leakage current with decreasing gate oxide thickness, (ii) undesirable boron diffusion from the polysilicon gate through the oxide, (iii) poor reliability, (iv) high defect density, and (v) poor uniformity of the gate oxide. Therefore alternate dielectric materials will be a key to continue transistor scaling past 0.1nm gate dimensions. With these materials, thicker dielectric layers can be used yet the same inversion layer characteristics can be maintained. These thicker layers result in less carrier tunneling, and they permit further scaling of the effective oxide thickness. Some of the alternate dielectric materials that could be used are Si3N4/Nitride, Ta2O5, TiO2. [14]Figure 8 shows the depletion layer obtained from a device simulator for two NMOS devices with the same threshold voltage but with

[14]Figure 9: Vertical concentration doping profile for SSRW and conventional well doping profiles

[14]Figure 8: Device simulation of two devices showing depletion layers: a) N+ poly-Si and b) tungsten gate

different gate electrodes: (a) with an N+ poly-Si gate and (b) with a tungsten gate. As can be seen from this figure, the device with the tungsten gate has a significantly larger depletion layer and hence degraded short channel behavior. B. Well Engineering By changing the doping profile in the channel region, the distribution of the electric field and potential contours can be changed. The goal is to optimize the channel profile to minimize the off-state leakage while maximizing the linear and saturated drive currents. Super Steep Retrograde Wells and Halo doping are the techniques employed in well engineering. (1) Super Steep Retrograde Well(SSRW) [10]Retrograde channel doping is a vertically nonuniform, low-high channel doping. It is used to improve the SCEs and to increase surface channel mobility by creating a low surface channel concentration followed by a highly doped subsurface region. The low surface concentration increases surface channel mobility by minimizing channel impurity scattering while the highly doped subsurface region acts as a barrier against punchthrough. The retrograde profile is typically created by using a slow diffusing dopant species such as arsenic or antimony for PMOS devices and indium for NMOS devices. Figure 9 shows the vertical doping profile for an SSRW formed by an arsenic implant and by a conventional flat phosphorus well. Although the leakage current is reduced as shown in Figure 10, the drain current saturates at a lower drain bias value.

[14]Figure 10: Leakage current as a function of channel length for SSRW and uniform well transistors with the same threshold voltage

(2) Halo Doping Halo doping or non-uniform channel profile in a lateral direction was introduced below 0.25m technology node to provide another way to control the dependence of threshold voltage on channel length. For n-channel MOSFETs, more highly p-type doped regions are introduced near the two ends of the channel thereby reducing the width of the depletion regions. This reduction in the drain and source depletion width reduces the DIBL effect and sub-threshold current. These halo implants also consume larger fraction of the channel as the channel length is reduced thus reducing the threshold voltage dependence on cannel length. However, the higher doping near the channel increases BTBT and GIDL.

Figure 11: Halo Doping in NMOS

One of the significant drawbacks of power gating is that the circuits cannot retain the information in flip-flops or other

Figure 12: Power Gating Circuit

C. Power Gating and Multi threshold CMOS This technique uses additional transistors (sleep), which are inserted in series between the power supply and pull-up network (PMOS) and/or between pull-down (NMOS) network and ground to reduce the standby leakage currents. The sleep transistors are turned on when circuit are in active mode and turned off when circuits are in standby mode. Actually, on one gating transistor is sufficient to disconnect the circuit from the power rails. Because of their lower on resistance, NMOS transistors are preferred over PMOS. Moreover, the threshold voltage of sleep transistors must be more than the circuit transistors to prevent high leakage current through the sleep transistors, which makes power gating less effective. Multi threshold CMOS is used for power gating. To implement multiple threshold designs, various parameters of the MOS can be varied viz.. multiple channel doping, multiple gate oxide thickness, multiple channel length and multiple body bias; each technique with its own pros and cons. [11]In the active mode, the sleep transistor can be modeled as a resistor which will cause a voltage drop across it V sleep. This reduces the gate driving capability to Vdd Vsleep. This reduction in driving capability causes degradation in circuit performance. To overcome this problem, it is essential to lower the resistance of the transistor as much as possible. This in turn implies increasing the size (width) of the transistor, since the resistance of the transistor is inversely proportional to its width. This, however, comes at an expense of increased area and dynamic power dissipation. Conversely, a small size transistor would degrade the circuit speed. A solution to this problem would be to reduce the threshold voltage but subthreshold current and hence the leakage power would increase exponentially. Hence, there is a clear trade-off between area, power and delay metrics of a circuit for low leakage designs. Alternatively[10], instead of using high threshold sleep control transistors as MTCMOS, super cutoff CMOS (SCCMOS) technique uses low Vth transistors with an inserted gate bias generator. For the PMOS (NMOS) insertion, the gate is applied to 0V (VDD) in the active mode, and the virtual VDD (VSS) line is connected to supply VDD (VSS). In the standby mode, the gate is applied to VDD+V (VSS-V) to fully cut off the leakage current. Compared with MTCMOS, SCCMOS circuits can work at lower supply voltages.

[7]Figure 13: Sub-threshold leakage current differences among (a) a single off transistor, (b) a stack of two off-transistors, and (c) a stack of two offtransistors with reverse body bias. The barrier height increases for a stack of two off transistors shown in (b) due to both negative VGS and VDS reduction (VDS = VDD Vm < VDD), and the barrier height further increases for a stack of two off-transistors with reverse body bias shown in (c) due to the stronger body effect than in (b) (increased VSB).

static memory elements when the circuit is disconnected from the power source. This can be overcome by implementing separate state retention logic circuitry which adds to the circuit area. [4]The reduction in leakage achieved by power gating is much less significant in 90-, 65-, and 45-nm technologies. For these technologies, we find that the gate leakage of state-retention storage elements and output-holding circuits dominates the total leakage current, and these effects are not eliminated by power gating. D. Reverse Body Bias [5] One of the methods proposed for decreasing the leakage current is using reverse-body bias (RBB) to increase the threshold voltage of transistors in the STANDBY state. The threshold voltage of a transistor can be calculated from the following standard expression, | | | (| where Vt0 is the threshold voltage for Vsb=0, f is the substrate Fermi potential, and the parameter is the bodyeffect coefficient. As one can see, reverse biasing a transistor increases its threshold voltage. Reverse biasing can be done during standby, by applying a strong negative bias to the NMOS bulk via a charge pump and connecting the PMOS bulks (N wells) to the VDD rail. Because the threshold voltage changes with the square root of the reverse bias voltage, a large voltage may be necessary to get a small increase in the threshold voltage. As a result, this method becomes less effective as the supply voltage is scaled down. On the positive side, with RBB, the IC logic state is retained while in the STANDBY mode, allowing operation to resume where it suspended. Although the subthreshold current may be reduced by this technique, the increased body voltage increses the reverse bias of the source/drain and well junctions leading to more BTBT and GIDL currents.

(a)

(b) [12]Figure 14: (a)Stacking Effect in NAND Gate (b) Forced Stacking

[9]Figure 15: LECTOR Technique Figure 16: Inverter using LECTOR

penalty in delay. However, it must be noted that stacking will reduce leakage current only at certain input combinations(vectors) and exhaustively searching all 2n combinations of primary input values would lead to finding the minimum leakage state. For large circuits, a random search based technique can be used to find good input combinations.
[8]Figure 15: Leakage current as a function of number of transistors in a stack.

F. LECTOR Technique The basic idea behind our approach for reduction of leakage power is the effective stacking of transistors in the path from supply voltage to ground. The topology of a LECTOR CMOS gate is shown in Figure 15. Two LCTs are introduced between nodes N1 and N2. The gate terminal of each LCT is controlled by the source of the other, hence termed as self-controlled stacked transistors. As LCTs are self-controlled, no external circuit is needed; thereby the limitation with the sleep transistor technique has been overcome. The introduction of LCTs increases the resistance of the path from Vdd to Gnd, thus reducing the leakage current. Leakage Control TransistOR (LECTOR) technique is illustrated in detail with the case of an inverter. A LECTOR INVERTER is shown in Figure 16. A PMOS is introduced as LCT1 and a NMOS as LCT2 between N1 and N2 nodes of inverter. The output of inverter is taken from the connected drain nodes LCT1 and LCT2. The source nodes of LCT1 and LCT2 are the nodes N1 and N2 respectively of the pull-up and the pull-down logic. The gates of LCT1 and LCT2 are controlled by the potential at source terminal of LCT2 and LCT1 respectively. This connection always keeps one of the two LCTs in its near cutoff region for any input. When Vdd = 1V, input A = 0, the voltage at the node N2 is 800 mV. LCT1 cannot be completely turned OFF as the voltage is not sufficient. Hence, the LCT1 resistance will be near to but slightly lesser than its OFF resistance, allowing conduction. The resistance provided by LCT1, even though not equal to the OFF resistance, increases the resistance in the path of supply voltage to ground, thereby reducing the subthreshold leakage current, attaining reduction in leakage

E. Stacking of transistors [6] The "stacking effect" is the reduction in subthreshold current observed when multiple transistors connected in series (in a stack) are turned off. The stacking effect can be easily explained by considering the two input NAND gate as shown in Figure 14(a). When both M1 and M2 are turned off, the voltage at the intermediate node (VM) is slightly positive due to the non-zero drain leakage current [13]. With a positive source potential, VM the gate to source voltage of M1 (Vgs1) is negative, and hence the sub-threshold current reduces substantially. Moreover, since VM > 0, the body to source potential (Vbs1) of M1, is negative, resulting in an increase in the threshold voltage of M1 due to the body effect, which also reduces the sub-threshold leakage. In addition, the drain to source potential (Vdsl) of M1 decreases thereby raising the threshold voltage of M1 by reducing the DIBL and thus reducing the sub-threshold leakage. Figure 13 illustrates the increase in barrier height for leakage current in case of stacking and stacking with RBB. [12]As the depth of the stack is increased, higher leakage power saving is observed. However, in certain circuits the natural stacking of transistors do not exist. To utilize the stacking effect in such a situation a single transistor of width W is replaced by two transistors each whose width is W/2. This is called forced stacking as shown in Figure 14(b). It is necessary to note that the reduced device width for forced stacking might result in higher Vth than the nominal devices due to narrow width effects. In this case, the leakage reduction will be higher than just forced stack with a corresponding

[13]Figure 17: VCLEARIT CMOS Circuit

[4]Figure 18: Supply switching with ground collapse.

power. Similarly, when input A = 1, the voltage at the node N1 is 200 mV; hence LCT2 will be operated in near cutoff state. Two transistors are added in LECTOR technique in every path from Vdd to gnd irrespective of number of transistors in pull-up and pull-down network. Whereas, forced stacks have 100% area overhead. The loading requirement with LCTs is a constant which is much lower. Whereas, the loading requirements with forced stacks depend on number of transistors added and are huge. Hence, the performance degradation is insignificant in the case of LECTOR, and we overcome the drawback faced by forced stack technique. G. VCLEARIT Figure 17 is the topology of a generic VCLEARIT (Vlsi Cmos LEAkage ReductIon Technique)[13] CMOS circuit with sleep transistors embedded in it. There are n inputs in1.inn feeding the Pull-Up Network (PUN) as well as the Pull-Down Network (PDN). The transistors in both the PUN and PDN are standard-VT devices. The sleep circuitry consists of three transistors - two PMOS devices {P0 and P1}, and one NMOS device {N0}. Transistors P0 and N0 are standard-VT devices, while P1 is a high-VT device. P0 is connected in parallel with the PUN, one end connecting to the source (Vdd) and the other end to a common point X1. N0 is connected in parallel with the PDN, one end connecting to the Gnd and the other end to a common point X2. The high-VT transistor, P1, connects between the two common points X1 and X2 and behaves like a transmission gate. Two input signals sleep and its complement sleepbar feed transistors {P1, N0} and P0 respectively. The output of the CMOS circuit, out, is drawn from the common point X2. The working of the VCLEARIT CMOS circuit is now explained. In the normal operating mode, sleep is off and sleepbar is on. This causes transistors {P0, N0} to turn off and transistor P1 to turn on. The circuit now behaves exactly as a normal CMOS complementary circuit should. The sleep (standby) operating mode is a little more involved. In this mode, sleep is on and sleepbar is off. Hence transistors {P0, N0} turn on and transistor P1 turns off. Since P0 is on,

common point X1 is also at voltage Vdd. The PUN is now between two points at equal voltage potential (Vdd) and hence no leakage current should flow through the PUN. Similarly, N0 is on and common point X2 is grounded. The PDN is now between two points at equal voltage potential (Gnd) and hence no leakage current should flow through the PDN. Since out is connected to X2, during the sleep mode the output value will always be 0. The leakage loss occurring during the sleep mode will only be through the high-VT transistor P1 which is turned off, but, connected between points X1 and X2 that are at different voltage potentials . For any given process technology, the standard-VT transistors P0 and N0 are unit-sized devices (smallest widthto-length {W/L} ratio as defined by the technology). However, the high-VT transistor P1 needs to be sized appropriately for the VCLEARIT sleep-embedded CMOS cell to have a propagation delay comparable to that of the standard CMOS cell.

H. Supply Switching With Ground Collpase [4]Figure 18 shows the Supply switching with Ground Collapse circuit where the component of gate leakage in storage elements is reduced by dropping the supply voltage, while power gating largely eliminates subthreshold leakage in the combinational circuits. When the circuit is in active mode, the normal supply voltage (VDD) applied through supply control switches and the footer is turned on. When the PMU detects1 that the circuit is in standby state, it steers the supply control switches so that the standby supply voltage (Vsb) is applied to the circuit. At the same time, the footer is turned off and subthreshold leakage from the combinational logic is eliminated. Note that some part of the storage elements are connected to the footer, while the remaining parts bypass the footer and are directly connected to VSS. This allows us to use conventional storage elements with only slight modification, while we maintain the states in standby state. This solves the two main problems of conventional power gating: gate leakage and the overhead of the state-retention storage elements.

The voltage Vsb is considerably lower than VDD, significantly reducing the standby gate leakage since gate leakage is proportional to VDD2. The standby voltage Vsb should be chosen so that the potential that drives the logic block (the virtual supply voltage Vddv Fig. 18) is higher than the minimum voltage necessary for the storage elements to retain their states, plus some margin to guarantee state retention in the presence of noise. IV. CONCLUSIONS As CMOS devices continue to scale, leakage becomes an even more important contributor to the total power consumption. In current technologies, subthreshold and gate leakage are the dominant sources of leakage. In advanced devices, band-to-band tunneling is also likely to be a concern. To manage these leakage currents it is necessary to consider leakage management at both the process technology and circuit levels. At the process technology level, well engineering techniques such as retrograde and halo doping are used to reduce leakage and improve short channel characteristics. At the circuit level, transistor stacking, multiple Vth and Power gating and LECTOR techniques can effectively reduce the leakage current in high performance CMOS circuits. REFERENCES
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